7. Mentor Graphics PCB Design Tools Support

Transcription

1 June 2012 QII Mentor Graphics PCB Design Tools Support QII This chapter discusses how the Quartus II sotware interacts with the Mentor Graphics I/O Designer sotware and the DxDesigner sotware to provide a complete FPGA-to-board design worklow. With today s large, high-pin-count and high-speed FPGA devices, good and correct PCB design practices are essential to ensure correct system operation. The PCB design takes place concurrently with the design and programming o the FPGA. The FPGA or ASIC designer initially creates signal and pin assignments, and the board designer must correctly transer these assignments to the symbols in their system circuit schematics and board layout. As the board design progresses, Altera recommends reassigning pins to optimize the PCB layout. Ensure that you inorm the FPGA designer o the pin reassignments so that the new assignments are included in an updated placement and routing o the design. The Mentor Graphics I/O Designer sotware allows you to take advantage o the ull FPGA symbol design, creation, editing, and back-annotation low supported by the Mentor Graphics tools. This chapter covers the ollowing topics: Perorming design low between the Quartus II sotware, the Mentor Graphics I/O Designer sotware, and the DxDesigner sotware Setting up the Quartus II sotware to create the design low iles Creating an I/O Designer database project to incorporate the Quartus II sotware signal and pin assignment data Updating signal and pin assignment changes between the I/O Designer sotware and the Quartus II sotware Generating symbols in the I/O Designer sotware Creating symbols in the DxDesigner sotware rom the Quartus II sotware output iles without the use o the I/O Designer sotware This chapter is intended or board design and layout engineers who want to start the FPGA board integration while the FPGA is still in the design phase. Alternatively, the board designer can plan the FPGA pin-out and routing requirements in the Mentor Graphics tools and pass the inormation back to the Quartus II sotware or placement and routing. Part librarians can also beneit rom this chapter by learning how to use output rom the Quartus II sotware to create new library parts and symbols. The procedures in this chapter require the ollowing sotware: The Quartus II sotware version 5.1 or later DxDesigner sotware version 2004 or later 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks o Altera Corporation and registered in the U.S. Patent and Trademark Oice and in other countries. All other words and logos identiied as trademarks or service marks are the property o their respective holders as described at Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services. ISO 9001:2008 Registered Quartus II Handbook Version 13.1 June 2012 Twitter Feedback Subscribe

2 7 2 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-PCB Design Flow Mentor Graphics I/O Designer sotware (optional) To obtain and license the Mentor Graphics tools and or product inormation, support, and training, reer to the Mentor Graphics website ( FPGA-to-PCB Design Flow You can create a design low integrating an Altera FPGA design rom the Quartus II sotware, and a circuit schematic in the DxDesigner sotware. Figure 7 1 shows the design low with and without the I/O Designer sotware. Figure 7 1. Design Flow with and Without the I/O Designer Sotware Start FPGA Design Quartus II Sotware Start PCB Design Create or Change Pin Assignments Import Pin Assignments Using I/O Designer? No Run I/O Assignment Analysis I/O Designer Yes Set Up to Generate FPGA Xchange File (.x) Compile and Run EDA Netlist Writer (1).x Create or Update I/O Designer Database (.pc) Create or Change Pin Assignments Regenerate.x Generate Symbol DxDesigner Create New or Open Existing Project.pin Generate Symbol Instantiate Symbol in Schematic Forward to Board Layout Tool Board Layout Tool Layout & Route FPGA Changes? Yes Back-Annotate Changes No End Note to Figure 7 1: (1) The Quartus II sotware generates the.x in the output directory you speciy in the Board-Level page o the Settings dialog box. However, the Quartus II sotware and the I/O Designer sotware can import pin assignments rom an.x located in any directory. Altera recommends working with a backup.x to prevent overwriting existing assignments or importing invalid assignments. To perorm the design low shown in Figure 7 1, ollow these steps: 1. In the Quartus II sotware, set up the board-level assignment settings to generate an.x or symbol generation. 2. Compile your design to generate the.x and Pin-Out File (.pin). You can locate the generated.x and.pin iles in the Quartus II project directory. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

3 Chapter 7: Mentor Graphics PCB Design Tools Support 7 3 FPGA-to-PCB Design Flow 3. Create a board design with the DxDesigner sotware and the I/O Designer sotware by perorming the ollowing steps: a. Create a new I/O Designer database based on the.x and the.pin iles. b. In the I/O Designer sotware, make adjustments to signal and pin assignments. c. Regenerate the.x in the I/O Designer sotware to export the I/O Designer sotware changes to the Quartus II sotware. d. Generate a single or ractured symbol or use in the DxDesigner sotware. e. Add the symbol to the sym directory o a DxDesigner project, or speciy a new DxDesigner project with the new symbol.. Instantiate the symbol in your DxDesigner schematic and export the design to the board layout tool. g. Back-annotate pin changes created in the board layout tool to the DxDesigner sotware and back to the I/O Designer sotware and the Quartus II sotware. 4. Create a board design with the DxDesigner sotware without the I/O Designer sotware by perorming the ollowing steps: a. Create a new DxBoardLink symbol with the Symbol wizard and reerence the.pin rom the Quartus II sotware in an existing DxDesigner project. b. Instantiate the symbol in your DxDesigner schematic and export the design to a board layout tool. 1 You can update these symbols with design changes with or without the I/O Designer sotware. I you use the Mentor Graphics I/O Designer sotware and you change symbols with the DxDesigner sotware, you must reimport the symbols into I/O Designer to avoid overwriting your symbol changes. Perorming Simultaneous Switching Noise (SSN) Analysis o Your FPGA With the Quartus II sotware, you can extract pin assignment data and perorm SSN analysis o your design or designs targeting the Stratix III device amily. You can perorm SSN analysis early in the board layout stage as part o your overall pin planning process; however, you do not have to perorm SSN analysis to generate pin assignment data rom the Quartus II sotware. You can use the SSN Analyzer tool in the Quartus II sotware to optimize the pin assignments or better SSN perormance. For more inormation about the SSN Analyzer, reer to the Simultaneous Switching Noise (SSN) Analysis and Optimizations chapter in volume 2 o the Quartus II Handbook and About the SSN Analyzer in Quartus II Help. June 2012 Altera Corporation Quartus II Handbook Version 13.1

4 7 4 Chapter 7: Mentor Graphics PCB Design Tools Support Setting Up the Quartus II Sotware Setting Up the Quartus II Sotware You can transer pin and signal assignments rom the Quartus II sotware to the Mentor Graphics tools by generating.pin and.x iles (reer to Figure 7 2). The.pin is an output ile generated by the Quartus II Fitter that contains pin assignment inormation. You can use the Quartus II Pin Planner to set and change the assignments contained in the.pin and then transer the assignments to the Mentor Graphics tools. You cannot, however, import pin assignment changes rom the Mentor Graphics tools into the Quartus II sotware with the.pin. The.pin lists all used and unused pins on your selected Altera device. It also provides the ollowing basic inormation ields or each assigned pin on the device: Pin signal name and usage Pin number Signal direction I/O standard Voltage I/O bank User or Fitter-assigned The.x is an input/output ile generated by the Quartus II sotware and the I/O Designer sotware that can be imported and exported rom both programs. The.x generated by the Quartus II sotware lists only assigned pins and provides the ollowing advanced inormation ields or each pin on a device: Pin number I/O bank Signal name Signal direction I/O standard Drive strength (ma) Termination enabling Slew rate IOB delay Swap group Dierential pair type The.x generated by the I/O Designer sotware lists all pins, including unused pins. In addition to the advanced inormation ields listed above, the.x generated by the Mentor Graphics I/O Designer sotware also includes the ollowing inormation ields: Device pin name Pin set Pin set position Quartus II Handbook Version 13.1 June 2012 Altera Corporation

5 Chapter 7: Mentor Graphics PCB Design Tools Support 7 5 Setting Up the Quartus II Sotware Pin set group Super pin set group Super pin set position For more inormation about.x iles and the inormation ields added by the Mentor Graphics sotware, reer to FPGA Xchange-Format File (.x) Deinition in Quartus II Help and Mentor Graphics website ( respectively. The I/O Designer sotware can also read rom or update a Quartus II Settings File (.qs). The design low uses the.qs in a similar manner to the.x, but does not transer pin swap group inormation between the I/O Designer sotware and the Quartus II sotware. 1 Because the.qs contains additional inormation about your project that the Mentor Graphics I/O Designer sotware does not use, Altera recommends using the.x instead o the.qs. h For more inormation about the.qs, reer to Quartus II Settings File (.qs) Deinition in Quartus II Help. Generating a.pin File The Quartus II sotware automatically generates the.pin ater compiling your FPGA design or during I/O assignment analysis. To start I/O assignment analysis, on the Processing menu, point to Start and then click Start I/O Assignment Analysis. The Quartus II Fitter generates the.pin and places the ile in your Quartus II design directory with the name <project name>.pin. The Quartus II sotware cannot import assignments rom an existing.pin. Figure 7 2 shows how to generate.pin and.x iles. Figure 7 2. Generating.pin and.x Files (1) Start FPGA Design Create or Change Pin Assignments Quartus II Sotware Import Pin Assignments Run I/O Assignment Analysis Set Up to Generate.x Compile and Run EDA Netlist Writer.x.pin Note to Figure 7 2: (1) For more inormation about the ull design low, which includes the I/O Designer sotware, the DxDesigner sotware, and the board layout tool lowchart details, reer to Figure 7 1. June 2012 Altera Corporation Quartus II Handbook Version 13.1

6 7 6 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware For more inormation about pin and signal assignment transer and the iles that the Quartus II sotware can import and export, reer to the I/O Management chapter in volume 2 o the Quartus II Handbook. Generating an.x File You can generate an.x in the Quartus II sotware or symbol generation in the Mentor Graphics I/O Designer sotware. h For more inormation about generating an.x, reer to Generating FPGA Xchange-Format Files or Use with Other EDA Tools in Quartus II Help. Creating a Backup.qs To create a backup.qs o your current pin assignments, ollow these steps: 1. On the Assignments menu, click Import Assignments. The Import Assignments dialog box appears. 2. In the Import Assignments dialog box, browse to your project and turn on Copy existing assignments into <project name>.qs.bak. 3. Click OK. For more inormation about pin and signal assignment transer, and iles the Quartus II sotware can import and export, reer to the I/O Management chapter in volume 2 o the Quartus II Handbook. FPGA-to-Board Integration with the I/O Designer Sotware The Mentor Graphics I/O Designer sotware allows you to integrate your FPGA and PCB designs. Pin and signal assignment changes can be made anywhere in the design low with either the Quartus II Pin Planner or the I/O Designer sotware. The I/O Designer sotware acilitates moving these changes, as well as synthesis, placement, and routing changes, between the Quartus II sotware, an external synthesis tool (i used), and a schematic capture tool such as the DxDesigner sotware. This section describes how to use the I/O Designer sotware to transer pin and signal assignment inormation to and rom the Quartus II sotware with an.x, and how to create symbols or the DxDesigner sotware. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

7 Chapter 7: Mentor Graphics PCB Design Tools Support 7 7 FPGA-to-Board Integration with the I/O Designer Sotware Figure 7 3 shows the design low using the I/O Designer sotware. Figure 7 3. Design Flow Using the I/O Designer Sotware (1) I/O Designer Create or Update.pc Create or Change Pin Assignments.x Regenerate.x Generate Symbol DxDesigner Create New or Open Existing Project (2).pin Generate Symbol (2) Instantiate Symbol in Schematic Board Layout Tool Forward to Board Layout Tool Layout and Route FPGA Changes? Yes Back-Annotate Changes No End Notes to Figure 7 3: (1) For more inormation about the ull design low including the Quartus II sotware lowchart details, reer to Figure 7 1 on page 7 2. (2) These are DxDesigner sotware-speciic steps in the design low and are not part o the I/O Designer low. For more inormation about the I/O Designer sotware, and to obtain usage, support, and product updates, use the Help menu in the I/O Designer sotware or reer to the Mentor Graphics website ( I/O Designer Database Wizard An.pc ile stores all I/O Designer project inormation. You can create a new database incorporating inormation or the.x and.pin iles generated by the Quartus II sotware using the I/O Designer Database Wizard. You can also create a new, empty database and manually add the assignment inormation. I there is no signal or pin assignment inormation currently available, you can create an empty database containing only a selection o the target device. This action is useul i you know the signals in your design and the pins you want to assign. You can transer this inormation at a later time to the Quartus II sotware or placement and routing. June 2012 Altera Corporation Quartus II Handbook Version 13.1

8 7 8 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware You can create an I/O Designer database with only a.pin or an.x. However, i you are only using a.pin, you cannot import any I/O assignment changes made in the I/O Designer sotware back into the Quartus II sotware without irst generating an.x. Ian.x creates the I/O Designer database, the database may not contain all the available I/O assignment inormation. The.x generated by the Quartus II sotware only lists pins with assigned signals. Because the.pin lists all device pins whether signals are assigned to them or not its use, along with the.x, produces the most complete set o inormation or creating the I/O Designer database. I you skip a step in the ollowing process, you can complete the skipped step later. To return to a skipped step, on the Properties menu, click File. Tocreateanew I/O Designer database using the Database wizard, ollow these steps: 1. Start the I/O Designer sotware. The Welcome to I/O Designer dialog box appears. Select Wizard to create new database and click OK. 1 I the Welcome to I/O Designer dialog box does not appear, you can access the wizard through the menu. To access the wizard, on the File menu, click Database Wizard. 2. Click Next. The Deine HDL source ile page appears. 1 I no HDL iles are available, or i the.x contains your signal and pin assignments, you can skip Step 3 and proceed to Step 4. For more inormation about creating and using HDL iles in the Quartus II sotware, reer to the Recommended HDL Coding Styles chapter in volume 1 o the Quartus II Handbook, or reer to the I/O Designer Help. 3. I you have created a Verilog HDL or VHDL ile in your Quartus II sotware design, you can add a top-level Verilog HDL or VHDL ile in the I/O Designer sotware. Adding a ile allows you to create unctional blocks or get signal names rom your design. You must create all physical pin assignments in I/O Designer i you are not using an.x or a.pin. Click Next. The Database Name page appears. 4. In the Database Name page, type your database ile name. Click Next. The Database Location window appears. 5. Add a path to the new or an existing database in the Location ield, or browse to a database location. Click Next. The FPGA low page appears. 6. In the Vendor menu, click Altera. 7. In the Tool/Library menu, click Quartus II 5.0, or a later version o the Quartus II sotware. 8. Select the appropriate device amily, device, package, and speed (i applicable), rom the corresponding menus. Click Next. The Place and route page appears. 1 The Quartus II sotware version selections in the Tool/Library menu may not relect the version o the Quartus II sotware currently installed in your system even i you are using the latest version o the I/O Designer sotware. The I/O Designer sotware uses the version number selection in this window to identiy available or obsolete devices in that particular version o the Quartus II sotware. I you are unsure o the version to select, Quartus II Handbook Version 13.1 June 2012 Altera Corporation

9 Chapter 7: Mentor Graphics PCB Design Tools Support 7 9 FPGA-to-Board Integration with the I/O Designer Sotware use the latest version listed in the menu. I the device you are targeting does not appear in the device menu ater making this selection, the device may be new and not yet added to the I/O Designer sotware. For I/O Designer sotware updates, contact Mentor Graphics or reer to their website ( 9. In the FPGAX ile name ield, type or browse to the backup copy o the.x generated by the Quartus II sotware. 10. In the Pin report ile name ield, type or browse to the.pin generated by the Quartus II sotware. Click Next. You can also select a.qs or update. The I/O Designer sotware can update the pin assignment inormation in the.qs without aecting any other inormation in the ile. 1 You can select a.pin without selecting an.x or import. The I/O Designer sotware does not generate a.pin. To transer assignment inormation to the Quartus II sotware, select an additional ile and ile type. Altera recommends selecting an.x in addition to a.pin or transerring all the assignment inormation in the.x and.pin iles. 1 In some versions o the I/O Designer sotware, the standard ile picker may incorrectly look or a.pin instead o an.x. In this case, select All Files (*.*) rom the Save as type list and select the ile rom the list. 11. The Synthesis page appears. On the Synthesis page, you can speciy an external synthesis tool and a synthesis constraints ile or use with the tool. I you do not use an external synthesis tool, click Next. For more inormation about third-party synthesis tools, reer to Volume 3: Veriication o the Quartus II Handbook. 12. On the PCB Flow page, you can select an existing schematic project or create a new project as a symbol inormation destination. To select an existing project, select Choose existing project and click Browse ater the Project Path ield. The Select project dialog box appears. Select the project. To create a new project, in the Select project dialog box, select Create new empty project. Type the project ile name in the Name ield and browse to the location where you want to save the ile. Click OK. I you have not speciied a design tool to which you can send symbol inormation in the I/O Designer sotware, click Advanced in the PCB Flow page and select your design tool. I you select the DxDesigner sotware, you have the option to speciy a Hierarchical Occurrence Attributes (.oat) ile to import into the I/O Designer sotware. Click Next and then click Finish to create the database. 1 In I/O Designer version 2005 or later, the Update Wizard dialog box (reer to Figure 7 7 on page 7 13) appears i you are creating the database with the Database wizard. Use the Update Wizard dialog box to conirm creation o the I/O Designer database using the selected.x and.pin iles. June 2012 Altera Corporation Quartus II Handbook Version 13.1

10 7 10 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware Use the I/O Designer sotware and your newly created database to make pin assignment changes, create pin swap groups, or adjust signal and pin properties in the I/O Designer GUI (Figure 7 4). Figure 7 4. Mentor Graphics I/O Designer Main Window For more inormation about using the I/O Designer sotware and the DxDesigner sotware, reer to the Mentor Graphics website ( or reer to the I/O Designer sotware or the DxDesigner Help. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

11 Chapter 7: Mentor Graphics PCB Design Tools Support 7 11 FPGA-to-Board Integration with the I/O Designer Sotware Updating Pin Assignments rom the Quartus II Sotware As the design process continues, the FPGA designer must make changes to the logic design in the Quartus II sotware that places signals on dierent pins ater recompiling the design, or manually with the Quartus II Pin Planner. These types o changes must be carried orward to the circuit schematic and board layout tools to ensure that signals connect to the correct pins on the FPGA. Updating the.x and the.pin iles in the Quartus II sotware acilitates this low (Figure 7 5). Figure 7 5. Updating the I/O Designer Pin Assignments in the Design Flow (1) I/O Designer Create or Update.pc Create or Change Pin Assignments.x Regenerate.x.pin Generate Symbol Note to Figure 7 5: (1) For more inormation about the ull design low, which includes the Quartus II sotware, the DxDesigner sotware, and the board layout tool lowchart details, reer to Figure 7 1 on page 7 2. To update the.x in your selected output directory and the.pin in your project directory ater making changes to the design, perorm one o the ollowing tasks: compile, or start EDA Netlist Writer. You must rerun the I/O Assignment Analyzer whenever you make I/O changes in the Quartus II sotware. To rerun the I/O Assignment Analyzer, perorm one o the ollowing tasks: on the Processing menu, click Start Compilation, or on the Processing menu, click Start I/O Assignment Analysis. c For more inormation about setting up the.x and running the I/O Assignment Analyzer, reer to the I/O Management chapter in volume 2 o the Quartus II Handbook. I your I/O Designer database points to the.x generated by the Quartus II sotware instead o a backup copy o the ile, updating the ile in the Quartus II sotware overwrites any changes made to the ile by the I/O Designer sotware. I there are I/O Designer assignments in the.x that you want to preserve, create a backup copy o the ile beore updating it in the Quartus II sotware, and veriy that your I/O Designer database points to the backup copy. To point to the backup copy, perorm the steps in the ollowing section. June 2012 Altera Corporation Quartus II Handbook Version 13.1

12 7 12 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware Whenever you update the.x or the.pin in the Quartus II sotware, the I/O Designer database imports the changes. You must set up the locations or the iles in the I/O Designer sotware. 1. To set up the ile locations, on the File menu, click Properties. The project Properties dialog box appears (Figure 7 6). Figure 7 6. Project Properties Dialog Box 2. Under FPGA Xchange, click Browse to select the.x ile name and location. 3. To speciy a Pin report ile, under Place and Route, click Browse to select the.pin ile name and location. Ater you have set up these ile locations, the I/O Designer sotware monitors these iles or changes. I the.x or.pin changes during the design low, three indicators lash red in the lower right corner o the I/O Designer GUI (reer to Figure 7 4 on page 7 10). You can continue working or click on the indicators to open the I/O Designer Update Wizard dialog box. I you have made changes to your design in the Quartus II sotware that result in an updated.x or.pin and the update indicators do not lash or you have previously canceled an indicated update, manually open the Update Wizard dialog box. To open the Update Wizard dialog box, on the File menu, click Update. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

13 Chapter 7: Mentor Graphics PCB Design Tools Support 7 13 FPGA-to-Board Integration with the I/O Designer Sotware The I/O Designer Update Wizard dialog box lists the updated iles associated with the database (Figure 7 7). Figure 7 7. Update Wizard Dialog Box The paths to the updated iles have yellow exclamation points and the Status column shows Not updated, indicating that the database has not yet been updated with the newer inormation contained in the iles. A checkmark to the let o any updated ile indicates that the ile updates the database. Turn on any iles you want to use to update the I/O Designer database, and click Next. I you are not satisied with the database update, on the Edit menu, click Undo. 1 You can update the I/O Designer database using the.x and the.pin iles simultaneously. Turning on the.x and the.pin iles or update causes the Update Wizard dialog box to provide options or using assignments rom one ile or the other exclusively or merging the assignments contained in both iles into the I/O Designer database. Versions o the I/O Designer sotware older than version 2005 merge assignments contained in multiple iles. June 2012 Altera Corporation Quartus II Handbook Version 13.1

14 7 14 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware Sending Pin Assignment Changes to the Quartus II Sotware In the same way that the FPGA designer can make adjustments that aect the PCB design, the board designer can make changes to optimize signal routing and layout that must be applied to the FPGA. The FPGA designer can take these required changes back into the Quartus II sotware to reit the logic to match the adjustments to the pin-out. The I/O Designer sotware accommodates this reverse low as shown in Figure 7 8. Figure 7 8. Updating the Quartus II Pin Assignments in the Reverse Design Flow Start FPGA Design Create or Change Pin Assignments Quartus II Sotware Import Pin Assignments Run I/O Assignment Analysis Set Up to Generate.x (1) I/O Designer Create or Update.pc (1) Create or Change Pin Assignments Compile and Run EDA Netlist Writer.x Regenerate.x Generate Symbol (2) Notes to Figure 7 8: (1) These are sotware-speciic steps in the design low and are not necessary or the reverse low steps o the design. (2) For more inormation about the ull design low, which includes the complete I/O Designer sotware, the DxDesigner sotware, and the board layout tool lowchart details, reer to Figure 7 1 on page 7 2. You can make pin assignment changes directly in the I/O Designer sotware, or the sotware can automatically update changes made in a board layout tool that are back-annotated to a schematic entry program such as the DxDesigner sotware. You must update the.x to relect these updates in the Quartus II sotware. To perorm this update in the I/O Designer sotware, on the Generate menu, click FPGA Xchange File. c I your I/O Designer database points to the.x generated by the Quartus II sotware instead o a backup copy, updating the ile rom the I/O Designer sotware overwrites any changes made to the ile by the Quartus II sotware. I there are assignments rom the Quartus II sotware in the ile that you want to preserve, create a backup copy o the ile beore updating it in the I/O Designer sotware, and veriy that your I/O Designer database points to the backup copy. To point to the backup copy, perorm the steps in Updating Pin Assignments rom the Quartus II Sotware on page Quartus II Handbook Version 13.1 June 2012 Altera Corporation

15 Chapter 7: Mentor Graphics PCB Design Tools Support 7 15 FPGA-to-Board Integration with the I/O Designer Sotware You must import the updated.x into the Quartus II sotware. To import the ile, ollow these steps: 1. Start the Quartus II sotware and open your project. 2. On the Assignments menu, click Import Assignments. 3. In the File name box, click Browse and rom the Files o type list, select FPGA Xchange Files (*.x). 4. Select the.x and click Open. 5. Click OK. Protecting Assignments in the Quartus II Sotware To protect assignments in the Quartus II sotware, ollow these steps: 1. Start the Quartus II sotware. 2. On the Assignments menu, click Import Assignments. The Import Assignments dialog box appears. 3. Turn on Copy existing assignments into <project name>.qs.bak beore importing beore importing the.x. This action automatically creates a backup copy o the Quartus II constraints ile that contains all your current pin assignments. Generating Symbols or the DxDesigner Sotware Along with circuit simulation, circuit board schematic creation is one o the irst tasks required in the design o a new PCB. Schematics must understand how the PCB works, and to generate a netlist or a board layout tool or board design and routing. The I/O Designer sotware allows you to create schematic symbols based on the FPGA design exported rom the Quartus II sotware. Most FPGA devices contain hundreds o pins, requiring large schematic symbols that may not it on a single schematic page. Symbol designs in the I/O Designer sotware can be split or ractured into various unctional blocks, allowing multiple part ractures on the same schematic page or across multiple pages. In the DxDesigner sotware, these part ractures join together with the use o the HETERO attribute. The I/O Designer sotware can generate symbols or use in various Mentor Graphics schematic entry tools, and can import changes back-annotated by board layout tools to update the database and eed updates back to the Quartus II sotware with the.x. This section discusses symbol creation speciically or the DxDesigner sotware. You can create schematic symbols with the I/O Designer sotware in the ollowing ways: Manually Using the I/O Designer Symbol wizard Importing previously created symbols rom the DxDesigner sotware The I/O Designer Symbol wizard can be used as a design base that allows you to quickly create a symbol or manual editing at a later time. I you have created symbols in a DxDesigner project and want to apply a dierent FPGA design to them, you can manually import these symbols rom the DxDesigner project. To import the symbols, start the I/O Designer sotware, and on the File menu, click Import Symbol. June 2012 Altera Corporation Quartus II Handbook Version 13.1

16 7 16 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware For more inormation about importing symbols rom the DxDesigner sotware into an I/O Designer database, reer to the I/O Designer Help. Symbols created in the I/O Designer sotware are either unctional, physical (PCB), or both. Signals imported into the database, usually rom Verilog HDL or VHDL iles, are the basis o a unctional symbol. No physical device pins must be associated with the signals to generate a unctional symbol. This section ocuses on board-level PCB symbols with signals directly mapped to physical device pins through assignments in either the Quartus II Pin Planner or in the I/O Designer database. For more inormation about manually creating, importing, and editing symbols in the I/O Designer sotware, as well as the dierent types o symbols the sotware can generate, reer to the I/O Designer Help. Setting Up the I/O Designer Sotware to Work with the DxDesigner Sotware To veriy i you are set up to export symbols to a DxDesigner project, or to manually set up the I/O Designer sotware to work with the DxDesigner sotware, you must set the path to the DxDesigner executable, set the export type to DxDesigner, and set the path to a DxDesigner project directory. To set these options, ollow these steps: 1. Start the I/O Designer sotware. 2. On the Tools menu, click Preerences. The Preerences dialog box appears. 3. Click Paths, double-click on the DxDesigner executable ile path ield, and click Browse to select the location o the DxDesigner application (Figure 7 9). 4. Click Apply. Figure 7 9. Path Preerences Dialog Box 5. Click Symbol Editor and click Export. In the Export type menu, under General, select DxDesigner/PADS-Designer (Figure 7 10). Quartus II Handbook Version 13.1 June 2012 Altera Corporation

17 Chapter 7: Mentor Graphics PCB Design Tools Support 7 17 FPGA-to-Board Integration with the I/O Designer Sotware 6. Click Apply and click OK. Figure Symbol Editor Export Preerences 7. On the File menu, click Properties. The Properties dialog box appears. 8. Click the PCB Flow tab and click Path to a DxDesigner project directory. 9. Click OK. I you do not have a new DxDesigner project in the Database wizard and a DxDesigner project, you must create a new database with the DxDesigner sotware, and point the I/O Designer sotware to this new project. For more inormation about creating and working with DxDesigner projects, reer to the DxDesigner Help. Creating Symbols with the Symbol Wizard You can create, racture, and edit FPGA symbols based on Altera devices with the I/O Designer Symbol wizard. To create a symbol based on a selected Altera FPGA device, ollow these steps: 1. Start the I/O Designer sotware. June 2012 Altera Corporation Quartus II Handbook Version 13.1

18 7 18 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the I/O Designer Sotware 2. Click Symbol Wizard in the toolbar, or on the Symbol menu, click Symbol Wizard. The Symbol Wizard (1 o 6) page appears (Figure 7 11). Figure Symbol Wizard 3. On page 1 o the Symbol Wizard page, in the Symbol name ield, type the symbol name. The DEVICE and PKG_TYPE ields are automatically populated with the device and package inormation. Under Symbol type, click PCB. Under Use signals, click All. 4. Click Next. The Symbol Wizard (2 o 6) page appears. 1 I the DEVICE and PKG_TYPE ields are blank or incorrect, cancel the Symbol wizard and select the correct device inormation. On the File menu, click Properties. In the Properties window, click the FPGA Flow tab and enter the correct device inormation. 5. On page 2 o the Symbol Wizard page, select racturing options or your symbol. I you are using the Symbol wizard to edit a previously created ractured symbol, you must turn on Reuse existing ractures to preserve your current ractures. Select other options on this page as appropriate or your symbol. 6. Click Next. The Symbol Wizard (3 o 6) page appears. 7. Additional racturing options are available on page 3 o the Symbol Wizard page. Ater selecting the necessary options, click Next. The Symbol Wizard (4 o 6) page appears. 8. On page 4 o the Symbol Wizard page, select the options or the appearance o the symbols. Select the necessary options and click Next. The Symbol Wizard (5 o 6) page appears. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

19 Chapter 7: Mentor Graphics PCB Design Tools Support 7 19 FPGA-to-Board Integration with the I/O Designer Sotware 9. On page 5 o the Symbol Wizard page, deine what inormation you want to label or the entire symbol and or individual pins. Select the necessary options and click Next. The Symbol Wizard (6 o 6) page appears. 10. On the inal page o the Symbol Wizard page, add additional signals and pins that have not been placed in the symbol. Click Finish when you complete your selections. You can view your symbol and any ractures you created with the Symbol Editor (Figure 7 12). You can edit parts o the symbol, delete ractures, or rerun the Symbol wizard. Figure The I/O Designer Symbol Editor I assignments in the I/O Designer database are updated, the symbols created in the I/O Designer sotware automatically relect these changes. Assignment changes can be made in the I/O Designer sotware, with an updated.x rom the Quartus II sotware, or rom a back-annotated change in your board layout tool. Exporting Symbols to the DxDesigner Sotware Ater you have completed your symbols, export the symbols to your DxDesigner project. To generate all the ractures o a symbol, on the Generate menu, click All Symbols. To generate a symbol or the currently displayed symbol in Symbol Editor, click Current Symbol Only. The /sym directory in your DxDesigner project saves each symbol in the database as a separate ile. The symbols can be instantiated in your DxDesigner schematics. For more inormation about working with DxDesigner projects, reer to the DxDesigner Help. Scripting Support The I/O Designer sotware eatures a command line Tcl interpreter. All commands issued through the GUI in the I/O Designer sotware translate into Tcl commands run by the tool. You can view the generated Tcl commands and run scripts, or type individual commands in the I/O Designer Console window. June 2012 Altera Corporation Quartus II Handbook Version 13.1

20 7 20 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the DxDesigner Sotware This scripting support section includes commands that perorm some o the operations described in this chapter. I you want to change the.x rom which the I/O Designer sotware updates assignments, type the ollowing command at an I/O Designer Tcl prompt: set_pga_xchange_ile <ile name> You can type the ollowing command to update the I/O Designer database with assignment updates made in the Quartus II sotware ater speciying the.x: update_rom_pga_xchange_ile You can type the ollowing command to update the.x with changes made to the assignments in the I/O Designer sotware or transer back into the Quartus II sotware: generate_pga_xchange_ile You can type the ollowing command i you want to import assignment data rom a.pin created by the Quartus II sotware: set_pin_report_ile -quartus_pin <ile name> You can run the I/O Designer Symbol wizard with the ollowing command: symbolwizard You can set the DxDesigner project directory path where symbols are saved with the ollowing command: set_dx_designer_project -path <path> For more inormation about Tcl scripting and Tcl scripting with the Quartus II sotware, reer to the Tcl Scripting chapter in volume 2 o the Quartus II Handbook. For more inormation about the Tcl scripting capabilities o the I/O Designer sotware as well as a list o available commands, reer to the I/O Designer Help. FPGA-to-Board Integration with the DxDesigner Sotware The Mentor Graphics DxDesigner sotware is a design entry tool or schematic capture. You can use it to create lat circuit schematics or all the PCB design types. You can also use the DxDesigner sotware to create hierarchical schematics that acilitate design reuse and a team-based design. You can use the DxDesigner sotware in the design low alone or in conjunction with the I/O Designer sotware. However, i you use the DxDesigner sotware without the I/O Designer sotware, the design low is one-way, using only the.pin generated by the Quartus II sotware. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

21 Chapter 7: Mentor Graphics PCB Design Tools Support 7 21 FPGA-to-Board Integration with the DxDesigner Sotware You can only make signal and pin assignment changes in the Quartus II sotware and these changes relect as updated symbols in a DxDesigner schematic. You cannot back-annotate changes made in a board layout tool or in a DxDesigner symbol to the Quartus II sotware. Figure 7 13 shows the design low without the I/O Designer sotware. Figure Design Flow Without the I/O Designer Sotware (1) DxDesigner Create New or Open Existing Project.pin Generate Symbol Instantiate in Schematic Forward to Board Layout Tool Note to Figure 7 13: (1) For more inormation about the ull design low, which includes the Quartus II sotware, the I/O Designer sotware, and the board layout tool lowchart details, reer to Figure 7 1 on page 7 2. For more inormation about the DxDesigner sotware, including usage, support, training, and product updates, reer to the Mentor Graphics website ( or choose Schematic Design Help Topics in the DxDesigner Help. DxDesigner Project Settings New projects in the DxDesigner sotware are set up to create FPGA symbols by deault. However, i you are using the I/O Designer sotware with the DxDesigner sotware, you must enable the DxBoardLink Flow options or complete support and compatibility with the I/O Designer sotware. You can enable the DxBoardLink low design coniguration during or ater creating a new DxDesigner project. To enable the DxBoardLink low design coniguration when creating a new DxDesigner project, ollow these steps: 1. Start the DxDesigner sotware. June 2012 Altera Corporation Quartus II Handbook Version 13.1

22 7 22 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the DxDesigner Sotware 2. On the File menu, click New and click the Project tab. The New dialog box appears (Figure 7 14). Figure New Project Dialog Box 3. Click More. Turn on DxBoardLink (Figure 7 14). 1 To enable the DxBoardLink Flow design coniguration in an existing project, click Design Conigurations in the Design Coniguration toolbar and turn on DxBoardLink (Figure 7 15). Figure DxBoardLink Design Coniguration Quartus II Handbook Version 13.1 June 2012 Altera Corporation

23 Chapter 7: Mentor Graphics PCB Design Tools Support 7 23 FPGA-to-Board Integration with the DxDesigner Sotware DxDesigner Symbol Wizard You can create schematic symbols in the DxDesigner sotware manually or with the Symbol wizard. The DxDesigner Symbol wizard is similar to the I/O Designer Symbol wizard, but with ewer racturing options. FPGA symbols based on Altera devices can be created, ractured, and edited with the DxDesigner Symbol wizard. To start the Symbol wizard, ollow these steps: 1. Start the DxDesigner sotware. 2. Click Symbol Wizard in the toolbar, or on the File menu, click New. The New window appears. Click the File tab and create a new ile o type Symbol Wizard. 3. Type the new symbol name in the name ield and click OK. The Symbol Wizard page appears (Figure 7 16). Figure Wizard Task Selection 4. On the Wizard Task Selection page, choose to create a new symbol or modiy an existing symbol. I you are modiying an existing symbol, speciy the library path or alias, and select the existing symbol. I you are creating a new symbol, select DxBoardLink or the symbol source. The DxDesigner block type deaults to Module because the FPGA design does not have an underlying DxDesigner schematic. Choose whether or not to racture the symbol. Ater making your selections, click Next. The New Symbol and Library Name page appears. 5. On the New Symbol and Library Name page, type a name or the symbol, an overall part name or all the symbol ractures, and a library name or the new library created or this symbol. By deault, the part and library names are the same as the symbol name. Click Next. The Symbol Parameters page appears. June 2012 Altera Corporation Quartus II Handbook Version 13.1

24 7 24 Chapter 7: Mentor Graphics PCB Design Tools Support FPGA-to-Board Integration with the DxDesigner Sotware 6. On the Symbol Parameters page, speciy the appearance o the generated symbol and how it matches up with the grid you have set in your DxDesigner project schematic. Ater making your selections, click Next. The DxBoardLink Pin List Import page appears (Figure 7 17). Figure DxBoardLink Pin List Import 7. On the DxBoardLink Pin List Import page, in the FPGA vendor list, select Altera Quartus. In the Pin-Out ile to import ield, browse to and select the.pin rom your Quartus II design project directory. You can also select choices rom the Fracturing Scheme, Bus pin, and Power pin options. Ater making your selections, click Next. The Symbol Attributes page appears. 8. On the Symbol Attributes page, select to create or modiy symbol attributes or use in the DxDesigner sotware. Ater making your selections, click Next. The Pin Settings page appears. 9. On the Pin Settings page, make any inal adjustments to pin and label location and inormation. Each tabbed spreadsheet represents a racture o your symbol. Ater making your selections, click Save Symbol. Ater creating the symbol, you can examine and place any racture o the symbol in your schematic. You can locate separate iles o all the ractures you created in the library you speciied or created in the /sym directory in your DxDesigner project. You can add the symbols to your schematics or you can manually edit the symbols or with the Symbol wizard. Quartus II Handbook Version 13.1 June 2012 Altera Corporation

25 Chapter 7: Mentor Graphics PCB Design Tools Support 7 25 Conclusion 1 Symbols created in the DxDesigner sotware can be edited and updated with newer versions o the.pin generated by the Quartus II sotware. However, you cannot racture a symbol again because symbol racturing is permanent. To create new ractures or your design, create a new symbol in the Symbol wizard, and perorm the steps in DxDesigner Symbol Wizard on page Conclusion For more inormation about creating, editing, and instantiating component symbols in DxDesigner, choose Schematic Design Help Topics rom the Help menu in the DxDesigner sotware. Transerring a complex, high-pin-count FPGA design to a PCB or prototyping or manuacturing is a daunting process that can lead to errors in the PCB netlist or design, especially when multiple engineers are working on dierent parts o the project. The design worklow available when using the Quartus II sotware with the Mentor Graphics toolset assists the FPGA designer and the board designer in preventing errors and ocusing their attention on the design. Document Revision History Table 7 1. Document Revision History Table 7 1 shows the revision history or this chapter. Date Version Changes June Removed survey link. November Template update. December Template update. July Removed Reerence Document section. General style editing. Added a link to Help in Perorming Simultaneous Switching Noise (SSN) Analysis o Your FPGA. Removed Figure 8 4 on page 8 9 and Figure 8 5 on page Updated Generating an.x File. Added minor inormation about simultaneous switching noise (SSN) analysis on November Perorming Simultaneous Switching Noise (SSN) Analysis o Your FPGA. General style editing. Was chapter 6 in the release. March Removed Figures that were numbered 6-4, 6-6, 6-7, and 6-8 in v November Changed to 8½ 11 page size. No change to content. May Updated reerences. For previous versions o the Quartus II Handbook, reer to the Quartus II Handbook Archive. June 2012 Altera Corporation Quartus II Handbook Version 13.1

26 7 26 Chapter 7: Mentor Graphics PCB Design Tools Support Document Revision History Quartus II Handbook Version 13.1 June 2012 Altera Corporation