A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

C Analog Integrated Circuits and Signal Processing, 32, 249 256, 2002 2002 Kluwer Academic Publishers. Manufactured in The Netherlands. A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation TAKAHIRO INOUE, 1 HIDEO NAKANE, 1 YUUJI FUKUJU 1 AND EDGAR SÁNCHEZ-SINENCIO 2 1 Department of Electrical and Computer Engineering, Kumamoto University 2 Department of Electrical Engineering, Texas A&M University E-mail: pt-inoue@eecs.kumamoto-u.ac.jp; hid@eecs.kumamoto-u.ac.jp; yfuku@eecs.kumamoto-u.ac.jp; sanchez@ee.tamu.edu Received January 26, 2000; Revised September 11, 2000 Abstract. In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1 1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FGFloating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4 750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 µw. The proposed circuit was fabricated by a Motorola 1.2 µm double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center VDEC). Key Words: low voltage, low power, differential integrator, floating-gate MOSFET 1. Introduction Needs of low-voltage design of analog integrated circuits have been increasing recently [1]. Down-scaling into submicrons in advanced VLSI fabrication technologies demands lowering of supply voltages for digital circuits [1]. This also demands analog circuits to be operable with low supply voltages since analog signal processing circuits are usually implemented in the form of an analog-digital mixed system on a VLSI. On the other hand, development of portable telephone systems also drives analog circuits to be operable with low supply voltages since portable telephones are powered by dry batteries [2]. In order to establish low-voltage analog circuit techniques compatible with CMOS technologies, several approaches have been tried: the application of back-gate control in a MOS translinear circuit [3], the use of subthreshold operation of MOSFETs [4], etc. A current-mode CMOS circuit is a promising solution to low-voltage analog CMOS circuit design since it is theoretically operable with a supply voltage of several hundreds millivolts greater than the threshold voltage of a MOSFET [5]. In currentmode CMOS circuits, the addition of the signals has been possible only in current mode so that the addition and subtraction of signals are power consuming operations and the circuit design flexibility have been limited by its nonlinear I-V and V-I conversions. A floatinggate MOSFETFG-MOSFET) enables linear addition of signals in voltage mode and it is implementable using a standard double-poly CMOS technology [6 9]. The addition of signals by an FG-MOSFET does not consume DC power since the addition is performed by capacitive coupling [6]. The threshold voltage is linearly controllable by the gate voltage whereas the threshold control through the back-gate results in nonlinear dependence [6]. Even a depletion-type MOSFET is realizable from an enhancement-type MOSFET by applying an appropriate gate-bias voltage to the gate of the FG-MOSFET. This property is useful for realizing low-voltage analog circuit building blocks [8]. In addition, when the above functions of FG-MOSFETs

250 Inoue et al. are combined with a current-mode CMOS circuit technology, a circuit designer can enjoy both its enhanced design flexibility and its suitability to low-voltage CMOS circuit design. In this paper, a low voltage design of a fullydifferential current-mode integrator using FG- MOSFETs is presented. In Section 2, the fundamental properties of FG-MOSFETs are reviewed. And the equivalent macromodel for SPICE simulation is described. In Section 3, a design of a simple fully-differential current-mode integrator using FG- MOSFETs is presented at first. Then for this circuit, the differential and common-mode transfer functions and the common-mode rejection ratio CMRR) are derived. Section 4 shows the design example which is fabricated by a standard 1.2 µm double-poly CMOS process provided through VLSI design and education center VDEC). The HSPICE simulation results and the chip microphotograph are given and discussed. Section 5 summarizes the main conclusions. 2. Floating-Gate MOSFET 2.1. Floating-Gate MOSFET s Characteristics In this section, FG-MOSFET structure will be explained [6,8,9]. Figure 1 shows typical FG-MOSFET structure. The top figure shows the top view of the structure and the bottom figure shows the cross section along the a a line. The FG-MOSFET has the structure that the gate of a conventional MOSFET is connected to double-poly capacitors. When the total charge stored on the floating-gate is Q FG, the floating gate potential V FG is determined by the charge conservation law on the floating gate: Q FG C g1 V FG V G1 ) + C g2 V FG V G2 ) + C fb V FG V B ) + C fs V FG V S ) + C fd V FG V D ) Q C Q o 1) where V G1 and V G2 are the gate potentials of the G 1 - and the G 2 -gate, respectively, V S, V D, and V B are the source, the drain, and the bulk potential, respectively, and C fs, C fd and C fb are the floating-gate to source, the floating-gate to drain, and the floating-gate to bulk coupling capacitance, respectively, Q C is the total semiconductor charge which is the sum of the total inversion charge Q I and the total depletion charge Q B [10,11], and Q o is the total effective interface charge [11]. From equation 1), V FG is given by V FG C g1v G1 + C g2 V G2 + C fb V B + C fs V S + C fd V D C g1 + C g2 + C fb + C fs + C fd Q C + Q o + Q FG + 2) C g1 + C g2 + C fb + C fs + C fd As equation 2) shows, analog addition of voltage signals is possible in an FG-MOSFET [6,7]. Furthermore, if we regard V G2 in equation 2) as the threshold control gate, the apparent threshold voltage V th ) a is given by [6] V th ) a C g1 + C g2 + C fb + C fs + C fd V th C g1 + C g2 + C fb + C fd V S C fb V B C fd V D C g1 C g1 C g1 C g2 C g1 V G2 Q B0 + Q o + Q FG C g1 3) Fig. 1. FG-MOSFET structure. where V th is the threshold voltage of an inside MOSFET and Q B0 is the total depletion charge at V FG V S V th. As equation 3) shows, an FG-MOSFET can work even as a depletion-type MOSFET by using an appropriate second gate bias voltage. This is a favorable feature for realizing low-voltage circuits [8]. 1 It is also important to notice that, in an FG- MOSFET, the DC bias of the floating gate is supplied in an electrostatic manner. 2 The other important is-

Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator 251 sue to be considered in the design is the pre-stored charge Q FG on the floating gate. The influence of Q FG gives rise to unpredictable variations in the apparent threshold voltage. This effect can be alleviated by a factor of 20 by the charge-resetting process using UV ultraviolet) light illumination [7]. 2.2. Floating-Gate MOSFET s Macromodel Figure 2 shows the circuit symbol and the equivalent macromodel of an FG-MOSFET [9]. To implement this macromodel into HSPICE, V FG in equation 2) needs to be determined by solving a nonlinear algebraic equation in the subcircuit of HSPICE. This is because, for an n-channel FG-MOSFET, Q C in equation 2) is given by [10] Q C C ox φ t { 2 3 B S + B D B S B D B S + B D ) } 1 C ox γ 2 2n 1) C oxn 1)φ t 4) where B S 1 + i f 5) B D 1 + ir 6) i f I F I s 7) I R i r I s 8) I s µnc W φ 2 ) t ox L 2 9) C ox WLC ox 10) n 1 γ 1 2 V FG V B V TO + γ 2 + ) 2 2φ F γ 2 11) I F and I R are the forward and reverse currents [10], respectively, µ is the mobility of the carrier, n is the slope factor, W is the channel width, L is the channel length, φ t is the thermal potential, C ox is oxide capacitance per unit area, γ is the body effect factor, V TO is the zero-bias threshold voltage, and φ F is the Fermi potential [11]. When the FG-MOSFET is operated in forward saturation, we can use B S 1 + I D /I s ) and B D 1inequations 4) 11) since I D I F and I R 0 hold [10]. Equation 4) shows that Q C in equation 2) is a nonlinear function of V FG, i f, and i r whereas Q o in equation 2) is a process-dependent constant. The resistor R G in Fig. 2b) provides the controlled voltage source V FG with a very high output impedance while keeping a DC bias path with no DC voltage drop. 3 This resistor value must be sufficiently larger than 1/ωC fb ) at the lower edge frequency of interest. FG-MOSFET, and b) Equivalent macro- Fig. 2. a) Symbol of model. 2.3. DC Simulation Results of the Macromodel Figure 3 shows the HSPICE simulation results of the proposed maromodel of an FG-MOSFET. As this figure shows, V FG is linearly controllable by varying the second-gate voltage. The V G1 value at each point of intersection denoted by a closed circle) gives the apparent threshold value to the corresponding V G2 value.

252 Inoue et al. where i + i and i i are the respective small-signal input currents, v + and v are the respective small-signal input terminal voltages, C is the integrating capacitance, C pgq is the qth gate to floating-gate capacitance of the FG-MOSFET M p,v fgp is the floating-gate to bulk voltage of M p, g dsb is the output conductance of I B, g dsp is the drain-source conductance of M p, g mp is the transconductance from the floating-gate of M p, and s is the complex frequency. v fg1 and v fg2 are given by v fg1 C 1g1v + + C 1g2 v + C 1fd v+ 14) Fig. 3. V FG vs. V G1 characteristics where V G2 is a control parameter. 3. Current-Mode Fully-Differential Integrator 3.1. Small Signal Analysis Figure 4 shows the proposed low-voltage currentmode fully-differential analog CMOS integrator using FG-MOSFETs. For this circuit, the following equations hold for small signals at the respective input terminals. i + i scv + + g dsb v + + g m1 v fg1 + g ds1 v + i i + sc 1g1 v + v fg1 ) + sc 3g2 v + v fg3 ) + sc 2g2 v + v fg2 ) 12) scv + g dsb v + g m3 v fg3 + g ds3 v + sc 3g1 v v fg3 ) + sc 1g2 v v fg1 ) + sc 4g2 v v fg4 ) 13) where v fg2 C 2g2v + + C 2fd v o 15) C1g1 + C 1g2 + C 1g3 + C 1fd + C 1fs + C 1fb 16) C2g1 + C 2g2 + C 2fd + C 2fs + C 2fb 17) And v o + and vo are the respective small-signal output terminal voltages, and Cpfd, C pfs and Cpfb are the small-signal floating-gate to drain, floatinggate to source, and floating to bulk capacitances of M p, respectively, which are given by Cpfd C pfd + Q C V D ) VFG, Cpfs C pfs + Q C V S ) VFG, and Cpfb C pfb Q C V S ) VB Q C V D ) VB Q C V FG ) VB, where C pfd, C pfs, and C pfb denote the respective components independent of Q C. v fg3 and v fg4 can also be given in similar expressions. From equations 12), 13), and with the assumption that the respective paired MOSFETs are perfectly matched, we obtain i i + sc e1 + g e1 )v + sc e2 g e2 )v sc e3 vo 18) ii sc e1 + g e1 )v sc e2 g e2 )v + sc e3 v o + 19) where C e1 C + C 1g1 + C 1g2 + C 2g2 C 2 1g1 + C 1g1 C1fd + C2 1g2 C e2 C 1g2 2C1g1 + C 1 fd ) + C2 2g2 ) 20) 21) Fig. 4. Current-mode fully-differential integrator using FG-MOSFETs. C e3 C 2g2C 2fd 22)

Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator 253 C1g1 + C ) 1fd g e1 g ds1 + g dsb + g m1 23) g e2 C 1g2 g m1 24) On the other hand, the following equations hold for small signals at the respective output terminals under the condition that the respective MOSFET are perfectly matched. where i o + g ov o + g mov fg4 25) io g ovo g mov fg2 26) g o g ds2 + g dsb + g mo C 2fd g mo g m2 g m4 and g dsb is the output conductance of I B. From equations 18), 19), and 25), 26), and with the condition that v o + v o 0, we can obtain the differential gain A dif and the common-mode gain A cm as and A dif i + o i o i i + ii g mo C 2g2 sc e1 + C e2 ) + g e1 g e2 27) i + A cm o + i o i i + + ii g mo C 2g2 28) sc e1 C e2 ) + g e1 + g e2 and CMRR s j C e1 C e2 C e1 + C < 1 32) e2 As equations 31) and 32) show, very high CMRR can be realized at low frequencies by setting g e1 g e2 whereas the CMRR degrades at high frequencies. Although the signal path is immune to the commonmode noise even at high frequencies thanks to its fullydifferential structure, this poor CMRR at high frequencies causes distortion in the differential output signal when the common-mode signal level is too large. 4. Design Example 4.1. Simulation Results The performance of the current-mode fully-differential integrator in Fig. 4 is simulated by HSPICE under the following conditions. In Table 1, the W and L values are designed sizes based on the length-unit and this does not mean that such accuracy is necessary for L and W see Figs. 5 and 6). A f is the area of the floating-gate. A g1, A g2, and A g3 are the areas of the second poly-silicon electrodes which form the gates of the FG-MOSFET. In Table 2, g in, g load, and C load are the input termination conductance, the output termination conductance, and the output termination capacitance, respectively. g in is connected in parallel to the input current source. g load and C load are connected in parallel to the output terminal. Each of the current sources, I B and I B,isrealized by using a single p-channel MOSFET. 3.2. Common Mode Rejection Ratio When we define the common-mode rejection ratio CMRR) by CMRR A dif 29) A cm Equations 28), 29), and 30) give CMRR sc e1 C e2 ) + g e1 + g e2 sc e1 + C e2 ) + g e1 g 30) e2 From this equation, we obtain CMRR s j0 g e1 + g e2 g e1 g 31) e2 Table 1. FG-MOSFET geometries. M 1, M 3 M 2, M 4 Table 2. Other conditions. W 2.96 µm, L 1.48 µm, C fb 224 ff, A f 3903 µm 2, C g1 C g2 C g3 527 ff, A g1 A g2 A g3 1024 µm 2 W 2.96 µm, L 1.48 µm, C fb 148 ff, A f 2575 µm 2, C g1 C g2 527 ff, A g1 A g2 1024 µm 2 V DD 1.5 V I B 9.0 µa I B 14.5 µa g in, g load 0.76 µs C load 0.54 pf C 2pF

254 Inoue et al. Fig. 5. Differential gain response. Figures 5, 6, and 7 show the differential gain response, the differential phase response, and the total harmonic distortion THD) of the proposed circuit, respectively. The THD is calculated assuming a 16 µa p p sine-wave balanced input current and a 5% worst-case mismatch in the W/L ratios of the paired FG-MOSFETs. The simulated characteristics of this current-mode fully-differential integrator are summarized in Table 3. Table 4 shows the element-sensitivity values in the design example. As this table and Figs. 5 and 6 show, the proposed integrator is not sensitive to the element-value variations. Table 5 shows the comparison with a conventional method. From this, we can expect the proposed integrator can achieve low-voltage and low-power while keeping its performance comparable to the conventional method. Table 3. Integrator s characteristics. Supply voltage 1.5 V Frequency range 4 750 MHz for 90 ± 2.5 in phase Power consumption 70 µw THD <2.5% up to 100 MHz for a16µa p p sine-wave balanced input Table 4. Element-sensitivity values in the design example. Element x S C e1+c e2 ) x S g e1 g e2 ) x Fig. 6. Differential phase response. C 1g1 0.108 0.188 C 1g2 0.045 0.188 C 1g3 0.000 0.268 C 2g1 0.014 0.000 C 2g2 0.074 0.000 C1 fd 0.000 0.000 Table 5. Comparison with a conventional method. Proposed Method Method in Ref. [12] Supply voltage 1.5 V 3.3 V Frequency range 4 750 MHz 50 MHz Power consumption 70 µw 700 µw THD <0.13% <0.1% at 4 MHz and at i od 2I b 0.14 i od 2I B 0.138 Fabrication process 1.2 µm CMOS 2 µm CMOS Fig. 7. Total harmonic distortion under a 5% W/L-ratio mismatch. i od i + o i o.

Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator 255 Center VDEC), The University of Tokyo, in collaboration with On-Semiconductor, Nippon Motorola Ltd., Dai Nippon Printing Corp., and KYOCERA Corp. Notes 1. It is important to notice here that the transconductance from V G1 becomes κg mf, where κ C g1 /C g1 + C g2 + C fb + C fs + C fd ) and g mf is the transconductance from the floating gate. For C fb, C fs, and C fd, see subsection 3.1. 2. To make SPICE DC analysis possible, a fictitious resistive circuit is usually introduced into a DC model of an FG-MOSFET. 3. This does not mean that the floating gate needs the resistive biasing in the real world. References Fig. 8. Chip microphotograph of the integrator. 4.2. Chip Design The proposed integrator circuit is designed considering a Motorola 1.2 µm double-poly CMOS process provided through VDEC. The chip layout is made by using MAGIC. Figure 8 shows a chip microphotograph of the fabricated integrator. Experimental results are in progress and will be reported later. 5. Conclusions In this paper, a design of a low-voltage current-mode fully-differential analog CMOS integrator using FG- MOSFETs has been proposed. A simple macromodel of an FG-MOSFET has also been proposed and it was implemented into HSPICE. SPICE simulations were performed to predict the performance of the proposed integrator circuit. These simulations showed that the proposed circuit behaves as an integrator in the frequency range 4 750 MHz, The THD was less than 2.5% for a 16 µa p p sine-wave balanced input in the frequency range 4 100 MHz under a 5% W/L ratios mismatch. The DC power consumption was 70 µw. This circuit will be useful for implementing portable telephone systems. Acknowledgment The chip in this paper was fabricated in the chip fabrication program of VLSI Design and Education 1. Hu, C., Future CMOS scaling and reliability, in Proc. IEEE 815), pp. 682 689, 1993. 2. Tanimoto, H., Koyama, M. and Yoshida, Y., Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs. IEEE J. Solid-State Circuits 267), pp. 937 945, 1991. 3. Mulder, J., van der Woerd, A. C., Serdijn, W. A. and van Roermund, A. H. M., Application of the back gate in MOS weak inversion translinear circuits. IEEE Trans. Circuits Syst. I 4211), pp. 958 962, 1995. 4. Hwang, C., Bibyk, S., Ismail, M. and Lohiser, B., A very low frequency, micropower, low voltage CMOS oscillator for noncardiac pacemakers. IEEE Trans. Circuits Syst. I 4211), pp. 962 966, November 1995. 5. Hughes, J. B., Bird, N. C. and Macbeth, I. C., Switched current a new technique for analog sampled-data signal processing, in Proc. Int. Symp. Circuits Syst., Portland, USA, pp. 1584 1587, May 1989. 6. Shibata, T. and Ohmi, T., A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans. Electron Devices 396), pp. 1444 1455, 1992. 7. Yang, K. and Andreou, A. G., The multiple input floating gate MOS differential amplifier: An analog computational building block, in Proc. Int. Symp. Circuits Syst., London, UK, pp. 37 40, May 1994. 8. Ramírez-Angulo, J., Choi, S. C. and González-Altamirano, G., Low-voltage circuits building blocks using multiple-input floating-gate transistors. IEEE Trans. Circuits Syst. I 4211), pp. 971 974, November 1995. 9. Sánchez-Sinencio, E., Modern monolithic analog filters. CSSC-97 Workshop, Tampere, Finland, April 1997. 10. Cunha, A. I. A., Schneider, M. C. and Galup-Montoro, C., An explicit physical model for the long-channel MOS transistor including small-signal parameters. Solid-State Electron. 3811), pp. 1945 1952, 1995. 11. Tsividis, Y. P., Operation and Modeling of the MOS Transistor. McGraw-Hill, New York, 1987. 12. Smith, S. L. and Sánchez-Sinencio, E., Low voltage integrators for high-frequency CMOS filters using current mode techniques. IEEE Trans. Circuits Syst. II 431), pp. 39 48, 1996.

256 Inoue et al. Takahiro Inoue was born in Nobeoka, Miyazaki, Japan, in October 1946. He received the B.E. and the M.E. degree from Kumamoto University, Kumamoto, Japan, in 1969 and 1971, respectively, and the D.E. degree from Kyushu University, Fukuoka, Japan, in 1982. From 1971 to 1974, he worked as a Research Staff at Hitachi, Ltd., Yokohama, Japan. In 1975, he joined the faculty of Kumamoto University, where he is presently a professor in the Department of Electrical and Computer Engineering. Dr. Inoue was an associate editor of IEEE Transactions on Fuzzy Systems during 1994 1997. He was a member of the editorial board of the IEICE Journal in 1996 and was a member of the Technical Groups on Circuits and Systems and on Integrated Circuits, IEICE. He served as an associate editor for several special sections in the IEICE Journal and in the IEICE Transactions.He is presently serving as the Chairman of the Research Committee of Electronic Circuits, IEEJ. He was on leave to Texas A&M University and to Swiss Federal Institute of Technology ETH) during March 1997 January 1998 as a visiting scholar sponsored by the Ministry of Education, Science, Sports, and Culture, Japan. Hideo Nakane was born in Tamana, Kumamoto, Japan, in November 1974. He received the B.E. and the M.E. degree from Kumamoto University, Kumamoto, Japan, in 1997 and 1999, respectively. He is currently pursuing the D.E. degree in the same university. Since 1997, he has been engaged in low-voltage/low-power current-mode analog integrated circuit design. Yuuji Fukuju was born in Yatsushiro, Kumamoto, Japan, in December 1975. He received the B.E. and the M.E. degree from Kumamoto University, Kumamoto, Japan, in 1998 and 2000, respectively. In 2000, he joined Hitachi, Ltd. When he was a master-course student in Kumamoto University, he was engaged in the research on low-voltage/low-power analog integrated circuit design. Edgar Sánchez-Sinencio was born in Mexico City, Mexico, in October 1944. He received the degree in communications and electronic engineering Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1966, 1970, and 1973, respectively. He worked as a research assistant at the Coordinated Science Laboratory, University of Illinois 1971 1973). In 1974 he held an industrial Post Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica INAOE), Puebla, Mexico. He was a visiting professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979 1980 and 1983 1984. He is currently the TI chair professor in analog engineering at Texas A&M University and director of the Analog and Mixed Signal Center. He was the editor-in-chief of the IEEE Transactions on Circuits and System II for 1997 1999. He is coauthor of the book Switched Capacitor Circuits Van Nostrand Reinhold, 1984). He is co-editor of the book Low-Voltage/Low-Power Integrated Circuits and Systems IEEE Press, 1999). He received the 1995 Guillemin-Cauer Award for his work on Cellular Networks. He was also the co-recipient of the 1997 Darlington Award for his work on highfrequency filters. His present interests are in the area of active filter design, RF-communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member.