AUTOSAR MCALs and OS implementation

March, 2010 AUTOSAR MCALs and OS implementation Francisco Ramirez Field Applications Engineer

Designing with Freescale March, 2010 AUTOSAR MCALs and OS implementation Francisco Ramirez Field Applications Engineer

AUTOSAR Overview MCAL & OS layers CONFIGURATION METHODOLOGY TOOLS AUTOSAR/OS Design Process Flow Chart EXAMPLE

AUTomotive Operative System ARchitecture Application Software Component Application Software Component Application Layer Application Software Component Application Software Component AUTOSAR Runtime Environment (RTE) Operating System System Services Onboard Device Abstraction Memory Services Memory Hardware Abstraction Communication Services Communication Hardware Abstraction I/O Hardware Abstraction Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers Complex Driver Basic Software Microcontroller AUTOSAR Software Packages from Freescale 4

AUTOSAR partnership objectives (AUTomotive Open System ARchitecture) Manage increasing E/E complexity associated with growth in functional scope Improve flexibility for product modification, upgrade and update Improve scalability of solutions within and across product lines Improve quality and reliability of E/E systems Enable detection of errors in early design phases. 5

Worldwide, OEMs and Suppliers Participate in AUTOSAR Core Partners Associate Members CapeWare Premium Members OEM Tier 1 Semiconductors Standard Software Tools Source:, actual status at http://www.autosar.org 6

AUTOSAR An Industry Standard Phase I (2004 2006) Basic Software & RTE Specification R2.0 Improvements R2.1 Release 2.0 Release 2.1 2H 2005 1H 2006 2005 2006 2H 2006 Phase II (2007 2009) Basic Software & RTE Specification R3.0 Concepts R4.0 Specification R4.0 Improvements R4.0 Release 3.0 Release 3.1 Release 4.0 1H 2007 2H 2007 1H 2008 2H 2008 1H 2009 2007 2008 2009 2H 2009 7

AUTOSAR BSW Architecture Basic Layers Application Software Component Application Software Component Application Layer Application Software Component Application Software Component AUTOSAR Runtime Environment Services Layer ECU Abstraction Layer Microcontroller Abstraction Layer Complex Driver Basic Software Microcontroller 8

AUTOSAR BSW Architecture Sub-Layers Application Software Component Application Software Component Application Layer Application Software Component Application Software Component AUTOSAR Runtime Environment (RTE) System Services Memory Services Communication Services Operating System Onboard Device Abstraction Memory Hardware Abstraction Communication Hardware Abstraction I/O Hardware Abstraction Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers Complex Driver Basic Software Microcontroller 9

Freescale s offering is based on AUTOSAR Basic Software AUTOSAR software product packages from Freescale MCAL Operating System Application Software Component Application Software Component Application Layer Application Software Component Application Software Component AUTOSAR Runtime Environment (RTE) Operating System System Services Onboard Device Abstraction Memory Services Memory Hardware Abstraction Communication Services Communication Hardware Abstraction I/O Hardware Abstraction Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers Complex Driver Basic Software Microcontroller 10

MCAL drivers + Flash EEPROM Emulation, compliant to Autosar 2.1 or 3.0 Autosar 2.1/3.0 MCAL releases do not contain RAM Test module All components configurable in any AUTOSAR-compliant configuration tool Including plugins for EB tresos Studio Memory Hardware Abstraction Flash EEPROM Emulation AUTOSAR MCAL Product Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers ICU Driver PWM Driver ADC Driver DIO Driver GPT Driver Watchdog Driver MCU Driver Internal Flash Driver SPI Driver LIN Driver CAN Driver FlexRay Driver GPT WDT MCU Power & Clock Unit PORT Driver Flash Microcontroller Hardware SPI LIN / SCI CAN FlexRay Timer PWM ADC DIO PORTS 11

OS & System Services Application Software Component Application Software Component Application Layer Application Software Component Application Software Component AUTOSAR Runtime Environment (RTE) System Services Operating System System Services Onboard Device Abstraction Memory Services Memory Hardware Abstraction Microcontroller Communication Services Communication Hardware Abstraction I/O Hardware Abstraction Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers System Services Provide functionality to be used by all other modules, e.g., diagnostic event manager (DEM), diagnostic error tracer (DET), operating system (OS) OS is a system service that is MCU dependent, i.e., has to be optimized for each MCU Other modules can be application and/or hardware dependent (e.g., ECU state manager) Complex Driver Basic Software (BSW) Operating System Communication Manager ECU State Manager CRC Library Function Inhibition Manager Watchdog Manager Diagnostic Event Manager Diagnostic Error Tracer AUTOSAR OS is OSEK/VDX OS plus: New core features Software and hardware counters Schedule tables with time synchronisation Stack monitoring Protection features Timing protection, memory protection and service protection OS applications, trusted and non-trusted code Protection hook 12

AUTOSAR OS Scalability Classes 1 4 Scalability Class 1 Scalability Class 2 Scalability Class 3 Scalability Class 4 OSEK OS (all conformance classes) Counter Interface Schedule Tables Stack Monitoring Protection Hook Timing Protection Global Time/Synchronization Support Memory Protection OS Applications Service Protection CallTrustedFunction 13

ElektroBit (EB) Tresos Studio EB tresos Studio is a easy-to-use tool for ECU standard software configuration, validation and code generation Full support for the AUTOSAR standard Full support for the Freescale AUTOSAR software and the EB tresos AutoCore Integrated, graphical user interface Based upon Eclipse and open standards Online-help and parameter-specific help 14

Parameter Description Files EPD/EPC Legend read EPD BSW Module Description BSW Module Configuration AUTOSAR Files Elektrobit Files Generated Files EB tresos Studio Configurator write EPC read read write c, h EB tresos Studio Generator Generated Code read c, h templates Code Templates Source: Elektrobit 15

Parameter Description Files XDM Legend EPD convert read XDM BSW Module Description import/ export EPC BSW Module Configuration AUTOSAR Files Elektrobit Files Generated Files EB tresos Studio Configurator write XDM read read write c, h EB tresos Studio Generator Generated Code read c, h templates Code Templates Source: Elektrobit 16

Main Window Project Browser Editor Node Outline Error & Problem Messages Parameter Information Source: Elektrobit 17

Parameter Description Files XDM read EPD XDM BSW Module Description BSW Module Configuration Legend AUTOSAR Files Elektrobit Files Generated Files EB tresos Studio Config Editor write EPC XDM read read write c, h XDM is a proprietary format (EB) providing enhanced usability features during configuration with EB tresos Studio. EB tresos Studio Generator read Generated Code c, h templates Code Templates Source: Elektrobit 18

Parameter Description Files EPD/EPC read EPD EPD BSW Module Description BSW Module Configuration Legend AUTOSAR Files Elektrobit Files Generated Files Any other AUTOSAR-compliant Config Editor write EPC EPC read read write c, h EPD is the standard AUTOSAR format. This allows the Freescale Autosar software to be used with any other Autosar GCE tool. EB tresos Studio Generator read Generated Code c, h templates Code Templates 19

March, 2010 New Power Architecture Solutions for Automotive Body Electronics Francisco Ramirez Field Applications Engineer

March, 2010 New Power Architecture: MPC560X MPC560XB Bolero for Body Electronics

Power Architecture : e200 Core Key Characteristics Programming Model Auxiliary Processing Unit: Signal Processing Engine Memory Management Unit Cache Common Microcontroller System Features Direct Memory Access Crossbar Memory Protection Unit Phase Lock Loop Power Control and Peripheral Clock Generation Boot Assist Module Memories Pad Configuration Interrupts Peripheral Example Overviews Timed I/O: Timers Analog I/O: eqadc, ADC Serial I/O: LIN, CAN, FlexRAY Bolero Unique Features ADC diagram block/functionality Lightning PWM Channels Bolero Roadmaps

Enabling More Integration Body Controller (interior features + lighting) Benefits: Less modules, less cables Reduced weight, fuel efficiency Reduced manufacturing costs Better quality Lower total cost of ownership CAN Gateway Fuses Box Replacement Central Body Domain Controller RF Receiver (key, tires) 23

Application Performance / Integration MPC5510 e200z1, edma e200z0 optional 48-66-80MHz 144/176LQFP 208MAPBGA 130nm Available In Design Planned Proposed MPC5517x 1.5M Flash, 80 KB RAM Up to 6 CAN, FlexRay, MLB MPC5516x 1M Flash, 64KB RAM Up to 6 CAN, FlexRay, MLB MPC5515S 768KB Flash, 48 KB RAM 5 CAN, 6 esci MPC5514E/G 512KB Flash 32K/64K RAM MPC5604B/C 512KB Flash, 64KB Data flash 3/6 CAN, 32/48KB RAM 32-bit Body Electronics MCU Roadmap MPC5668G 2MB Flash, 592KB RAM FlexRay, Ethernet, MediaLB MPC564xB/C e200z4 or e200z4+z0 80-120MHz 90nm MPC5668E 2MB Flash, 128KB RAM, 6 CAN, 12LIN MPC5607B (w/ edma) 1.5M Flash, 64KB Data Flash 6 CAN, 96KB RAM MPC5606B (w/ edma) 1M Flash, 64KB Data Flash 6 CAN, 80KB RAM MPC5605B (w/ edma) 768KB Flash, 64KB Data Flash 6 CAN, 64KB RAM MPC5646B/C 3MB Flash, up to 256K RAM, 6 CAN, Flexray, Ethernet option MPC5668G/E High performance gateways Dual-core 200z6+z0, 116MHz @105C 208MAPBGA MPC560xB/C e200z0 32, 48, 64MHz 64/100/144/176LQFP 90nm 90nm MPC5603B/C 384KB Flash, 64KB Data flash 3/6 CAN, 28-40KB RAM MPC5602B/C 256KB Flash, 64KB Data flash 3/6 CAN, 24-32KB RAM MPC5602D 256K Flash, 64KB Data Flash 1 CAN, 20KB RAM MPC5601D 128K Flash, 64KB Data Flash 1 CAN, 16KB RAM NOW 2010 2011 24

MPC5604B (Bolero 512K) System Integration VReg PIT 4ch 32b Oscillator FMPLL Interrupt Controller MCM Power Mgt Crossbar Masters PowerPC e200z0 Core Debug JTAG Nexus 2+ CORE PowerPC e200z0 core running 48-64MHz VLE ISA instruction set for superior code density Vectored interrupt controller Memory Protection Unit with 8 regions, 32byte granularity MEMORY 512Kbyte embedded program Flash, 64KByte data flash 64Kbyte embedded data Flash (for EE Emulation) Up to 64MHz non-sequential access with 2WS ECC-enabled array with error detect/correct 32Kbyte SRAM (single cycle access, ECC-enabled) emioslite 6ch IC/OC 50ch PWM I/O Bridge CTU CROSSBAR SWITCH Memory Protection Unit (MPU) 512K Flash 32K SRAM Crossbar Slaves Communications I/O System 36 ch ADC 10bit 64K Data Flash 3 FlexCAN Standby RAM 4 LINFlex 3 DSPI 1 I2C Boot Assist Module (BAM) COMMUNICATIONS 3x enhanced FlexCAN 64 Message Buffers each, full CAN 2.0 spec 4x LINFlex 3x DSPI, 8-16 bits wide & chip selects 1x I²C ANALOG 5V ADC 10-bit resolution TIMED I/O 16-bit emios module OTHER CTU (Cross Triggering Unit) to sync ADC with PWM Channels Debug: Nexus 2+ I/O: 5V I/O, high flexibility with selecting GPIO functionality Packages: 100LQFP, 144LQFP, 208MAPBGA (Development only) Boot Assist Module for production and bench programming 25

System Integration VReg PIT 4ch 32b Oscillator FMPLL Interrupt Controller emios 64ch, 16 bit MCM Power Mgt I/O Bridge Up to 52 ch ADC 16x12bit, 36x10 Bit Crossbar Masters PowerPC e200z0 Core CROSSBAR SWITCH Memory Protection Unit (MPU) 1.5M Flash 64K Data Flash 96K SRAM Crossbar Slaves Communications I/O System CTU 6 FlexCAN Standby RAM 10 LINFlex DMA 6 DSPI 1 I2C Debug JTAG Nexus 2+ Boot Assist Module (BAM) MPC5607 (Bolero 1.5M) CORE PowerPC e200z0 core running at up to 64MHz VLE ISA instruction set for superior code density Vectored interrupt controller Memory Protection Unit with 16 regions, 32byte granularity MEMORY 1.5M byte embedded program Flash 64Kbyte embedded data Flash (for EE Emulation) Up to 64MHz non-sequential access with 2WS ECC-enabled array with error detect/correct 96Kbyte SRAM (single cycle access, ECC-enabled) COMMUNICATIONS 6x enhanced FlexCAN 64 Message Buffers each, full CAN 2.0 spec 10 x LINFlex 6 x DSPI, 8-16 bits wide & chip selects 1 x I²C ANALOG Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution, CTU (Cross Triggering Unit) to sync with PWM Channels TIMED I/O 16-bit emios module, 64ch. Counter / OPWM / IC/OC 10ch O(I)PWM / OPWFMCB / IC/OC 7ch O(I)PWM / IC/OC - 19 ch OPWM / ICOC 28 ch OTHER 32 Channel DMA Controller Debug: Nexus 2+ I/O: 5V I/O, high flexibility with selecting GPIO functionality Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA (TBD) Boot Assist Module for production and bench programming 26

Power Architecture: e200 Core

Power Architecture e200 Core Family Key Characteristics Synthesizable Power Architecture cores with Power ISA 2.03 Additional supported instructions SPE Signal Processing Engine: DSP, SIMD and vector floating point VLE Variable Length Encoding: for improved code footprint Standard interfaces: AMBA bus, which has a large following in the licensable-ip community Nexus debug interface (ISTO 5001) Leverages Power Architecture tools and software ecosystem Hardware and software development tools are available. Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments.

Highly modular core add DSP & FP, cache, pre-fetch buffers packaging, module library, peripherals single and dual core options Cost reduction through maximum re-use same tools, drivers, application code cross-application platform with 1 core 60MHz 2 x 300MHz, 256K 8MB Z0/Z1 First embedded PowerPC processor Separate products for embedded and computing markets Z3/Vector 32 bit PowerPC Book Single-issue, 4-stage 32-Bit AMBA AHB bus SPE and SPFP APUs 16-entry unified MMU Optional Harvard cache (4 KB 16K) Z4 32 bit PowerPC Book Single-issue, 5-stage 32-Bit AMBA AHB bus SPE and SPFP APUs 16-entry unified MMU Optional Harvard cache (4 KB 16K) Increased Integration / Advanced Process Technology Z6 32 bit PowerPC Book E Single-issue, 7-stage 64 bit AMBA AHB Bus EFP and SPE APUs Unified 32KB Cache 8-way set-associative 32-entry unified MMU e200 Power Core Platform Z7 preliminary 32 bit PowerPC Book E Dual-issue, 10 stage 64/128-Bit bus Single Precision FP and SPE SIMD APUs Harvard L1 caches and optional L2 Large MMU Software Compatible Architecture * Future Versions Next Generation 64 bit, 3+ GHz (Power Architecture driven High Performance Applications) 86XX Performance Original Slide by J. Shockey

e200z Core Roadmap 10-stage pipeline Up to 32k cache Dual Issue /VLE Performance / Features 7-stage pipeline Up to 32k cache FPU e200z6 144MHz SIMD Powertrain & Chassis 4-stage pipeline FPU VLE e200z3 80MHz SIMD 7-stage pipeline Up to 32k cache FPU VLE e200z6 200MHz SIMD 4-stage pipeline VLE e200z1 80MHz 5-stage pipeline Up to 16k cache Dual Issue / VLE FPU e200z4 120MHz SIMD 4-stage pipeline VLE Only e200z0 80MHz FPU e200z7 266MHz SIMD Body Electronics 2004 2005 2006 2007 30 This document contains forward-looking statements based on current expectations, forecast and assumptions of Freescale that involves risk and uncertainties. Forward looking statements are subject to risk and uncertainties associated with Freescale business that could cause actual results to vary materially from those stated or implied by such forward-looking statements.

Dhrystone Comparative Performance Core DMIPS/MHz e200 z4d 2.79 e200 z7 2.42 e500 v2 2.40 SH-2A 2.40 QCOM Scorpion 2.10 Cortex A8 2.00 Cortex A9 2.00 IBM 464 2.00 e300 1.99 MIPS 74k 1.80 Cortex R4 1.60 e200 z1 & z3 1.60 MIPS 4K 1.50 Tri-Core 1.50 SH-2 1.3 Cortex M3 1.25

Variable Length Encoding (VLE) VLE is an extension to the existing 32bit Power Book E instruction set. VLE instruction set includes 16-bit and 32-bit VLE instructions VLE and Power code can be mixed in the application by using separate MMU pages 1.2 1 0.8 0.6 0.4 0.2 Power ISA VLE The e200z0 core only uses VLE instructions 0 Code Size Performance

Auxiliary Processing Unit: Signal Processing Engine (SPE) SPE is an Auxillary Processing Unit (APU) that provides signal processing capabilities Aimed specifically at DSP operations, such as filters and FFTs Key SPE Features: Single Instruction Multiple Data (SIMD) functionality Includes Embedded Floating Point APU Support for the following data types: 32-bit fractional 32-bit integer Single precision floating point 16-bit fractional 16-bit integer

Single Instruction Multiple Data (SIMD) Ordinary PowerPC instructions operate as usual just on the bottom 32 bits, leaving the top 32 bits untouched Classic PowerPC: add r5, r3, r4 0 31 32 63 0 31 32 63 ra 13 21 r3 rb 85 46 r4 op op add 77 67 evfs* add r5, r3, r4 rd r5 SPE extends the ordinary Book E 32 bit registers to be 64 bits in size SPE instructions do the specified operation on the bottom 32 bits and, in parallel, on the top 32 bits. So two independent operations are executed by the one instruction 0 31 32 63 0 31 32 63 ra 13 21 r3 rb 85 46 r4 rd op77 op 34 r5 evfs* Register File SPE: evadd r5, r3, r4 0 31 32 63 0 31 32 63 ra 13 21 r3 rb 85 46 r4 op op add add 98 67 evfs* evadd r5, r3, r4 rd r5

Memory Management Unit Core Effective virtual Address (32-bits) Memory Management Unit (MMU) MMU TLB TLB Entry 0 TLB Entry 1 TLB Entry 2 TLB Entry 3 TLB Entry 31 Real Address (32-bits) Physical Memory Yellow: Flash Green: Peripherals Blue: SRAM Page0 Page1 Memory must be defined in the MMU for Core access MMU does not control accesses from EBI, edma, or NEXUS Nexus may read MMU & change the settings on the fly (in some devices) Memory space is divided into up to 32 pages, each having: Defined size (1k, 2k, 4K, 8k,16K, 64K, 256K, 1M ) Address base, Effective Page Number (EPN), which is translated to a different base, Real Page Number (RPN) Permission control Memory and cache attributes Each page is created by an entry in the Translation Lookaside Buffer (TLB) ECU calibration does not require any change in the software As required by OEMs same build is used for ECU calibration e200 MMU is Autosar compatible. Page2 cal_var Page3

Calibration Example Using The MMU Use the MMU to switch between any number of calibration banks. MMU solution requires a very small amount of core intervention when switching banks. MMU selects which of many calibrations the software sees at a fixed address Effective Address Calibration MMU Physical Address Internal FLASH Calibration #1 Internal FLASH Calibration #2 External SRAM Calibration #3 External SRAM Calibration #4 External Memory Emulator Calibrations #5&6

Common Microcontroller System Features

Architecture Performance Support The crossbar switch allows two bus masters to simultaneously connect to different bus slaves Example snapshot In addition, e200z1 has a private connection to flash module for instructions The edma offloads the processor tasks for data movement, especially for communications Optional second processor, e200z0 CPU 1 Instructions e200z1 e200z0 Crossbar Flash SRAM edma Controller IP Bus i/f to peripherals and I/Os Smart peripherals Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM7 is the trademark of ARM Limited. Freescale Semiconductor, Inc. 2004

Simultaneous transfers between independent master and slave ports Crossbar Switch Programmable master priorities on a perslave port basis Fixed and Round-Robin arbitration priorities Parking on slave ports Explicit, park on last master to access that slave and none (low power parking) 32-bit internal address, 32 or 64-bit internal data paths Master Ports Core complex Load/Store port Core complex Instruction port DMAs FlexRay EBI AHB Slave Ports Flash SRAM Peripheral Bridge (AIPS)

Memory Protection Unit Overview Unlike MMU, provides access control for DMA, EBI, and FlexRAY, in addition to core accesses Full compliance with Autosar Class 4 Protects slaves against erroneous master accesses Supports concurrent accesses between masters Splits the memory space into regions 8 or 16 regions with a granularity of up minimal 32 bytes Assigns access rights for each region For supervisor (read, write, execute) For user mode (read, write, execute) Flexray: read and write attributes only Regions can be assigned per task or group of tasks Patented scheme allowing static MPU configuration in safety systems 2 supported MPU schemes MPU entries reload on task change Fully static configuration Memory Protection Unit (MPU) Masters Master# (optional PID) Transfer Error Crossbar MPU Slaves

Up to 64 DMA channels implemented Each channel source is selected by Software - Sources are NOT pre-assigned to peripherals Hardware - Sources are not pre-assigned to peripherals edma Features One DMA engine services all channels Devices may have multiple DMA engines DMA requests can come from: Peripheral (e.g., eqadc) Software command Programmable Interrupt Timer (PIT) Transfer Control Descriptors define each channel s transfer Optional generation of interrupt request upon Reaching half of the transfer After completion of the transfer

Software Selection Of A DMA Source Disabled Source # 0 Source # 1 Peripherals Always Enabled Source # 2... Source # n # n+1.. # 32 or. 64 DMA Channel Mux DMA Channel #0 DMA Channel #1... DMA Channel # 15 Software selects which DMA sources connect to the 16 DMA channels DMA request for channels can be initiated by: A peripheral (example: ADC conversion result ready to be put into queue) Software (example: set a bit to initiate a block move) Periodic Interval Timer (example: enable periodic transmit of latest pending SPI data) Periodic Interval Timer available to 8 of the 16 channels (DMA channel 0 to 7)

DMA Channel Mux Sources (shown for MPC5604P) DMA Mux Source Input # # sources DMA Source 0 1 Channel Disabled 1 8 8 4 DSPIs: TX and RX 9-13 5 CTU, CTU FIFO 1:5 14, 15 2 FlexPWM 0: WR, RD 16-19 4 etimer 0 channels 0:1 and etimer 1 channels 0:1 20 21 2 ADC 0:1 22-30 Always Enabled -With PIT to generate periodic DMA - w/o PIT for continuous DMA transfer

Lock Detect Loss of Clock Detect FMPLL Block Diagram (MPC563xM) LOCK Loss Of Clock FM Mod. Control f ref (xtal) PRE DIV PFD (Phase Freq. Detector) Charge Pump Filter ICO (Current Controlled Osc.) f ico RFD fsys feedbackclk MFD fsys = fref x (MFD + 4) ---------------------------- (PREDIV + 1) x 2 RFD Default Fsys = 1.5 x Fextclk unless PLLCFG2 = 1, then Fsys = 0.75 x Fextclk

Peripheral Clock Generation To conserve power, many peripherals do not have a clock signal after reset. A bus error will occur when attempting to access peripherals without clocks. Software must initialize in two ways: 1. Peripheral clock gating on a mode basis. Based on ME_RUN_PCx, ME_LPx and various ME_PCTLx registers 2. Clock generation on a peripheral or peripheral set basis.

Peripheral Clock Generation Examples

Boot Assist Module (BAM) Overview The Boot Assist Module is a block of read-only memory which assists the boot process. Typically it is executed after RESET Features: Locates and detects application boot code Searches for a BOOTID value in pre-assigned locations in flash Can allow serial download of code into internal SRAM for execution Uses FlexCAN or esci for MPC563xM Uses FlexCAN or LINFlex for MPC560xB / P / S Can allow boot from external flash (if external bus is implemented) If an MMU is implemented, MMU pages are configured processor resources Censorship protection for internal flash module

SIU Pad Configuration Each pad has its own 16-bit Pad Configuration Register (PCR) Registers SIU_PCR0 to SIU_PCR230 Register number corresponds to GPIO number Not all pads have all bit fields BAM will alter defaults for some pads Software must configure pin assignments to be other than their common default GPIO assignment. MPC56xxB / P / S also includes registers to select which pin input is connected to which peripheral. Allows a single input to be routed to 2 peripherals Pad Selection For Multiplexed Inputs (SIU_PSMIx)

Pad Configuration Example: Assign EMIOS Channel 0 MPC5553/MPC5554 Microcontroller Reference Manual, Table 2-1 MPC5553 Signal Properties: Primary Function: EMIOS chan. 0 Alternate Function: ETPU A chan. 0 [reserved] GPIO: GPIO[179] 11 10 01 00 Pad SIU_PCR179[PA] (Pad Assignment can be 1, 2 or 3 bits)

Bit Field Name Symbol Description SIU_PCR: Pad Configuration Registers Pad Assignment PA Assigns pad as GPIO (common default), alternate or primary function Output Buffer Enable OBE If pad can be input or output, enables as output. Input Buffer Enable IBE If pad can be input or output, enables as input. Tip: If pad is configured as an output, the pad state can be read when IBE is also enabled.. Drive Strength Control DSC** Output drive strength of 10, 20, 30 or 50 pf Open Drain output Enable ODE Output has open drain Input Hysteresis HYS Input has Hysteresis (for noise, but slower) Slew Rate Control SRC** Output has minimum, medium or max. slew rate Reset default is min. slew rate (slowest transition) Weak Pull down/up Enable WPE* Enables selected pull down/up Weak Pull down/up Select WPS* 0= pull down, 1 = pull up * *WPE and WPS override initial pullup/down configured at reset by WKCFG for emios/etpu. ** DSC applies to fast pad types (example: external bus), SRC applies to medium & slow

Interrupt Generation Interrupts are handled between: The Interrupt Controller (INTC) The Core The Interrupt controller provides a mechanism to service non core based interrupts Software selects one of 16 priority levels for each interrupt Interrupts are serviced in one of 2 ways: Software vector mode (which conforms to Power Architecture technology) Hardware vector mode

Peripheral Example Overviews

PIT Timer Module Independent AutoSAR system timers Down counting with auto reload 32 bits wide Most channels Clocked by system clock 1 channel clocked by crystal clock Operates in stop mode Used to wake-up CPU Interrupt and trigger on each channel Ideal tick source for operating system Channel outputs can trigger eqadc queues

emios Timer Module 24 Independent Channels Unified all have same output and input time function (mode) capability 24-bit wide counter buses Global: Counter bus A Driven by channel 23 or etpua or etpub Local: Counter buses B, C, D Driven by channels 0, 8, 16 for channels 0-7, 8-15, 16-23 Internal: Internal Counter inside the channel. Output Pins can be disabled by input or output events on other emios Channels Any one of channels 8, 9, 10 or 11 disables any user selected emios emios Channels 8-11, 20-23 provide disable control to 8 groups of 8 channels on etpua, etpub Bus A etpua etpub Bus B Bus C Bus D Chan 0 Chan 7 Chan 8-11 Chan 8 Chan 15 Chan 16 Chan 23 Chan 20-23 Output disable control to etpua, etpub

Timer Mode Modulus Counter 1,2 (does not use pin) emios Modes of Operation Input Channel Modes Single Action Input Capture 1 Input Pulse Width Measurement 1 Note: As a supplement to the reference Input Period Measurement 1 manual, see EB651: MPC5500 emios Pulse/Edge Accumulation Avoiding Unexpected Module Operation Pulse Edge Counting Quadrature Decode Windowed Programmable Time Accumulation Modulus Counter Output Channel Modes Single Action Output Compare 1 Double Action Output Compare 1 Output Pulse Width Modulation 1,2 Output Pulse Width and Frequency Modulation 2 Center Aligned Output Pulse Width Modulation with dead time insertion 2 1 Mode supported on MPC500 2 Buffered mode versions avaialble except for MPC5554 and MPC5552 input modes

eqadc Features Two independent on - chip ADC s 12 bit resolution Single-ended signal range from 0 to 5V 4 pairs of differential analog input channels Sample times of 2 (default), 8, 64 or 128 ADC clock cycles Right- justified unsigned and signed result formats Provides time stamp information when requested Target Accuracy Max. Rate ADC_CLK Conversion Type Min. # of ADC_CLKs Conversion Rate Conversion Time 10 bit 6 MHz Differential 15 400 K /sec 2.5 usec Single Ended 16 375 K / sec 2.67 usec 8 bit 12 MHz Differential 15 800 K /sec 1.25 usec Single Ended 16 750 K /sec 1.33 usec

Trigger (0) eqadc Command/Data Flow Command Queue 0 DMA Push Reg. 0 Command FIFO 0 Trigger (1) A/D BN 0 Result FIFO 0 Pop Reg. 0 DMA Result Queue 0 Command Queue 1 DMA Push Reg. 1 Command FIFO 1 Result FIFO 1 Pop Reg. 1 DMA Result Queue 1 O O O O O O Trigger (5) A/D BN 1 O O O O O O Command Queue 5 DMA Push Reg. 5 Command FIFO 5 Result FIFO 5 Pop Reg. 5 DMA Result Queue 5 Each CFIFO and RFIFO are hard-wired to individual DMA channels Each result can return through any RFIFO

Features: Supports LIN protocol version 1.3, and 2.0 UART mode 7/8-bit data, parity/no-parity, 1 or 2 stop bit MSB / LSB first LIN Management Initialization, Normal and Sleep Maskable interrupts Wake-up event on dominant bit detection 8-bit counter for time-out management Software-efficient data buffer interface mapping at a unique address space LIN Master Mode Autonomous message handling Once the software has triggered the header transmission, no further intervention needed: until the next header transmission request in transmission mode until the checksum reception in reception mode LIN Slave Mode Software intervention needed only to: Trigger transmission or reception depending on the identifier, Fill the buffer (transmission) or get data from buffer (reception). If Filter mode is available for Slave mode (option), Software intervention needed only to: Fill the buffer in transmission, Get data from buffer in reception. UART mode Full duplex; Character length 7 & 8 bits; opt parity, 1 or 2 stop bits 4 byte Tx and Rx buffers 3 interrupt sources : error, Rx, Tx MSB / LSB first Transmit/receive data inversion at pin level LINFlex(LIN and UART) SCI / LIN

FlexCAN: Architecture with MPC5510 FlexCAN CONTROL 20 IRQs 64 Transmit/Receive Message Buffers CANTx CANRx SERIAL BUFFERS Tx Shifter Rx Shifter Transparent to user Rx ID Mask 0 Rx ID Mask 63 Each buffer has it s own receive ID mask (up to 3 diff IDs)... 29 29 BUFFER 13 BUFFER 14 BUFFER 15 DATA DATA LENGTH DATA BUFFER 62 TIME DATA STAMP LENGTH DATA BUFFER 63 TIME IDDATA STAMP LENGTH DATA TIME ID STAMP DATA LENGTH ID TIME STAMP Buffers 0-7 can be used to implement an 8 frame Rx FIFO ID

Flexcan: Architecture - Combining FlexCAN Modules FlexCAN A (Transmit and Receive) Message Buffer 0 Message Buffer 1... CNTXA CNRXA Transceiver CANH CANL Vehicle CAN Bus Message Buffer 63 FlexCAN B (Receive only) Message Buffer 0 Message Buffer 1... Message Buffer 63 CNTXB CNRXB Benefit: More buffers available for one CAN bus. CNTXB is not connected. (Otherwise FlexCAN B would acknowledge FlexCAN A transmissions)

MPC560xB Family Unique Features

emios Enhanced Modular IO System CTU conversion 48 49 CTU Cross Triggering Unit 16 ANP (Precise) TUE +/-2 counts PIT Period Interrupt INJECTED conversion ADC 16 ANS (Standard) TUE +/-3 counts 10-bit 64 channel e200 z0h NORMAL or SW INJ. conversion 4 32 MUX x4 ANX (Muxed) TUE +/-3 counts Power Architecture CORE 3 INTC Interrupt Controller WATCHDOG End of of CONV. CHAIN CTU INJ. MPC5604B Bolero 512K

Lighting - PWM Channels period n period n + 1 100Hz channels (n+1) Ch 0 Ch 1 Ch 2 Ch 3 Ch n-1 Ch n 0% shift, 40% duty cycle 5% shift, 40% duty cycle 10% shift, 100% duty cycle OFF 90% shift, 70% duty cycle 95% shift, 90% duty cycle 160Hz channels (n+1) Ch 0 Ch 1 Ch 2 Ch 3 Ch n-1 Ch n period n period n+1 period n+2 0% shift, 15% duty cycle 5% shift, 100% duty cycle 20% shift, 30% duty cycle OFF 80% shift, 15% duty cycle 90% shift, 90% duty cycle

emios - OPWMT Mode Period Match A1 Match C1 Match B1 B1 C1 A1 Output Pin Period: the period of the PWM is defined by a Modulus Counter channel. A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly. B1 Value: define the trailing edge (or duty cycle) of the PWM channel B2 Value: buffered value of trailing edge B1 update: transfer from B2 to B1 takes place at A1 match EDPOL: define the output polarity C1 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period.

Application Performance / Integration MPC5510 e200z1, edma e200z0 optional 48-66-80MHz 144/176LQFP 208MAPBGA 130nm Available In Design Planned Proposed MPC5517x 1.5M Flash, 80 KB RAM Up to 6 CAN, FlexRay, MLB MPC5516x 1M Flash, 64KB RAM Up to 6 CAN, FlexRay, MLB MPC5515S 768KB Flash, 48 KB RAM 5 CAN, 6 esci MPC5514E/G 512KB Flash 32K/64K RAM 32-bit Body Electronics MCU Roadmap MPC5668G 2MB Flash, 592KB RAM FlexRay, Ethernet, MediaLB MPC564xB e200z4 or e200z4+z0 80-120MHz MPC5606B (w/ edma) 1M Flash, 64KB Data Flash 6 CAN, 80KB RAM MPC5605B (w/ edma) 768KB Flash, 64KB Data Flash 6 CAN, 64KB RAM MPC5604B/C 512KB Flash, 64KB Data flash 3/6 CAN, 32/48KB RAM MPC5668E 2MB Flash, 128KB RAM, 6 CAN, 12LIN 90nm MPC5607B (w/ edma) 1.5M Flash, 64KB Data Flash 6 CAN, 96KB RAM MPC5668G/E High performance gateways Dual-core 200z6+z0, 116MHz @105C 208MAPBGA Bolero Gateway 2MB 2Mb Flash, 192K RAM, 64K Dataflash 6 CAN, 10 LIN, 6SPI. FR, Ethernet Samples: May 2009 Qual: Q3-2010 MPC560xB/C e200z0 32, 48, 64MHz 64/100/144/176LQFP 90nm 90nm Bolero Gateway 4MB 4Mb flash, 256K RAM, 64K Dataflash 6 CAN, 12 LIN, 6SPI. FR, Ethernet MPC5603B/C 384KB Flash, 64KB Data flash 3/6 CAN, 28-40KB RAM MPC5602B/C 256KB Flash, 64KB Data flash 3/6 CAN, 24-32KB RAM MPC5602D 256K Flash, 64KB Data Flash 1 CAN, 20KB RAM MPC5601D 128K Flash, 64KB Data Flash 1 CAN, 16KB RAM Samples: Feb 2010 Qual:Q1-2011 NOW 2010 2011 65

Bolero Family Line-up Data Flash Code Flash 4Mb 3Mb 2Mb 1.5Mb 1Mb 768K 512K 384K 256K 256K 128K Pin Out 64Kb 64Kb 64Kb 64Kb 64Kb 64 Kb Technology 5602D Up to 20K 5601D Up to 16K 5605 Up to 64K 5604 Up to 48K 5603 Up to 40K 5602B/C Up to 32K 5602D Up to 20K 5601D Up to 16K 5607 Up to 96K 5606 Up to 80K 5605 Up to 64K 5604 Up to 48K 5603 Up to 28K 5602B/C Up to 24K 5647 Up to 256K 5646 Up to 256K 5645 Up to 192K 5607 Up to 96K 5606 Up to 80K 5605 Up to 64K 5647 Up to 256K 5646 Up to 256K 5645 Up to 192K 5647 Up to 256K 5646 Up to 256K 5645 Up to 192K 90nm(TBC) 120 MHz 125oC T a 90nm 64 MHz 125oC T a 90nm 64 MHz 125oC T a 90nm 48 MHz 125oC T a 64 100 144 176 QFP 208 (*1) 256 (*1) BGA Device Ram Size Committed Proposed *1= package subject to confirmation. All proposed parts features subject to change with out notice.

Cross Family Compatibility Monaco (Powertrain) Pictus/Tokay (Airbag/Steering) Bolero (Body) Spectrum (Instrument Cluster) System Integration VReg Oscillator FMPLL RTC Interrupt Controller Crossbar Masters PowerPC e200z3 Core SIMD DMA MMU CROSSBAR SWITCH Debug JTAG Nexus Cal Bus Interface System Integration VReg Oscillator FMPLL RTC Interrupt Controller Crossbar Masters PowerPC e200z0 Core DMA FlexRay CROSSBAR SWITCH Debug JTAG Nexus System Integration VReg Oscillator FMPLL RTC Interrupt Controller Crossbar Masters DMA Ready PowerPC e200z0 Core CROSSBAR SWITCH Memory Protection Unit (MPU) Debug JTAG Nexus PIT 4ch 32b MCM System Integration VReg Oscillator FMPLL RTC Interrupt Controller Crossbar Masters PowerPC e200z0 Core Display DMA Interface Unit CROSSBAR SWITCH Memory Protection Unit (MPU) Debug JTAG Nexus I/O Bridge 48K 1Mb SRAM Flash Crossbar Slaves Communications I/O System Boot Assist Module (BAM) I/O Bridge 40K 512Kb SRAM Flash Crossbar Slaves Communications I/O System Boot Assist Module (BAM) I/O Bridge 512Kb Flash 32K SRAM Power Sw Crossbar Slaves Communications I/O System Boot Assist Module (BAM) I/O Bridge 64K Video External 1Mb SRAM RAM Bus Flash (tbd) (208MAPBGA) Crossbar Slaves Communications I/O System Boot Assist Module (BAM) emioslite 24ch 2.5K Code RAM 12K Data RAM etpu 32 ch. 2 FlexCAN 2 esci 2 DSPI 32 ch ATD 12bit Mc Timer Mc Timer Mc Timer Mc PWM ADC I/F 10 bit 650 nsec S&H S&H mux mux 1or2 FlexCAN 1 esci 3 DSPI emioslite 8ch IO 36ch shift PWM 2 I2C 3 FlexCAN 4 LINFlex 3 DSPI 32 ch ATD 12bit emioslite 24 ch. 2 CAN 2 LIN Flex 3 DSPI 2 I2C 16 ch ATD 10bit 6 gauge drivers sound 40x4 LCD 32-bit standard architecture adopted across all product families Maximum IP reuse Faster time-to-market Reduced risk Leverage software and tools investments

Tools

RAppID application, initialization, and documentation software Comprehensive Initialization of MPC560xB/C GUI based tool for easy and fast development of initialization code. Automatic report generation of Peripheral and Register settings. Efficient C and Assembly code generation for a multitude of compilers like CodeWarrior, Diab(WindRiver), and GreenHills. On-line documentation and built-in tool tips for ease of use Performs consistency checks to eliminate mistakes and inconsistencies. C code and Documentation templates customizable as a service. Supports multiple initialization strategy code generation. RAppID Time to Market Improvement for the MPC560xB/C Family 69

Pin Allocation Wizard - Screenshot 70

Fully enabled RAppID MPC5516 CodeWarrior 71

Development Tools An Existing Ecosystem CodeWarrior Green Hills Wind River GNU Lauterbach isystem P&E Micro RAppID Init dspace MathWorks Compilers Debuggers Simulators Eval Boards works w/ any (v2.2) debugger Initialization Tools Modeling and Code 72

March, 2010 New Power Architecture Solutions for Automotive Body Electronics Francisco Ramirez Field Applications Engineer

March, 2010 New Power Architecture: MPC560X MPC560XS Spectrum for Clusters

Common Microcontroller System Features Building Block Diagram DCU Quad SPI Interface Sound Generation Software Librarles Software / Tools Graphic Application Concept Design

DIS MCU Roadmap Application Performance / Integration Production Committed Proposed 0.25um Stepper Motor, LCD drive 25MHz 80,112 pin (ROM 32K-256K 512K 384K 256K S12HZ 256K 128K 64K MPC5121e E300 @ 400MHz OpenGL ES1.1 Accelerator Up to XGA display External Flash & DRAM i/f 400 BGA i.mx35g ARM1136JF-S CPU @ 400MHz Open VG 1.1 2D Graphics Accelerator Ip to SVGA display External Flash & DRAM i/f 400 BGA 0.25um 400 MHz MPC560xS Z0h CPU @ 64MHz DCU on 1MB & 768K Up to 160KB GRAM Stepper Motor, LCD drive 144 / 176 pin 800 MIPs Stepper Motor, S12XHZ LCD drive 40MHz XGATE 112,144 pin 1MB 768KB 512KB 256KB 90nm Stepper Motor, LCD drive 32MHz 100,64 pin S12HY Stepper Motor, LCD drive 32MHz 112, 144 pin 64K 48K 32K 256K 128K i.mx51 Coretex A8 600MHz OpenVG1.1 & OpenGL2.0 Accel Up to WXGA display External Flash & DRAM i/f 530 BGA MPC564xS Z4d CPU @ 120MHz DCU (TFT Display Driver) Graphics Accelerator 1MB of GRAM Stepper Motor Drive 176 / 208 QFP, 324 BGA 0.18um 1200 MIPS 2MB 1MB 90nm High end Multimedia MCU s Single chip Instrument cluster 76

MPC5606S: Spectrum 1M (64MHz) System Integration VReg Oscillator FMPLLx2 RTC/32kHz Interrupt Controller Power Management Boot Assist Module (BAM) Sound Generation emios 24 ch Crossbar Masters I/O Bridge 2 FlexCAN 16ch DMA 1Mb Flash Power e200z0h Core CROSSBAR SWITCH Memory Protection Unit (MPU) 4x16k EEE 48K SRAM Display Control Unit Crossbar Slaves Communications I/O System 2 LINFlex 3 SPI 4 I2C 160K Graphics SRAM 16 ch ATD 10bit Debug JTAG Nexus RGB / Control QuadSPI Serial Flash Controller Stall Detect 6 Gauge Drivers PDI 40x4 LCD General Characteritics: PPC e200z0h Core 1M FLASH with ECC 4x16k EEPROM Emulation block with ECC 48k SRAM with ECC 16 channel DMA Memory Protection Unit (12 regions) Voltage Regulator with external ballast transistor Real Time Counter + 32kHz crystal oscillator Watchdog, Periodic Interrupt Timer, System Timer 4-16MHz crystal oscillator Frequency Modulated PLL (x2) Nexus 2+ / JTAG Graphics Features: 160k Grpahics SRAM (No ECC) Display Controller Unit 18/24bit RGB Parallel Data Interface QuadSPI Serial Flash controller General Characteristics: Up to 64MHz operation Low power modes -40 to +105C, 3.0V to 5.5V 144 LQFP, 176 LQFP package options Peripherals and Communications: 6 Stepper Motor Drivers with Stall Detection Sound generation using emios 40x4 LCD Segment Driver 2xCAN, 2xDSPI, 4xI2C, 2xLIN, I2S 24 channel emios (PWM+Timer) 16 channel, 10bit ADC 77

Investment reuse/portability WXGA Application Performance / Integration WVGA HVGA TFT MPC5121e E300 @ 400MHz OpenGL ES1.1 Accelerator Up to XGA display External Flash & DRAM i/f 400 BGA i.mx51 Coretex A8 600MHz OpenVG1.1 i.mx35g & OpenGL2.0 Accel Up to WXGA display ARM1136JF-S External CPU Flash @ 400MHz & DRAM i/f Open VG 1.1 2D Graphics Accelerator 530 BGA Ip to SVGA display External Flash & DRAM i/f 400 BGA MPC5645S 800 MIPs 1200 MIPS 400 MHz Z4d CPU @ 120MHz DCU (TFT Display Driver) MPC5645S Graphics Accelerator Z4d CPU Stepper @ 120MHz Motor Drive DCU (TFT Display Driver) 176 / 208 pin MPC5606S Graphics Accelerator Stepper Motor Drive Z0h CPU @ 64MHz 176 / 208 pin DCU (TFT Display Driver) Up to 160KB GRAM Stepper Motor, LCD drive 144 / 176 pin 3MB 2MB 3MB 1.5MB 2MB 1MB1.5MB 768KB + + MPC5604S MPC5604S DRAM Connectivity, application, tools DCU OpenVG OpenGL No TFT MPC5604S Z0h CPU @ 64MHz Stepper Motor, LCD drive 144 / 176 pin 512KB 256KB 78

DCU The display driver used in Spectrum family MCU s s for instrument cluster is a combined direct un-buffered blit engine & display driver. Main advantages are Cost efficient Low memory requirement Optimized for GUI and advanced OSD Safety feature to enable safety related display content 79

Bliting concepts OBJECT memory Blit engine FRAME buffer Visible buffer Shadow buffer Display driver Classic solution Flexible and typically slow Needs typically 3x full frame buffer RAM for 480x272 @24/18bpp RGB888 that is 1147kB. Typically needs external fast RAM. CPU Scratch pad Needs min. 2 x resolution RAM for video input. Display frame rate asynchronous output composition DCU direct un-buffered blit engine OBJECT memory edma CPU FRAME buffer Fragmented frame buffer Bliter Display driver Fixed function and typically much faster Needs less frame buffer RAM. For 480x272 @24/18bpp RGB888 that is typically less than 160kB Suitable for single chip solutions with no external RAM. Blit functions optimized for GUI design. No RAM required for video input Display frame rate synchronous output composition 80

DCU features, (updated with rev2 enhancements) 16 Layers 4 planes Frame buffer limited by memory size (all memories, RAM, ROM INT,, EXT) Target size WVGA (Limited by memory bandwidth and pixel clock speed) s Support 16, 24, 32 bit color depth. Support 1, 2, 4, 8bpp indirect color mode Support TFT type LCD with 16, 18, 24bit wide digital RGB interface Alpha blend (per pixel and per layer in 4 planes) Chroma key (range per RGB component in 4 planes) Combined alpha blend and chroma key modes Font mode blending (transparency mode/alpha map) Highlight area mode. (luminance offset) Tile mode Digital video input Safety mode support Hardware cursor 81

DCU layers & planes Layer priority is fixed. Layers arbitrate for 4 planes on per pixel basis. The active layer that has the highest priority loads in the foreground plane 1, the next loads in foreground plane 2 etc. If no layer qualifies for the BG plane the BG color is loaded in the BG plane 82

MPC5606S, Layers and planes usage Green frame show Planes and HW cursor Red frames show Layers 83

DCU functions Font mode (Transparency) Original image Coded in 4bpp transparency Run time color selection in hardware to any back/fore color. *) Images are significantly enlarged for clarity. 84

Transparency Mode Blending examples 85

Transparency Mode Blending examples 86

DCU layers 16 + 1 background color Layers are memory areas that can reside in any memory. Internal or external FLASH or RAM. Size and position is configurable runtime in 1 pixel increments. The 2 highest priority layers support a special safety mode. Data in layers is coded in 1,2,4,8 bits per pixel or Raw color 16, 24, 32 bpp or.. (RGB565, RGB888, ARGB8888, ARGB1555, ARGB4444) or 4 or 8bpp transparency with foreground and background color or 4 or 8bpp luminance offset. 87

DCU CLUT CLUT is a color look up table. Size is 2k 24bpp colors, CLUT is assigned on a per layer basis. Pallet size is dynamic and is shared by all layers. Color depth is fixed to 24bpp RGB888 Layer control descriptor uses a color offset value to mark start position in the CLUT. As an example the CLUT can hold 8 x 8bpp pallets with 24bit colors. Or any combination required for the other indexed modes i.e. 1, 2, 4bpp. Run time manipulation and assignment of CLUT to a layer is possible. CLUT is part of the DCU memory and does not load the system memory bus. 88

MPC5606S, DCU timing example A B C 1 frame = 16,7ms @ 60Hz D A Layer CD s are latched in shadow buffer and frame composition starts. B CPU writes CD registers to prepare the next frame. Typically less than 0,1ms. Needs to be done within the frame period. C edma performs a ROM to RAM scan synchronized BLIT of the next car and navigation object. (Direct un-buffered frame synchronized blit) D edma performs vertical blanking period blit of CLUT, objects, HWC etc.. * C & D ie. the DMA activation is performed in ISR. * B The main frame loop is assumed to be a pre-emptive low priority task. Very relaxed latency requirement. Typically need <5% CPU as an average measured over 16ms. 89

PDI video input, use case example Camera ITU-R BT.656 (progressive RGB) MCU PDI 9 pin Digital RGB CCIR 656 Digital RGB Proprietary LVDS FPGA De-interlacing Scaling muxing Digital RGB MCU PDI 10 pin Digital RGB Camera or Navigation or DVD decoder or TV tuner or 16/18 bit RGB MCU PDI 20/22 pin Digital RGB PDI has 5 modes. 8bitcolor, 8bit mono, 16bit, 18bit digital RGB and ITU-R BT.656 (progressive RGB) Input video must be equal clock data must match used display. Example: if display is 480x272 9MHz input video must be 480x272 9MHZ 90

QuadSPI / Serial Flash 91

Serial Flash Bandwidth Expectations Serial Interface Bandwidth: Peak bandwidth = [Serial clock * 4(quad)] / [8bits/byte] For 48MHz flash = 24MByte/sec For 80MHz flash = 40MByte/sec Small overhead incurred to launch Serial Flash read commands reduces achievable b/w Impact depends on data size transferred As a frame buffer for Spectrum Display Control Unit (DCU): QVGA @ 5MHz pixel clock 16bpp layer = 10MByte/sec 24bpp layer = 15MByte/sec 32bpp layer = 20MByte/sec 480x272 @ 9MHz pixel clock 16bpp layer = 18MByte/sec 24bpp layer = 27MByte/sec 32bpp layer = 36MByte/sec 92

AMBA AHB Slave: Memory-mapped Serial Flash looks like On-Platform memory Accessible by all crossbar masters Direct access by DCU for prerendered layers. QuadSPI Integration Spectrum1M System Integration VReg Oscillator 2xFMPLL RTC Interrupt Controller Crossbar Masters 16ch DMA Power e200z0h Core Display Control Unit Debug JTAG Nexus RGB / Control PDI IPS: Connected as an IPS peripheral Useable as regular SPI Clocking Serial Interface runs up to full 48MHz platform speed Auxiliary PLL available as optional clock source. Power Management Boot Assist Module (BAM) Sound Generation emios 24 ch I/O Bridge 2 FlexCAN 1Mb Flash CROSSBAR SWITCH Memory Protection Unit (MPU) 4x16k EEE 48K SRAM Crossbar Slaves Communications I/O System 2 LINFlex 2 DSPI 4 I2C 160K Graphics SRAM 16 ch ATD 10bit QuadSPI Serial Flash Controller Stall Detect 6 Gauge Drivers 40x4 LCD 93

QuadSPI Memory Map AHB Mapping 4 x 128MByte Slots reserved for external serial flash in memory map (future expansion) AHB RX Data Buffer (QSPI_ARDB) for Serial-Flash-0 is mapped at 0x87FF_FFFC 128k QuadSPI Slot-0 MCU Memory Map 0x8000_0000 0x8000_0004 0x8000_0008 0x8000_000C 0x803F_FFFC 0x87FF_FFFC QSPI_ARDB Serial Flash Memory Map 0x00_0000 0x00_0004 0x00_0008 0x00_000C 0x3F_FFFC 32Mbit Serial Flash (4MByte) 94

Sound Generation 95

MPC560xS : Simple Audio Implementation Features: Used for simple beeps / alarms Uses dual-pwm outputs 1 x PWM channel to control Amplitude 1 x PWM channel to control Frequency Logical AND of any 2 emios PWM channels to generate audio output Simple external R-C Low pass filter on mixed PWM output Frequency Amplitude LPF Freq. Amplitude Filtered 96

MPC560xS: Advanced Audio Implementation Features: Playback of Sample-Based waveforms Polyphonic sound synthesis DMA reads sound files from internal (or external) Flash Up to 8KHz analog bandwidth Variation of duty cycle reconstructs the analog signal Speed of duty cycle variation proportional to frequency Width of duty cycle variation proportional to amplitude Analog signal AC centered around 50% duty cycle Low pass filter / amplifier on PWM I/O pin Software tools to support sound generation 50% Duty LPF Low Duty High Duty 97

Software Libraries 98

Introduction MPC56xxS Software Graphics Libraries The MPC56xxS Software Graphics Libraries is a set of drivers that allow the designers to develop fast and clean software animations. The libraries explodes most of the HW features of the Display Control Unit along with other peripherals such the DMA. Current Main Features Animations (Position, Transparency, Color, Scrolling, and Downscaling) HW accelerated Transformations (Rotations, Mirroring, Blitting) DMA accelerated RLE Decoding Hybrid CPU/DMA Color Look up table dynamic update. DMA accelerated Dynamic Memory Allocation for graphics. DMA accelerated UNICODE Text Rendering. CPU or DMA Accelerated PC Toolset to manipulate graphic 99

Software Architecture Software Architecture Key Features Drivers were made to work together in an abstract way Architecture allow correct interaction between software layers Users will focus in movie clips and functionality leaving alone lower layers SERVICES DMA Handler, Animation Handler, Interrupts, Others APPLICATION LAYER Movie Clips, Stimuli, Images, Font files HARDWARE INDEPENDENT LAYER (HIL) Font library, Graphics Library, Animation Library and Display driver. HARDWARE ABSTRACTION LAYER (HAL) Graphic Memory Allocation, DCU and DMA 100

Software / Tools 101

Freescale Image Encoder *.h Image File (gif, bmp, jpeg png, others) Freescale Image Encoder *.c Spectrum Graphics Libaries 102

Freescale Font Encoder *.fnt (xml file) Angel Code Font Bitmap Generator *_00.png [*_01.png] Freescale Font Encoder Spectrum Font Library 103