Buck Coverter Losses Uder the Microscope sychroous stepdow coverters, the parasitic iductaces associated with pcboard traces ad device packagig affect power losses, while limitig MOSFET switchig speeds. By Ala Elbahawy, Director, Computig ad Telecommuicatios Segmets, Advaced Power Systems Ceter, Fairchild Semicoductor, Sa Jose, Calif. V V R R Fig.. Simplified schematic of a buck coverter. Q L Q L L uh C u V Vdc R.6 T he sychroous buck coverter i Fig. is the most popular topology i the PC market. The race betwee the top MOSFET compaies is heatig up with the rush to desig ew devices that are faster ad better suited to meet the demads of the microprocessor makers. These customers require higher switchig frequecies for their core dcdc coverters to achieve wider cotrolloop badwidth ad lower coverteroutput impedace at lower cost. t is also well kow that faster switchig frequecies itroduce higher losses uless MOSFET parameters, such as gatedrai charge (Q gd ad Q sw ) ad draisource oresistace R DS(ON), are optimized for such applicatios. Nevertheless, gate charge ad oresistace are ot the oly parameters that create dcdc coverter losses. The iductaces associated with device packagig ad pcboard traces also cotribute to coverter losses i the sychroous buck coverter. To uderstad these loss mechaisms requires simulatio as well as testig of actual prototypes. Both of these parasitic parameters play a pivotal role i determiig the power loss i the coverter ad ultimately how fast we ca switch MOSFETs. Armed with a uderstadig of how stray iductaces cotribute to coverter losses, we ca devise ways to overcome their effects. The Highside MOSFET Fig. shows the switchig waveforms of a actual voltage regulator module (VRM). Ch is the gategroud voltage of the highside (HS) MOSFET Q i Fig. ; Ch is the sourcegroud voltage of the HS MOSFET Q i the same figure. The trace M i Fig. is the calculated ChCh represetig the gatesource voltage of the HS MOSFET, ad Ch ad Ch4 are the drai currets of Q ad Q. this particular test, we had to use a curret loop i both the sources of Q ad Q of Fig. (partially represeted by L ad L) to eable curret measuremets. This clearly alters the circuit performace by itroducig large iductaces i the circuit. Although this is ot the real circuit, it helps us uderstad the loss mechaism durig tur off of these MOSFETs. Later o, we will itroduce a oivasive way to measure the curret without disturbig the circuit too much. Fig., the trace M clearly shows a plateau of about.5 V after the gate voltage has tured off, as ca be see i Ch. Durig this plateau, which lasts for about s, the drai currets of both the HS ad the lowside (LS) MOSFETs chage states. The HS MOSFET turs off ad the drai curret (Ch4) returs to zero, while the LS MOSFET turs o ad the drai curret (Ch) reaches the iductor curret. This is where the circuit performs i a way cotrary to the curret uderstadig of how Power Electroics Techology February 5 4
Fig.. Switchig waveforms from VRM. Fig.. Switchig waveforms from VRM. the sychroous buck coverter performs. O closer examiatio, this pheomeo ca be clearly explaied. Whe the HS MOSFET gategroud voltage falls from V CC V GDrive to groud, the drai curret will start fallig from its curret level toward the off state of A. (V CC is the iput voltage ad V GDrive is the gatedrive voltage). Notice that Ch (sourcetogroud voltage) falls to groud withi 5 s to s, givig the false impressio that the switchig trasitio is completed withi this time. reality, the drai currets take about s to complete the trasitios. Also remember that the s is large because of the source loops. actual circuits where there are o loops, the curret will take shorter time to reach its fial level. We will show that i simulatio results where we ca probe without disturbig the circuit. Notice that the sourcegroud voltage goes egative. The rate of chage of the drai curret drai (where drai is the drai curret ad t is time) will geerate a backward voltage = pullig the source voltage i a egative directio with respect to the gate. This actio, i tur, makes the gate voltage positive with respect to the source, hece allowig curret to cotiue to flow though the gate voltage is firmly held to groud. Sice the curret trasitio is by large a liear trasitio the Cos t = ta. other words, this plateau has a fixed level with time util the curret completes its trasitio. This egative source voltage plateau will ow allow the drai curret to cotiue to flow util the curret reaches zero. We are used to a MOSFET beig fully ON whe the curret is flowig, but closer examiatio of Fig. reveals that the drai curret is flowig i the HS MOSFET while the voltage across it is V CC. Why is that? t is crucial that we examie the MOSFET performace at this plateau to further uderstad what is happeig. The MOSFET is i a balacig situatio where the voltage causes the source to go egative eough for the MOSFET to barely supply the curret for the trasitio, which is clear from the fact that V @5. Power Electroics Techology February 5 6
Fig. 4. Gatevoltage plateau time is proportioal to load curret. a mere V above the gatesource threshold voltage. The chael is ot fully ehaced; therefore, the MOSFET operates as a curret source where the curret level is maitaied by the egative feedback of the voltage plateau. Havig the MOSFET operatig as a regulated curret source, albeit durig the curret trasitio oly, meas the voltage across the drai source will sustai the full V CC voltage across it causig higher losses. To further complicate matters, the fall time of the drai curret is depedat o its magitude (i.e., the larger the curret, the larger the fall time, which leads to the coclusio that the losses are ot liear with curret as it has bee assumed so far). Fig. 4 shows this depedecy clearly. Fig. 4 (a), the trace M is the gate MULTLAYER POLYMER (MLP) CAPACTORS Ultra Low ESR ad ESL High Ripple Curret Hadlig Stable Uder AC & DC Voltage Telecom Grade No Agig Low Profile For Surface Mout Robust Mechaical ad Electrical Desig 5 to 5 Volts APPLCATONS 48 Volt Telecom/Datacom 4 Volt Automotive SMPS OffLie PFC Frot Eds RF/EM Suppressio Max rms Max RMS Curret vs. Capacitace MLP Capacitors @ 5KHz. 8. 6. 4... 8. 6. 4... 5 5 Cap Value (microfarads) Max RMS Curret vs. Capacitace Value P.O. Box 459 5 McCoville Road Lychburg, VA 45 TEL 449694 FAX 44947 itwpaktro@paktro.com Available through these distributors: Atlatic Compoets (8466) Future (88887) Gopher (859959) Corell Dubilier/Mallory (58996856) www.paktro.com CRCLE o Reader Service Card or freeproductifo.et/pet 7 Power Electroics Techology February 5
Fig. 5. Simulatio results that cofirms the test results. V= V= TD= s TR= 5 s TF= 5 s PW= 45 s PER= us V V V= V= TD= 48 s TR= 5 s TF= 5 s PW=.46 us PER= us Fig. 6. Schematic for Fig. 7. 5 Vdc V source voltage of the HS MOSFET at oload ad i Fig. 4 (b), the trace M shows gatesource voltage of the HS MOSFET at.5a load curret. This R 5 V5 5 Vdc R V4 5 5 L5 H V U FDS6694 V L 45 H L H V U FDS6688 L4 45 H V V Vdc L uh C uf R.6 leads to the equality TurOffLosses = drai V CC fs K drai = K drai V CC fs. () Whe =, the plateau will reach zero voltage ad the MOSFET turs off completely. Simulatio results i Fig. 5 usig the schematic i Fig. 6 cofirm the lab test fidigs. Fig. 5, the simulatio scas the value of the source iductace betwee. H ad 5. H for the same load curret. Clearly, the curret fall time is depedat o the parasitic source iductace further aggravatig the total losses Parasitic ductace Effect o MOSFET Turo Now that we have explaied a ew switchig loss mechaism i the HS MOSFET durig tur off, let s ivestigate what is the loss durig the turo trasitio. The situatio here is completely differet because L i Fig. does ot carry ay curret at the start of the turo cycle. This meas that the voltage ow is positive ad will ted to make the source move i the positive directio opposig the gate drive s attempt to force the gatesource voltage to be equal to the gatedrive voltage. This is ot a difficult situatio to correct, because we ca raise the gatedrive voltage to the level sufficiet to execute clea ad fast switchig withi the MOSFET V GSS limits. this case, the curret will follow the gate drive. The losses durig tur o are much smaller tha those durig tur off. This is because durig tur o, the total iductace i the loop will carry a substatial amout of the total iput voltage V CC. This loop comprises V CC trace iductace, HS MOSFET with its lead iductace, the pcboard trace iductace betwee the HS ad the LS MOSFET, the LS MOSFET with its lead iductace ad the pcboard iductace betwee the Power Electroics Techology February 5 8
Fig. 7. LS MOSFET turoff ad turo waveforms. source of the LS MOSFET ad the retur of V CC. Fig. illustrates that poit. Ch is the sourcegroud voltage, Ch is V CC, Ch ad Ch4 are the drai currets of MOSFETs Q ad Q, respectively. The trace M represetig the draitosource voltage drop across the HS MOSFET will hover aroud a itermediate value betwee V ad V cc while the curret is switchig o from zero to the output iductor curret. This itermediate voltage across the iductaces may be calculated from the equatio L where L drai is the sum of all the iductaces i that loop. Note that idividual voltages withi the above summig equatio may be positive or egative, depedig o the positio i the circuit. This meas the voltage drop across the MOSFET durig tur o may be calculated from the equatio: V CC L drai ad the losses may be calculated from the equatio Ł Vcc L drai drai ł tr fs () where t r is the curret rise time. This equatio represets a much lower loss because of several factors. Oe is that the rise time t r is a much smaller value sice the opposig effect of Cos t = ta may be overcome by raisig the gate voltage to accommodate this tur o voltage plateau. Aother differece betwee turo ad turoff performace is that i the turo trasitio, the HS MOSFET is actively beig drive by the gate driver; ad hece, we have fast trasitio cotrolled to a large degree by the gate driver ad to a lesser degree by the source parasitic iductace. Coversely, i the turoff trasitio the HS MOSFET is passively drive o by the backemf effect ad regulated to operate as a curret source. additio, the voltage drop from drai to source of the HS MOSFET is a small fractio of V cc as ca be calculated from Equatio. The Lowside MOSFET The loss mechaism for the LS MOSFET agrees so far with the curret uderstadig of their behavior. As HS MOSFET turs off, the iductor curret starts commutatig ito the body diode of the LS MOSFET ad the draisource voltage of the LS MOSFET switches from V CC to oe diode drop, as see o Fig. 7(b). As the gate voltage of the LS MOSFET turs o after the dead time, the drai curret will cotiue to rise util it reaches the iductor curret ad the HS MOSFET turs off. The slow rise time of the curret ca be directly attributed to the HS ad LS source iductors because the iductors will resist ay sudde chage i curret. Because the curret flows from the source to the drai of the LS MOSFET, the voltage developed across the source parasitic iductace (lead ad pcboard trace iductace) actually assists the turo cycle. t appears that the parasitic iductace of the HS MOSFET determies the curret trasitio here, as described before. Whe the LS MOSFET is tured off, the curret will flow i its body diode util the HS MOSFET starts turig o, the voltage developed across the parasitic iductace will force the gatesource voltage ito a egative value. Sice the gate is held at the groud, this will help keep the LS MOSFET off durig this trasitio. The graphs show i Fig. 7 preset 9 Power Electroics Techology February 5
L & L4 are the package lead iductace ad PCB trace iductace M M o surprises, ad hece, the losses i the LS MOSFET appear to cotiue to be mostly coductio or ohmic losses sice the draisource voltage L Vcc CL L & L are large loop for curret probe Fig. 8. Wirig techique to miimize lead iductace while eablig curret measuremet. is always held low while the curret is switchig o ad off. The measured currets i the HS ad LS MOSFETs do ot exactly match i these graphs because of the iaccuracies of the curret dividers used. Noivasive Curret Measuremet Curret measuremet i highfrequecy dcdc coverters is difficult, because isertig a loop to measure curret or a sese resistor will alter the origial coditios. This led us to propose the use of the circuit i Fig. 8. this approach, we use two parallel loops of wire (L& L ad L & L4). L ad L are loops that are barely log eough to accommodate the scope curret probe, while L ad L4 are a very short wire (e.g., the MOSFET package lead plus the pcboard trace iductace). this way, we have created a curret divider where the majority of the curret flows i the short wire (L ad L4) without disturbig the circuit much while a much smaller portio 8 Series SMPLE EFFCENT ECONOMCAL CONDUCTON CONVECTON Reflow Solderig & Curig BGA/CSP Packagig High desity packagig/substrates Lamiated power compoets Wafer Bump Reflow, Laser Diode Reflow Microwave hybrids, Fluxless Au/T Reflow 5/C SKAMA NTERNATONAL, c. 8 E. Gutierrez Street Sata Barbara, CA 94 U.S.A. Tel: 8596 Fax: 85966 www.sikama.com CRCLE o Reader Service Card or freeproductifo.et/pet Power Electroics Techology February 5
telliget MotioCotrol BUCK CONVERTER LOSSES Curret Probe Size: 6mm Elarged View: 4x Prited Circuit Board Log Curret Loop Short Curret Loop Majority of Curret of the source curret will flow i the large loop (L ad L). The ratio betwee the two currets i the two parallel paths is L L @, L L which is roughly the ratio betwee the two areas occupied by the two loops. Fig. 9 shows the method used to measure a sample of the curret with the least disturbace of the origial circuit. The curret uderstadig of HS MOSFET switchig must iclude the effects of the circuit parasitic iductaces ad their effects o the switchig performace of the sychroous buck dcdc coverter ad other topologies. These parasitic iductaces are amely the package lead iductace ad the pcboard trace iductaces. The HS MOSFET source parasitic iductace has several effects o switchig performace. First, the HS MOSFET will cotiue to coduct curret eve after the gate voltage reaches V (groud level). This is due to the egative back EMF of the parathemc7 Brushless MotorCotrollerC MOSFET Package Ultra highperformace Low cost Siusoidal or 6step commutatio teral profile geeratio Highspeed idex capture 6 sigal PWM with shoot through protectio Digital curret loop Velocity loop The Best Egieered Products i Motio PERFORMANCEMOTONDEVCES www.pmdcorp.com MOTORDRVES AMPLFERS CONTROLLERS CRCLE 4 o Reader Service Card or freeproductifo.et/pet 4 Performace Motio Devices, c. Fig. 9. Measuremet techique for miimum circuit disturbace. sitic iductace pullig the source to a egative level with respect to the gate, allowig the curret to flow freely. A secod effect is that the drai curret fall time is proportioal to the curret level. This leads to losses proportioal to drai, ad thus much larger switchig losses eve with the best MOSFETs. Thirdly, the drai curret fall time is proportioal to the parasitic iductace value. This puts a limit o the maximum power efficiecy available from the dcdc coverter regardless of how fast the HS MOSFET is. order to reach high switchig speeds, certai compoet characteristics must be obtaied. MOSFETs must have low Q gd ad Q sw. Packages must facilitate the coectio of the gate driver directly betwee the gate ad the source usig o curretcarryig leads or pcboard traces. A ball grid array (BGA) is a excellet package for this purpose. Furthermore, gate drivers must provide a true differetial gatesource drive sigal, low source ad sik resistace, ad very fast rise ad fall times. PETech Power Electroics Techology February 5