PD 9399A AUTOMOTIVE MOSFET Typical Applications Electric Power Steering (EPS) Antilock Braking System (ABS) Wiper Control Climate Control Power Door Benefits Advanced Process Technology Ultra Low OnResistance Dynamic dv/dt Rating 75 C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Description Specifically designed for Automotive applications, this Stripe Planar design of HEXFET Power MOSFETs utilizes the lastest processing techniques to achieve extremely low onresistance per silicon area. Additional features of this HEXFET power MOSFET are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. Absolute Maximum Ratings HEXFET Power MOSFET Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 69 I D @ T C = C Continuous Drain Current, V GS @ 0V 8 A I DM Pulsed Drain Current 680 P D @T C = 25 C Power Dissipation 330 W Linear Derating Factor 2.2 W/ C V GS GatetoSource Voltage ± 20 V E AS Single Pulse Avalanche Energy 560 mj I AR Avalanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting Torque, 632 or M3 screw 0 lbf in (.N m) Thermal Resistance G D S TO220AB IRF405 V DSS = 55V R DS(on) = 5.3mΩ I D = 69A Parameter Typ. Max. Units R θjc JunctiontoCase 0.45 C/W R θcs CasetoSink, Flat, Greased Surface 0.50 R θja JunctiontoAmbient 62 www.irf.com 3/25/0
IRF405 Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 55 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.057 V/ C Reference to 25 C, I D = ma R DS(on) Static DraintoSource OnResistance 4.6 5.3 mω V GS = 0V, I D = 0A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = 0V, I D = 250µA g fs Forward Transconductance 69 S V DS = 25V, I D = 0A I DSS DraintoSource Leakage Current 20 V µa DS = 55V, V GS = 0V 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 200 V GS = 20V na GatetoSource Reverse Leakage 200 V GS = 20V Q g Total Gate Charge 70 260 I D = 0A Q gs GatetoSource Charge 44 66 nc V DS = 44V Q gd GatetoDrain ("Miller") Charge 62 93 V GS = 0V t d(on) TurnOn Delay Time 3 V DD = 38V t r Rise Time 90 I D = 0A ns t d(off) TurnOff Delay Time 30 R G =.Ω t f Fall Time 0 V GS = 0V Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 5480 V GS = 0V C oss Output Capacitance 20 pf V DS = 25V C rss Reverse Transfer Capacitance 280 ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 520 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 900 V GS = 0V, V DS = 44V, ƒ =.0MHz C oss eff. Effective Output Capacitance 500 V GS = 0V, V DS = 0V to 44V SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 69 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 680 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 0A, V GS = 0V t rr Reverse Recovery Time 88 30 ns T J = 25 C, I F = 0A Q rr Reverse RecoveryCharge 250 380 nc di/dt = A/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Starting T J = 25 C, L = 0.mH R G = 25Ω, I AS = 0A. (See Figure 2). ƒ I SD 0A, di/dt 20A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. 2 www.irf.com
IRF405 I D, DraintoSource Current (A) 0 VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, DraintoSource Current (A) VGS TOP 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH T J = 75 C 0 0. 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current (A) 0 T J = 25 C T J = 75 C V DS= 25V 20µs PULSE WIDTH 4 6 8 0 2 V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = 69A 2.5 2.0.5.0 0.5 V GS = 0V 0.0 60 40 20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature www.irf.com 3
C, Capacitance(pF) IRF405 00 0 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) 20 6 2 8 4 I = D 0A V DS = 44V V DS = 27V FOR TEST CIRCUIT SEE FIGURE 3 0 0 60 20 80 240 300 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V 0.0 0.5.0.5 2.0 2.5 3.0 V SD,SourcetoDrain Voltage (V) 0 I D, Drain Current (A) 0 OPERATION IN THIS AREA LIMITED BY R DS(on) 0us us ms 0ms TC = 25 C TJ = 75 C Single Pulse 0 V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
IRF405 200 LIMITED BY PACKAGE V DS R D I D, Drain Current (A) 60 20 80 40 0 25 50 75 25 50 75 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% R G V GS 0V Pulse Width µs Duty Factor 0. % D.U.T. Fig 0a. Switching Time Test Circuit 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms V DD Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.00 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase www.irf.com 5
V GS(th), Variace ( V ) IRF405 R G V DS 20V tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T I AS 0.0Ω V (BR)DSS 5V DRIVER V DD A E AS, Single Pulse Avalanche Energy (mj) 200 800 600 400 200 I D TOP 4A 7A BOTTOM 0A 0 25 50 75 25 50 75 Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 4.0 V G 3.5 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 3.0 2.5 I D = 250µA 2V.2µF 50KΩ.3µF 2.0 V GS D.U.T. V DS.5 75 50 25 0 25 50 75 25 50 75 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage Vs. Temperature 6 www.irf.com
E AR, Avalanche Energy (mj) IRF405 Duty Cycle = Single Pulse 0.0 0.05 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses Avalanche Current (A) 0 0.0.0E08.0E07.0E06.0E05.0E04.0E03.0E02.0E0 tav (sec) Fig 5. Typical Avalanche Current Vs.Pulsewidth 600 500 400 300 200 0 TOP Single Pulse BOTTOM 0% Duty Cycle I D = 0A 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = T/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2 T/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRF405 Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Polarity of D.U.T for PChannel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =0V ] *** D.U.T. I SD Waveform Reverse Recovery Current ReApplied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 7. For Nchannel HEXFET power MOSFETs 8 www.irf.com
IRF405 Package Outline TO220AB Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) A 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4 6.47 (.255) 6.0 (.240) 2 3.5 (.045) MIN LEAD ASSIGNMENTS GATE 2 DRAIN 3 SOU RC E 4 DRAIN 4.09 (.555) 3.47 (.530) 4.06 (.60) 3.55 (.40) 3X.40 (.055).5 (.045) 2.54 (.) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.0 4 ) M B A M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO220AB. 2 C O N TR O L LIN G D IM E N S IO N : INC H 4 H E A T S IN K & LE A D M E A S U R E M E N T S D O N OT INCLUDE BURRS. Part Marking Information TO220AB EXAMPLE : THIS IS AN IRF00 W ITH ASSEMBLY LOT CODE 9BM INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CO DE IRF00 9246 9B M PART NUMBER DATE CODE (YYWW) YY = YEAR WW = WEEK A Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q0] market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) 252705 TAC Fax: (30) 2527903 Visit us at www.irf.com for sales contact information. 3/0 www.irf.com 9