An integrated CMOS optical receiver with clock and data recovery circuit

Uiversity of Pretoria etd Che, Y-J (5) A itegrated CMOS optical receiver with clock ad data recovery circuit by Yi-Ju Che Submitted i partial fulfillmet of the requiremet for the degree Master of Egieerig (Micro-electroics) i the Faculty of Egieerig, Built Eviromet ad Iformatio Techology Uiversity of Pretoria, Pretoria August 5

Uiversity of Pretoria etd Che, Y-J (5) SUMMARY A itegrated CMOS optical receiver with clock ad data recovery Circuit by Yi-Ju Che Supervisor: Prof. Mouko du Plessis Electrical, Electroic ad Computer Egieerig M.Eg (Micro-electroics) Keywords: Optical receiver, photodetector, frot-ed, iductive peakig, clock ad data recovery circuit, oscillator, phase-locked loop, frequecy-locked loop. Traditioal implemetatios of optical receivers are desiged to operate with exteral photodetectors or require itegratio i a hybrid techology. By itegratig a CMOS photodetector moolithically with a optical receiver, it ca lead to the advatage of speed performace ad cost. This dissertatio describes the implemetatio of a photodetector i CMOS techology ad the desig of a optical receiver frot-ed ad a clock ad data recovery system. The CMOS detector coverts the light iput ito a electrical sigal, which is the amplified by the receiver frot-ed. The recovery system subsequetly processes the amplified sigal to extract the clock sigal ad retime the data. A iductive peakig methodology has bee used extesively i the frot-ed. It allows the accomplishmet of a ecessary gai to compesate for a uderperformed resposivity from the photodetector. The recovery circuits based o a oliear circuit techique were desiged to detect the timig iformatio cotaied i the data iput. The clock ad data recovery system cosists of two uits viz. a frequecy-locked loop ad a phase-locked loop. The frequecy-locked loop adjusts the oscillator s frequecy to the viciity of data rate before phase lockig takes place. The phase-locked loop detects the relative locatios betwee the data trasitio ad the clock edge. It the sychroises the iput data to the clock sigal geerated by the oscillator. i

Uiversity of Pretoria etd Che, Y-J (5) A system level simulatio was performed ad it was foud to fuctio correctly ad to comply with the gigabit fibre chael specificatio. ii

OPSOMMING Uiversity of Pretoria etd Che, Y-J (5) ' Geïtegreerde CMOS optiese otvager met klok e data herwiigs stroombaa deur Yi-Ju Che Studieleier: Prof. Mouko du Plessis Elektriese, Elektroiese e Rekeaar Igeieurswese M.Ig (Mikroëlektroika) Sleutelwoorde: Optiese otvager, fotodetector, voorkat, iduktiewe piek metode, klok e data herwiig stroombaa, ossillator, fase sluit lus, frekwesie sluit lus. Tradisioele implemetasies va optiese otvagers is of otwerp om met ekstere fotodetektors te werk of hibriede itegrasie tegologie motet gebruik word. Deur ' CMOS foto detektor moolities te itegreer met die optiese otvager ka voordele i terme va spoed, werksverrigtig e koste verwag word. Hierdie dissertasie beskryf die implemetasie va ' foto detektor i CMOS tegologie asook die otwerp va ' optiese otvager voorkat e ' klok e data herwiig stelsel. Die CMOS detektor verader die optiese iset a ' elektriese sei wat daara versterk word by die otvager voorkat. Die herwiig stroombaa prosesseer da die versterkte sei om die klok data te verkry e die data te hersikroiseer. Iduktiewe piek metodes was ekstesief i dit voorkat gebruik. Addisioele versterkig word hierdeur verkry om te kompeseer vir die swak respos va die foto detektor. Die herwiig stroombae is gebaseer op ' ie-lieêre stelsel tegiek wat otwerp is om die sikroisasie iformasie uit die data te herwi. Die klok e data herwiig stelsel bestaa uit twee eehede aamlik ' frekwesie-sluit-lus e ' fase-sluit-lus. Die frekwesie-sluit-lus verstel die ossillator se frekwesie i die bereik va die data tempo voordat fase sluitig plaasvid. Die fase-sluit-lus bepaal die relatiewe posisies va die data-e klok trasisies. iii

Uiversity of Pretoria etd Che, Y-J (5) ' Stelsel vlak simulasie is gedoe, e daar was gevid dat dit korrek fuksioeer e voldoe aa die gigabit vesel optiese spesifikasie. iv

Uiversity of Pretoria etd Che, Y-J (5) LIST OF ABBREVIATIONS AMS Austria Micro System Iteratioal BER bit-error rate CDR clock ad data recovery CM commo-mode CMFB commo-mode feedback DETFFs double-edge-triggered flip-flops FD frequecy detector FLL frequecy-locked loop IC itegrated circuit ISI itersymbol iterferece LA limitig amplifier LAN local area etworks LPF low pass filter NRZ oretur-to-zero OTA operatioal trascoductace amplifier PFD phase/frequecy detector PLL phase-locked loop PRBS pseudoradom bit sequece RGC regulated cascode SML spatially modulated light SNR sigal to oise ratio TIA trasimpedace amplifier VCO voltage-cotrolled oscillator TM typical-mea TSPC true-sigle-phase-clock WO worst-oe WP worst-power WS worst-speed WZ worst-zero v

Uiversity of Pretoria etd Che, Y-J (5) CONTENTS CHAPTER INTRODUCTION.......... Summary of Related Work..... Photodetectors........ Frot-Ed...... Preamplifier....... Postamplifier.....3 Clock ad Data Recovery Circuit...... Cotributios of this Study....3 Presetatio of the Dissertatio....3. Objective.......3. Dissertatio Outlie... CHAPTER PHOTODETECTOR......... Itroductio...... Implemetatio....3 Layout.. CHAPTER 3 FRONT-END.. 3. Itroductio..... 3. Trasimpedace Amplifier......... 3.3 Limitig Amplifier...... 3.3. Curret Referece Circuit........ 3.4 Auto-DC-Cotrol Circuits ad Postamplifier..... 3.4. Replica Biasig Cotrol... 3.4. Realizatio of the Postamplifier... 3.5 Layout...... CHAPTER 4 CLOCK AND DATA RECOVERY CIRCUIT.. 4. Itroductio..... 4. Clock ad Data Recovery Priciple....... 4.. Phase-Locked Loop...... 4... Voltage Cotrolled Oscillator... 4... Liear Phase Detector..... 4...3 Voltage-to-Curret Coverter ad Loop Filter...... 4.. Frequecy-Locked Loop...... 4... Frequecy Detector..... 4 4 6 7 8 9 9 9 7 8 8 8 3 6 8 9 9 34 36 36 36 37 37 48 5 57 57 vi

Uiversity of Pretoria etd Che, Y-J (5) 4... Charge Pump ad Loop Filter..... 4.3 Layouts.... CHAPTER 5 OPTICAL RECEIVER..... 5. Itroductio..... 5. Optical Receiver System..... 5.3 Layout...... CHAPTER 6 CONCLUSION.. 6. Photodetector...... 6. Frot-ed..... 6.3 Clock ad Data Recovery Circuit.... 6.4 Future Work.... Refereces... Appedix A: Derivatio for the Miority Carrier Cocetratio... Appedix B: Frequecy Detector Logic...... Appedix C: Circuit Diagrams..... 6 67 69 69 69 74 76 76 76 77 78 79 85 9 9 vii

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER INTRODUCTION The rapid global growth of iformatio techology has resulted i the eed to trasport large volumes of data across broadbad etworks such as optical commuicatio ifrastructures. Low loss ad high badwidth ca easily be achieved with optical fibres ad data ca be trasported over vast distaces without sigificat loss of sigal itegrity. However, there is a icreasig challege for users to directly ad seamlessly access high capacity iformatio from etworks. The multimedia used by users is ot efficiet for high speed operatios ad the throughput of etworks is thus limited. The eed for high speed commuicatio is therefore becomig more promiet. Data trasportatio ca easily be accomplished by implemetig short distace applicatios such as optical-based local area etworks (LAN). The success of these systems has ecouraged the tred of ad opportuities for optical commuicatio techology. Traditioally, performace rather tha cost has bee the desig goal of optical receivers. As a result, high-speed semicoductor techologies rather tha the CMOS process have bee widely implemeted ad have resulted i prohibitively expesive receivers. With the expasio of optical commuicatios it has become ecessary to desig the system for both performace ad cost. The itegratio i CMOS techology, together with its improved fuctioality ad performace, has accelerated the implemetatio of CMOS itegrated circuits. A typical optical system cosists of a trasmitter, a optical fibre ad a receiver. O the trasmittig side of the optical etwork, modulated iformatio is processed by a optical source to geerate a optical sigal. This optical sigal is trasmitted through a optical fibre ad fially impiges o the photodetector at the receivig ed. The receiver cosists of a optical detector, amplifier circuitry ad a clock ad data recovery (CDR) circuit, as depicted i Figure..

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio Photodetector Preamplifier Postamplifier CDR Amplifier circuitry Recovered data Figure. Optical receiver. The photodetector coverts the optical sigal ito a electric curret which is the coverted ito a voltage sigal ad processed by the amplifier circuitry to boost the voltage swigs. The fial module of the receiver, the sychroous stage, retimes ad recovers the origial data. I order to achieve high badwidth operatio, high volume productio ad low cost fabricatio, a silico-based photodetector has to be realised moolithically with CMOS receiver circuits. However, the ability to realise high-performace CMOS detectors presets a problem for the itegratio of optical commuicatio systems ad places a tight desig costrait o sesitivity ad resposivity. The objective of this dissertatio is to desig a fully itegrated optical receiver with a stadard CMOS process while achievig acceptable bit-error rate (BER) performace at gigabit data rate.. SUMMARY OF RELATED WORK.. Photodetectors I optical commuicatios photodetectors are required to covert icidet photos to a electric curret. Whe light pulses hit the detector, a fractio of photos peetrates the detector, geeratig a photocurret through the creatio of electro-hole pairs. The amout of the curret geeratio, hece the resposivity (R) of the detector, is affected by the characteristics of the semicoductor material of the detector, as described i Equatio. [], ηq R =, (.) h ν where η is the quatum efficiecy (which is strogly related to the absorptio coefficiet for light at the wavelegth of operatio ad the geometry of the detector), q is the uit electro charge, h is Plack s costat ad v is the frequecy of the photo. The absorptio coefficiet of the material is a fuctio of the wavelegth. Thus, i order to maximise the Electrical, Electroic ad Computer Egieerig

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio resposivity, the icidet light wavelegth should be spectrally matched to the operatig regio of the wavelegths of the detectors. The sesitivity of the detector is also iflueced by the amout of photos received. By wideig the photo receptio widow, the sesitivity ca be icreased. However, this also icreases the parasitic capacitace ad trades the system speed for sesitivity. Overall, detector capacitace ad/or the carrier trasiet time are the major factors that determie the speed of photodetectors. For high speed operatio, such as gigabit applicatios, it is ecessary to have a detector that provides low capacitace ad fast carrier trasiet time, while maitaiig reasoable sesitivity. The followig discussio explais some detector implemetatios. High resposivity ca be obtaied by implemetig the -well ad p-substrate i a stadard CMOS process at a wavelegth of 85 m []. Nevertheless, the radom motio of carriers of the diffusio process of this photodetector results i log curret tails i impulse respose, hece impedig the detector speed. Woodward et al. realized a detector based o the cocept of usig the -well as a screeig termial []. The slowly respodig carriers diffuse to the substrate, after which they are screeed by the -well from a set of lateral iterdigitated p- juctios that forms the active cotact of the detector. However, this methodology results i a very limited resposivity ad high juctio capacitace. The detector based o the twi-tub CMOS process [3] that uses the low doped epitaxial layer to form the itrisic regio of the p-i- photodiode ca achieve reasoable speed ad quatum efficiecy. However, this approach has the dager of latch-up uless appropriate desig measures are take. Furthermore, a protectio mask is required to block out the threshold-adjustig implatatio from the - epitaxial layer across which the detector is to be realised. Spatially modulated light (SML) detectors preseted i [4] implemet the masked ad umasked regios of the p - - juctios to amplify the spatial gradiet i carrier cocetratios. The differetial approach elimiates the log curret-tail effect ad leads to dramatic speed improvemet. Ufortuately, this approach trades resposivity for speed. Electrical, Electroic ad Computer Egieerig 3

Chapter.. Frot-Ed Uiversity of Pretoria etd Che, Y-J (5) Itroductio After the coversio of the icidet light to a electric curret by the photodetector, a lowoise, high-badwidth preamplifier must be implemeted so that this curret ca be coverted to a sufficietly large voltage. A strig of postamplifiers is the cascaded to the preamplifier for further amplificatio to a voltage level sufficiet for the reliable operatio of the succeedig circuits.... Preamplifier Preamplifiers are critical i optical receivers because speed, sesitivity ad the oise performace of optical commuicatio systems are maily determied by the frot-eds. Low-impedace amplifiers, high-impedace amplifiers ad trasimpedace amplifiers (TIA) are commoly used preamplifiers i optical commuicatio receivers []. I a low-impedace amplifier, a sufficietly small value for the bias resistor has to be chose to achieve a preamplifier badwidth that is greater tha or equal to the sigal badwidth. The voltage developed across the iput impedace ad the bias resistor is, thus, relatively small ad results i a low receiver sesitivity. The thermal oise of the bias resistor ca be reduced to a miimum by selectig a very large resistor. This results i a alterative desig: the high-impedace amplifier. Although all sources of oise i the highimpedace amplifier are reduced to a absolute miimum ad it has bee proved to have a very high sesitivity, the large iput RC time costat results i a frot-ed badwidth that is less tha the sigal badwidth. Itegratio ad equalisatio techiques have to be employed for the compesatio. This causes the circuits to suffer from a limited dyamic rage. Desigs based o trasimpedace amplifiers overcome the drawbacks of the highimpedace amplifiers. Compromises are achieved betwee the wide badwidth of the lowimpedace cofiguratio ad the high sesitivity of the high-impedace desig. I the trasimpedace amplifier, the egative feedback is implemeted (as show i Figure.) through a feedback resistor to provide a wide dyamic rage, a high badwidth ad a good sesitivity. Due to the above-metioed factors, trasimpedace amplifiers are the most popular approach for the frot-ed implemetatios i optical receiver systems. Electrical, Electroic ad Computer Egieerig 4

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio R f A(s) V o (s) Light iput Figure. Trasimpedace amplifier. Depedig o the applicatio, the multiple amplifyig stages may be ecessary. The maximum achievable value of the trasimpedace amplifier ope-loop gai is ultimately restricted by the propagatio delay ad phase shift of the amplifyig stage withi the feedback loop. Because a costat gai-badwidth product is maitaied at all times, at higher speed operatios, the ope loop gai is ecessarily reduced ad the umber of amplifyig stages is decreased to miimise the excessive phase shift. As a result, a sigificat amout of oise is produced by the feedback resistor. Thus, tradeoffs betwee speed, trasimpedace gai ad sesitivity exhibit as the desig challeges for a high speed TIA. Over the past decades, several TIA cofiguratios have bee developed. Toumazou ad Park [5] have reported high speed ad low oise commo-gate ad commo-source trasimpedace amplifiers. However, these cofiguratios require dual supplies ad oly the simulatio results were provided. The CMOS multi-stage TIAs [6] may become ustable. Regulated cascode (RGC) techiques have bee implemeted recetly to efficietly isolate the iput capacitace from the performace determiatio [7, 8, 9]. The RGC circuit behaves like a commo-gate trasistor with a large trascoductace as a result of the local feedback stage. Schrodiger et al. [] have implemeted a folded cascode techique for the trasimpedace amplifier. The desig ca work at low supply voltage ad the Miller capacitaces ca be reduced effectively. Both the RGC ad folded cascade-based TIAs provide high badwidths ad reasoable equivalet iput oise currets. However, with a low resposivity photodetector, these iput oise currets are ot low eough to achieve the required bit-error rate performace. Electrical, Electroic ad Computer Egieerig 5

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio I Razavi [], the feedback resistor is replaced by two capacitors (the gai defiitio etwork). Oe capacitor is used to sese the voltage across the secod capacitor ad retur a proportioal curret to the iput. If the gai of the amplifyig stage withi the feedback loop is much greater tha uity, the the circuit ca operate as a curret amplifier. The equivalet iput oise of this cofiguratio is effectively reduced because the gai defiitio etwork does ot cotribute oise. Although the desig cotributes oly 4.5 pa/ Hz at a data rate of 6 Mb/s, at higher data rates a slightly higher iput oise spectrum is produced ad the TIA fails to meet the performace requiremet. A differet approach for the trasimpedace amplifier is implemeted usig a commodrai-commo-source cofiguratio []. I the desig, a iput source follower is placed before the gai stage to prevet the Miller capacitace effect ad hece icrease the closed loop badwidth. It has bee reported that a iput oise curret desity of oly 4.6 pa/ Hz was measured at a data rate of Gb/s. Ufortuately large trasistors with trasistor widths i the rage of µm are required to achieve high gai ad reduce the oise curret. As a result, the badwidth becomes limited. I Nakahara et al. [3], the trasimpedace amplifier is implemeted by usig a sigle stage CMOS iverter that takes the advatage of the NMOS ad PMOS trasistors at the iput to achieve high gai [4]. The amplifier was reported to achieve a high sesitivity of -7 dbm at Gb/s ad a badwidth of over GHz with the feedback resistor set as high as 5 kω.... Postamplifier The postamplifier must have a voltage gai large eough to provide sufficiet voltage swig for the subsequet CDR circuit ad a large eough badwidth to amplify the sigal with egligible itersymbol iterferece (ISI). It also provides isolatio for the trasimpedace amplifier from the subsequet sychroous circuits, prevetig the corruptio of the data sigal from the clock feed-through of the sychroous circuits. Gilbert gai cells [5] have bee widely used i may commuicatio systems but they cosume a great voltage headroom ad require level-shift circuits betwee the stages. Thus, at a low supply voltage, the utility of the Gilbert gai cell becomes limited. Sackiger ad Fischer [6] have modified a covetioal CMOS limitig amplifier (LA), cosistig of NMOS differetial pairs, to achieve high badwidth. The iverse scalig techique is applied to all gai stages to effectively reduce the total load capacitace ad Electrical, Electroic ad Computer Egieerig 6

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio improve the frequecy respose. The stage badwidth is further ehaced with the implemetatio of iductive shut-peakig techiques [6, 7]. I Igels ad Steyaert [8], the cofiguratio of the postamplifier is based o a strig of modified, biased high-speed iverters that achieve both the liear ad limitig amplificatio. The biasig of the postamplifier is performed through a offset tolerat replica circuit...3 Clock ad Data Recovery Circuit Power spectrum S(f)/S().8.6.4. cotais o clock frequecy.5.5.5 3 Normalized frequecy (f/fb) Figure.3 NRZ power spectrum. The iformatio trasmitted over the optical etwork is geerally ecoded as oretur-tozero (NRZ) data stream. These NRZ sigals do ot cotai ay iformatio about the clock sigal or the spectral compoet at the data rate, as show i Figure.3. Oly by determiig the miimum spacig betwee cosecutive zero crossigs of the data stream ca the clock sigal be derived from the data. This iformatio ca be extracted through the implemetatio of o-liear circuits, such as high Q-filters or phase-locked loops (PLL) [9]. PLLs are ofte the solutio, due to the difficulty i itegratig moolithically high Q-filters with other circuits. Trasmittig data through a optical etwork, cosistig of a series of regeerators, results i a jittered data sigal. Thus, jitter geeratio of regeerators is strigetly specified. This specificatio is closely related to the closed-loop badwidth of the system ad has to be traded off betwee jitter suppressio, capture rage ad acquisitio rage []. With the Electrical, Electroic ad Computer Egieerig 7

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio uaided CDR circuit, the acquisitio rage is limited by the loop badwidth that tightes the costraits of desigig PLLs. Whe the differece betwee the data frequecy ad the voltage-cotrolled oscillator (VCO) frequecy is larger tha roughly the loop badwidth, the PLL will fail to lock. By icreasig the acquisitio rage of the phase-locked loop, the lockig problem ca be solved. However, this results i a uacceptable high output jitter. I moder desigs, this problem is overcome by icorporatig PLLs with a frequecy acquisitio scheme [5]. Two differet schemes are geerally adapted: oe that icorporates a phase/frequecy detector (PFD) as part of a sigle phase- ad frequecylocked loop ad the other that implemets a dual loop frequecy acquisitio. A sigle loop CDR cosists of a PFD that derives phase ad frequecy errors betwee the iput data ad VCO sigals. These error sigals are fed back to the VCO to cacel the static phase error ad icrease the frequecy capture rage. The PFD circuit is geerally implemeted i digital mode. It is required to covert the two output states to a average voltage through a charge pump ad a low pass filter [, ]. The actio of curret pumpig creates sigificat ripple ad produces great jitter at the VCO output. I a dual loop frequecy acquisitio, two cotrol iputs are fed to the VCO iput. Oe cotrol provides a low sesitivity tuig drive by the mai aalogue loop; ad the secod cotrol, drive by a digital frequecy-locked loop (FLL), provides a wide rage tuig [, ]. Whe the VCO frequecy is tued to the viciity of the sigal frequecy, the FLL remais relatively quiet ad does ot produce high jitter.. CONTRIBUTION OF THIS STUDY The emphasis o cost ad modest sesitivity targets for optical itercoect ad shortdistace optical commuicatio systems such as local area etworks operatig at short wavelegths (~ 85 m or shorter), has ecouraged the itegrated silico solutio. CMOS detectors allow short wavelegth detectio of light due to the fact that the silico-based detector has a cutoff wavelegth of approximately.6 μm ad a peak sesitivity ear the ifra-red regio []. Covetioal CMOS optical receivers are icapable of realisig high-performace, silicobased photodetectors. Such detectors are ofte implemeted exterally or itegrated ito receiver circuits with hybrid techology. With exteral implemetatio, the iput Electrical, Electroic ad Computer Egieerig 8

Chapter Uiversity of Pretoria etd Che, Y-J (5) Itroductio capacitace from the itercoectios ad bodig wire iductace teds to be large ad limits the badwidth of the receiver-amplifier circuit. Hybridised photodetectors have bee used widely to solve the problem. This is expesive to maufacture, however. The aim of this dissertatio is to develop a optical receiver system with a moolithically itegrated photodetector i commercial CMOS techology. The system is desiged to perform at Gb/s applicatio..3 PRESENTATION OF THE DISSERTATION.3. Objective The objective of this dissertatio was to desig a itegrated CMOS optical receiver for gigabit optical commuicatio systems. The followig describes the overall system specificatios that had to be achieved [3, 4]: The photodetector, frot-ed receiver ad CDR circuit had to be itegrated to provide a sigle chip CMOS itegrated circuit (IC) solutio usig a stadard.35 μm CMOS process techology. The circuit had to operate from a sigle 3.3 V supply voltage. The system had to comply with the Gb/s fibre chael specificatio. The photodetector optical receptio widow had to be optimised for the 5 μm or 6.5 μm optical fibre, ad the operatig regio of the wavelegths of the detectors had to be withi the rage from 77 m to 86 m. The receiver sesitivity had to be greater tha or equal to -7 dbm. The receiver had to operate withi the BER objective of -. The total output jitter of the IC had to be less tha 6 ps peak-to-peak to comply with the jitter budget specificatio..3. Dissertatio Outlie Chapter Chapter Chapter 3 Chapter 4 Chapter 5 Chapter 6 A brief itroductio is preseted. The choice of photodetector is discussed ad the chose detector is aalysed. The aalysis ad desig of the preamplifier is discussed ad the circuit is evaluated by meas of simulatio. The desig, layout ad simulatio of the CDR circuit are discussed. The overall system is evaluated. Coclusios to this dissertatio are provided. Electrical, Electroic ad Computer Egieerig 9

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER PHOTODETECTOR. INTRODUCTION I order to achieve high-speed performace, such as that required for gigabit applicatios, the SML-detector is preferable. The desig is based o the differetial structure (as show i Figure.). Whe the light strikes the detector, carriers are geerated oly below the umasked zoes ad cotribute to the major amout of the immediate curret output. The radom motio diffusive carriers i the substrate will fially reach p juctios as time progresses ad will yield the deferred curret output ad cotribute partially to the immediate curret. While takig the differece betwee the respose of the immediate carriers ad that of the deferred carriers, the log diffusive curret respose is elimiated, ad improves dramatically the speed performace that trades off with the resposivity. light iput metal diffusio photo-curret p- substrate Figure. Cross-sectio of the SML detector (adapted from [4]). The low resposivity ca be partially compesated for by the detector capacitace. It has bee show that the sesitivity of preamplifiers is proportioal to C D /R, where C D ad R are the capacitace ad the resposivity of the detector respectively [5]. The detector capacitace is maily determied by the juctio capacitace because the photodiodes geerally operate uder the reverse-bias coditio [6]. Thus, by icreasig the reversebias voltage, which i tur icreases the depletio width, the juctio capacitace ca be decreased.

Chapter. IMPLEMENTATION Uiversity of Pretoria etd Che, Y-J (5) Photodetector The juctio capacitace of the detector ca be calculated as follows [6]: The juctio potetial that exists across the p juctio is N A N D = V l, (.) T i φ j where N A (atoms/cm 3 ) is the acceptor impurity cocetratio, N D (atoms/cm 3 ) is the door impurity cocetratio, i = /cm 3 is the itrisic carrier desity i silico at room temperature ad V T.5 V is the thermal voltage. For p - juctio betwee the active implatatio ad the p- substrate of the.35 μm CMOS techology, N D 3.3 9 /cm 3 ad N A.3 5 /cm 3 [7], φ j.84 V. With the juctio potetial kow, the total width of the depletio regio for a applied reverse-bias voltage v R is w d = x x p = ε q S N A N D ( φ v ) j R = w do v φ R j, (.) where x ad x p are the juctio depths from the metallurgical juctio o the -type material ad p-type material respectively, ε S is the permittivity of silico ad q is the electroic charge. The capacitace of the reverse-biased p juctio is the give by C j εs A = = wd w d ε S A v φ R j. (.3) l (grid periodicity): 5.6 μm. x:.8 μm. x:.3 μm. Figure. Six-figer SML detector top view. Electrical, Electroic ad Computer Egieerig

Chapter Uiversity of Pretoria etd Che, Y-J (5) Photodetector The stadard fibre core diameter is 5 μm or 6.5 μm [3]. I order to receive the maximum optical power, the area of the photodetector shall be A PD_T 396 μm. Thus, for a grid periodicity of 5.6 μm (as depicted i Figure.), a maximum of figers ca be realised withi the defied width of 6.5 μm. The effective detector area is A PD = (.8 6.5 ) μm = 475 μm. Figure.3 idicates that the juctio capacitace is greatly depedet o the reverse bias voltage. As show, it is desirable to work at a higher reverse bias voltage. However, the maximum reverse bias voltage is limited by the supply voltage ad the iput voltage of the trasimpedace amplifier. For a reverse bias voltage of.6 V (from Equatios. to.3) the width of the depletio regio is computed to be.54 μm ad the juctio capacitace is 56 ff. 3 Detector capacitace [ff] 5 5 5 5 5 Reverse bias voltage [V] Figure.3 Detector capacitace vs. reverse-bias voltage for the chose CMOS techology (the effective area of the detector is 475 μm ). Whe light (which has a eergy greater tha or equal to the badgap eergy of the semicoductor) strikes the surface of the detector, photos are absorbed to create electrohole pairs. The umber of electro-hole pairs created depeds o the absorptio coefficiet of material at the wavelegth of the optical source. The silico detector has a sigificat absorptio coefficiet at wavelegths below its cutoff wavelegth (.6 μm). Figure.4 illustrates the absorptio coefficiet of silico as a fuctio of wavelegth. Electrical, Electroic ad Computer Egieerig

Chapter Uiversity of Pretoria etd Che, Y-J (5) 5 Photodetector Absorptio coefficiet [cm - ] 4 3 cuoff-off wavelegth =.6 um.4.6.8. Wavelegth [um] Figure.4 Absorptio coefficiets versus wavelegths of silico (adapted from []). Photo flux travels through the semicoductor expoetially [8], hece, the optical power, P(x), at a depth of x below the surface ca be defied as P α( λ)x ( x) ( R ) P e = f. (.4) Here, R f is the reflectivity at the etrace face of the photodetector, P is the icidet optical power level ad α(λ) (cm - ) is the absorptio coefficiet at a wavelegth of λ. Assume that carriers geerated at the depletio layer lost by recombiatio are egligible ad that those geerated withi a diffusio legth of the depletio-layer edges cotribute to a appreciable fractio of the recombiatio process. The, at worst case, the optical power beig effectively absorbed is across the depletio regio. Usig Equatio.4 ad assumig that the reflectivity teds to be ifiitesimal, the absorbed power is derived as α( λ) x α( λ) x ( e e ) P = P, (.5) where x ad x are the distace from the detector surface to the top ad bottom of the depletio regio respectively. The importat characteristic quatum efficiecy η of a photodetector is the ratio betwee the umber of the electro-hole carrier pairs geerated ad icidet photo of photo eergy hv []. Relatig the quatum efficiecy to power absorptio i Equatio.5, η is From Equatio., x ad x p ca be derived ad calculated. P hv α( λ) x α( λ) x η = = e e. (.6) P hv Electrical, Electroic ad Computer Egieerig 3

Chapter Uiversity of Pretoria etd Che, Y-J (5) Photodetector x = wd vr = φ ( N N ) D A ( N N ) j.6 m, ad (.7) wd vr x =.54 μm φ =. (.8) p A D j Resposivity [A/W].6.4...8.6.4..38 A/W at wavelegth = 86 m.4.5.6.7.8.9. Wavelegth [um] Figure.5 Resposivity of the -diffusio p-substrate SML detector vs. wavelegth. At the wavelegth of 86 m ad α(λ) of 7 cm -, the computed quatum efficiecy is η.. Because half of the area of the photodetector is masked with floatig metals, whe the detector is illumiated with light, oly half of the photo flux is absorbed by the semicoductor, while the rest is reflected. Thus, the effective resposivity oly has a value of that computed with Equatio.. The resposivity of the detector at the wavelegth of 86 m is R =.38 A/W. The resposivity at differet wavelegths is show i Figure.5. The curret respose of perpedicular p juctio detectors is maily determied by the trasportatio of the miority carriers (which ca be represeted by the cotiuity equatio as described i Equatio.9) i the regio below the depletio regio [4]. p t = D p x D p y p τ g αx ( t, y) e, (.9) here p is the miority carrier cocetratio i the p-type doped layer, D is the diffusio coefficiet of the miority carrier i the p-type doped layer, τ is the miority carrier Electrical, Electroic ad Computer Egieerig 4

Chapter Uiversity of Pretoria etd Che, Y-J (5) Photodetector lifetime ad g(t,y) is the electro geeratio rate at the lower border of the space charge regio. With appropriate boudary coditios, the photogeerated miority-carrier profile is derived as (Appedix A) ( x, y, t) = p p, st ( x, y) A m= = m ( ( / Dτ ) ( mπ / a) (( ) π / b) e ) D t mπ ( ) π si x cos y, (.) a b where p,st (x,y) is the steady-state solutio, a ad b are the depth ad the legth of a sigle figer respectively, ad the coefficiets {A m } is A m ( ( x, y) ) = b a mπ ( ) p, st si x cos π y dxdy. (.) ab b a b The curret desity profile as a fuctio of frequecy has bee solved aalytically, from which the 3-dB frequecy respose of the detector was derived [4]. Whe /l is assumed to be much larger tha α, the -3-dB frequecy is give by f 3dB πd 3, (.) l L where l is the grid periodicity of metal figers of idetical structures ad L is the electro diffusio legth. With the aalogy to the argumet for the trasportatio of the miority carriers below the space charge regio, the carrier profile above the space charge regio has also bee postulated [4]. If the detector speed is limited by the hole diffusio, the the -3-dB frequecy of the detector is πd p f 3dB 3 (.3) lx l y Lp with D p beig the diffusio costat of the holes i the -doped layer, l x the distace betwee the surface ad the lower poit of the space charge regio, l y the grid periodicity ad L p the diffusio legth of the holes. Applyig the model described i Equatio., Figures.6 ad.7 illustrate the miority carrier profiles i the p- substrate after the diode was beig illumiated for ps. The profiles below demostrate oly the resposes of a basic vertical p photodiode. As show, whe time progresses, the diffusio process due to the trasiet respose almost dimiishes oly after ps. Electrical, Electroic ad Computer Egieerig 5

Chapter Uiversity of Pretoria etd Che, Y-J (5) Photodetector (a) (b) Figure.6 (a) Total ad (b) trasiet miority carrier cocetratios below the p juctio 3 ps after illumiatio. (a) (b) Figure.7 (a) Total ad (b) trasiet miority carrier cocetratios below the p juctio ps after illumiatio. The slow trasportatio mechaism is a result of the radom motio of carriers of which the frequecy respose of a basic p juctio detector with a ifiite dimesio ca be described as [4] f stadard. 354 ( αl ) πτ. (.4) Comparig Equatios. ad.4, the speed performace of the detector is expected to improve greatly whe the differetial structure is implemeted. Electrical, Electroic ad Computer Egieerig 6

Chapter Uiversity of Pretoria etd Che, Y-J (5) Photodetector With curret CMOS techology, the diffusio layers are made shallow. Thus, whe the detector is illumiated, the miority carriers geerated i the diffusio layer are immediately swept across the p juctio. This results i o diffusio i the -doped top layer. Cosequetly, it reduces the maximum hole diffusio legth ad has a fast hole respose curret. Thus, the detector speed of the diffusio ad p- substrate juctio is domiated by electro diffusio. For a SML detector with a grid periodicity of 5.6 μm, the detector speed is approximately equal to f -3dB 8.5 GHz..3 LAYOUT The layout of the photodetector, as show i Figure.8(a), was completed i the.35 μm Austria Micro System Iteratioal (AMS) CMOS process [4]. Figure.8(b) depicts the figer pitch i a cross-sectioal view. The area of the detector is 3787.5 μm. l = 5.6 µm 6.6 µm.3 µm (a) 6.5 µm metal diffusio l = 5.6 µm.3 µm p- substrate (b) Figure.8 (a) Layout of the photodetector; (b) Dimesios i a illustrative crosssectio. Electrical, Electroic ad Computer Egieerig 7

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER 3 FRONT-END 3. INTRODUCTION The preamplifier is ecessary to covert the photocurret ito a voltage. Further amplificatio is ofte achieved by a cascade of postamplifiers because the voltage produced by the preamplifier is ormally iadequate for the clock ad data recovery circuit. I this chapter, the operatio ad desig of the trasimpedace amplifier ad postamplifiers are discussed. The performace of the frot-ed circuit was evaluated by meas of simulatio. 3. TRANSIMPEDANCE AMPLIFIER The performace requiremet of the preamplifier is iflueced by the characteristics of the photodetector. For the SML detectors, the bit-error rate is determied by [4] BER = erfc ISI S v N = erfc S ISI v S N, (3.) where ISI v is the statistical variatio of the itersymbol iterferece, S is the sigal power ad N is the oise power. Assume that the TIA badwidth is larger tha.7 times the bit rate ad that the ISI ad the total itegrated oise are well compromised. The the ISI ca be assumed to be egligible. At the BER of -, the computed required sigal to oise ratio (SNR) is 6.97 db. For a photodetector with a.38 A/W resposivity ad a -7 dbm optical iput power, the maximum allowable equivalet iput oise curret at the data rate is approximately 34 A. From Figure., the closed loop trasimpedace gai ca be approximated as 8

Chapter 3 V I Uiversity of Pretoria etd Che, Y-J (5) out ( s) AOL () s = A () s PD s C OL i R F R F C out R out s () s ( C R C R ) i A F R F out out A A () s R F () s R F Frot-Ed, (3.) where A OL (s) is the ope loop gai, A(s) is the amplifier gai (as show i Figure.), R F is the feedback resistor, C i is the total iput capacitace, ad C out ad R out are the output capacitace ad output resistace respectively. The total iput capacitace is ormally large compared to the output capacitace ad with a large A(s) the domiat pole is assumed to be located at the iput. From Equatio 3., the upper 3-dB frequecy, ω -3dB, of the trasimpedace amplifier ca be described as i ( s) A ω 3dB =. (3.3) C R For the basic circuit of a trasimpedace amplifier, as illustrated i Figure., the equivalet iput-referred oise is approximated as [8] ktω C eq, i 9 μcgs i 6 F L 4 kt R i ( Vgs VTH ) F, (3.4) where g m represets the trascoductace, C gs is the gate-source capacitace, V gs is the gate-source voltage ad V TH is the threshold voltage of the preamplifier s iput trasistor, ad µ is the mobility of the miority carriers. It is clear that at low frequecies, the thermal oise of the feedback resistor becomes domiat. Thus, it is desirable to miimise the oise by implemetig a large feedback resistace, while compromisig the closed loop badwidth by icreasig the ope loop amplifier gai. Ufortuately, the amplifier gai A(s) is frequecy depedet ad the chose circuit techology may costrai the badwidth requiremet of the system. Furthermore, the higher order poles are lowered whe the ope loop gai icreases, thus decreasig the phase margi ad limitig the stability requiremet. I order to obtai the effective iformatio from the SML photodetector, the sigal is extracted differetially to elimiate the diffusive carriers. It would be possible to implemet a fully differetial preamplifier. However, as discussed previously, oe of the preamplifiers other tha the CMOS iverter trasimpedace amplifier [3] ca achieve a acceptable oise performace. I the implemetatio, as illustrated i Figure 3., two idetical trasimpedace amplifiers were coected to the immediate ad the deferred Electrical, Electroic ad Computer Egieerig 9

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed outputs of the detectors. The subsequet differetial postamplifiers were implemeted to extract the differece respose. R f Immediate curret A(s) Auto DC cotrol R f Limitig amplifier/ Postamplifier V out Deferred curret A(s) Auto DC cotrol Figure 3. Overview of the receiver frot-ed. Figure 3. shows the implemetatio of the topology of the trasimpedace amplifier i trasistor level. The cofiguratio is based o the desig i [3]. I Rf M Vout M Figure 3. Schematic diagram of the trasimpedace amplifier. The ope loop gai of the trasimpedace amplifier is give by A OL () s R F ( gm gm )( gds gds ) ( sc R )( sc R ) i f out out, (3.5) where g ds ad g ds are the coductace of M ad M, ad C i ad C out are the iput ad output capacitaces respectively. Usig Equatio 3., the quality factor ca be derived as Q A ( s) i F out out =. (3.6) C i R C F R C For high speed applicatios it is desirable to employ Q values larger tha.5 to icrease the badwidth. However, whe Q becomes too large the peakig effect becomes serious ad leads to sigal distortio. For practical applicatios, Q.85 is required to allow a Electrical, Electroic ad Computer Egieerig C out R R out

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed overshoot of less tha %. I order to provide a adequate iput voltage to bias the photodetector, the threshold voltage of the amplifier is set to ( W ) L ( W ) ( W ) L ( W ),, K p K p Vth = VTH ( VDD VTHp ) =.6, (3.7),, K K L L where V TH ad V THp are the threshold voltages of the NMOS ad PMOS trasistors respectively. With the threshold voltage defied, this leads to (W/L) /(W/L) 3. As described i Equatio 3.4, the miimum trasistor chael legth is ecessary to miimise the iput-referred oise curret. Large trasistor widths were chose to reduce the output resistaces of M ad M, thus, placig the frequecy of the output pole a few degrees higher tha that of the iput pole. By lettig Q =.8 ad assumig the output capacitace of approximately ff, the calculated feedback resistace is 3 kω. A large value resistor ca be realised with a small trasistor, hece reducig the phase shift that would be itroduced by a log itegrated resistor. However, whe the ope loop gai of the amplifier is sufficietly large, the trasimpedace gai is approximately equal to the feedback resistace, as ca be show from Equatio 3.. This implies that the frequecy respose is highly depedet o the quality of the feedback resistor. The threshold voltages of MOS resistors are greatly iflueced by the model processes. For the chose topology, depedig o the type of MOS resistor, it is especially sesitive to the worst-zero (WZ) or the worst-oe (WO) case ad easily fails to meet the miimum badwidth requiremet with either of the two process corers. Differet topologies could be implemeted to solve the problem. However, oe of the other literature studied ca provide a satisfactory oise performace. Due to the ifluece of process variatios, the feedback resistor has to be realised with available resistor implemetatios. The high resistive-poly was implemeted as it has the lowest temperature coefficiet ad the highest sheet resistace of. kω/ [7] cotributig to a relative low parasitic capacitace. Ufortuately, a miimum of five squares is required for the layout of a high resistive-poly module, which traslates to a miimum resistace of 6 kω, Therefore, the feedback resistor was realised by coectig two 6 kω high resistive-polys i parallel. - Simulatio The small-sigal equivalet circuit of the photodetector is modelled by a parallel combiatio of a curret source ad a capacitor. For a iput photocurret of A ad Electrical, Electroic ad Computer Egieerig

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed ff detector capacitace, the characteristic of the preamplifier i the frequecy domai is illustrated i Figure 3.3. 45 Coversio gai [V/I] 4 35 3 5 5 5 Worst-speed resistor model Typical-mea resistor model Worst-power resistor model 4 5 6 7 Frequecy [Hz] 8 9 Figure 3.3 Frequecy respose of the trasimpedace amplifier across differet resistor models with worst-speed (WS) trasistor model. Table 3. shows the frequecy respose of the trasimpedace amplifier for differet process coditios. The typical-mea (TM), typical-mea MOS trasistors ad typicalmea high resistive-poly, badwidth of the TIA is 9.5 MHz ad the trasimpedace gai is approximately 69.7 dbω. As ca be see, the TIA badwidth is larger tha 7% of the bit rate for all process coditios. I the process corer with the worst-speed MOS trasistors ad worst-speed high resistive-poly, the frequecy respose of the TIA is capable of achievig a badwidth of 74. MHz. Table 3. TIA frequecy respose across differet process coditios. Trasistor model Resistor model Typical-mea Worst-speed Worst-power Badwidth [MHz] Coversio gai [dbω] Badwidth [MHz] Coversio gai [dbω] Badwidth [MHz] Coversio gai [dbω] Typical-mea 9.5 69.7 8.3 69.7 97 69.5 Worst-speed 795. 7.5 74. 7.6 779. 7.4 Worst-power 48 67.5 93.4 67.5 74 67.4 The aalysis of the iput referred oise of the preamplifier is performed ad plotted i Figure 3.4. Assumig this oise is badwidth limited ad has a badwidth from khz to Electrical, Electroic ad Computer Egieerig

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed GHz, the the equivalet iput referred oise curret is approximately 8 A. For the BER of -, it requires a miimum optical iput power of -9.7 dbm. Equivalet iput referred oise [A/sqrt(Hz)] x - 9 8 7 6 5 4 3 5 6 7 8 9 Frequecy [Hz] Figure 3.4 Equivalet iput referred oise curret desity of the preamplifier. 3.3 LIMITING AMPLIFIER [6] Limitig amplifiers are implemeted as part of the postamplifiers to boost the biary voltage swigs produced by the TIA ad to isolate the sychroous stages from the trasimpedace amplifier. I order to achieve sufficiet overall gai ad meet the miimum badwidth requiremet for the gigabit applicatios, a multi-stage, low-gai prestage is ecessary for the optimal desig. Traditioally, a cascade of commo-source differetial pair gai stages is used to achieve the high-gai badwidth product. Selectig large widths for all the trasistors ad large curret tails, a reasoable badwidth ad oise figure ca be achieved but at the cost of power cosumptio. α: scalig factor. Figure 3.5 CMOS limitig amplifier block diagram. The modified LA employs the iverse scalig techique, as show i Figure 3.5. A scalig factor α is applied to the widths of all MOS trasistors ad curret sources of the drive Electrical, Electroic ad Computer Egieerig 3

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed gai stage such that the trasistor sizes i the drivig stage are α times larger tha those i the drive stage. Assumig that each gai stage has oe domiat pole ad it is strogly depedet o the total load capacitace of the stage C tot (which cosists of the stage output capacitace C o, the wirig capacitace C w ad the iput capacitace C i of the ext stage), applyig a scalig factor to the drive stages, the badwidth extesio factor of the th gai stage ca be defied as C C C κ =. (3.8) o i w ( ) ( Co Ci ) Cw α As show, a sigificat badwidth extesio is achieved for all stages. Hece, a obvious improvemet i the overall badwidth ca be obtaied. The circuit topology of idividual gai stages is illustrated i Figure 3.6. Each stage is a basic commo-source differetial. I order to alleviate the badwidth degradatio caused by the parasitic capacitaces, active iductors were implemeted for badwidth ehacemet. The active iductor cosists of a NMOS trasistor M3 ad a PMOS resistor R. By chagig the PMOS resistace, various iductace values ca be obtaied. M3 R R M4 Vout Vout Vi M M Vi Vbias Mct Figure 3.6 Circuit topology of a idividual gai stage. Assumig the products C L C gs3 ad C gs3 C μ3 are egligible, the the impedace Z L of the active iductor ca be approximated by Z L g m3 s sr( Cgs3 Cμ3 ) [ g RC ( C C )] m3 μ3 gs3 L, (3.9) where C gs3, C μ3 ad C L are the gate-source, gate-drai ad load capacitaces; g m3 is the trascoductace of the trasistor M3; ad R is the PMOS resistace. If the coditio g ( C C ) m3 gm3rc 3 gs3 is satisfied, the the iductive peakig is achieved. >> μ (3.) L Electrical, Electroic ad Computer Egieerig 4

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed The voltage gai of each cell ca be expressed as g A = g m m3 s with poles ad zero sr ( ) Cgs3 Cμ3 [ g ( )] [ ( ) ] m3rc μ3 Cgs3 CL g m3 s R CL Cgs3 Cμ3 Cgs3Cμ3 gm3 p g p z p R = R m3 R C ( C C ) g m3rc μ 3 ( C gs3 CL ) [ C ( C C ) C C ] L ( C C ) gs3 μ 3 g gs3 m3 μ 3 gs3 μ 3 L gs3 μ 3 (3.). (3.) From Equatio 3., the domiat pole ca be approximated by p. Settig the zero equal to p, p becomes the domiat pole ad improves the badwidth. The serious overshoot is preveted by selectig the Q-factor Q = g m3 R C [ C ( C C ) C C ] L L C gs3 gs3 g μ3 m3 R C μ3 gs3 μ3 =.77. (3.3) Due to the relatively low resposivity of the photodetector, the iput photocurret is i the rage of oly hudreds of ao-amperes. A moderate coversio gai is provided by the preamplifier to compesate betwee system sesitivity ad badwidth. I order to amplify the voltage swig to a amplitude of 4 mv peak-to-peak, a voltage gai of at least 56 db (784) is required, while maitaiig a sufficiet badwidth. The high-gai high-speed requiremet forces the implemetatio of a log chai postamplifier. A te-stage amplificatio is ecessary ad the effect of DC couplig resultig from cascadig is remedied by DC-cotrol circuits. The differetial amplifier is desiged with a voltage gai of. A scalig factor of. is applied to the limitig amplifier to prevet a serious capacitive loadig of the first commo-source differetial stage to its precedig stage. DCcotrol circuits are also implemeted immediately after the two sigle-eded TIAs to provide adequate DC iput voltages to the limitig amplifier ad to cacel the DC offset voltages from the TIAs. A moderately large width (W, = 6. μm) for the iput trasistors was chose for the first-stage limitig amplifier i order to reduce a systematic offset voltage ad to provide a moderate iput capacitace. To achieve a voltage gai of, it leads to a width with a value of W 3,4 = 4.3 μm for the load trasistors M3 ad M4. The miimum chael legth is used for trasistors M-M4 to achieve a high frequecy respose. A large tail curret is required to esure that the circuit meets the badwidth Electrical, Electroic ad Computer Egieerig 5

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed requiremet. However, it also has to be kept moderate for trasistors to operate i saturatio. A tail curret of I tail.4 ma was chose to meet the coditios. Usig Equatio 3.3, a PMOS resistace of R 3 kω is required to set Q =.77. This sets the ratio (W/L) R. The sizes of trasistors for the followig stages are scaled subsequetly. The complete circuit diagrams ca be foud i Appedix C. 3.3. Curret Referece Circuit M3 M4 I I I M5 M M R Figure 3.7 Curret referece circuit. The bias currets of the LA circuit ad the rest of the circuits discussed i the followig chapters were implemeted via curret mirrors from curret referece geerators. Cosider the referece circuit show i Figure 3.7 [5]. PMOS trasistors M3 ad M4 form a egative feedback loop ad force the currets I = I = I, (3.4) whe the PMOS trasistors with idetical dimesios are assumed. The gate voltages of the trasistors M ad M are equal. If all four trasistors operate i the saturatio regio, applyig Kirchoff s voltage law aroud the gate-source loop cosistig of M, M ad R gives k ' N I I VT = ( W ' ) k ( W ) L N L V T IR. (3.5) Igorig the body effect ad all other secodary effects ad lettig (W/L) = K(W/L), Equatio 3.5 gives k ( W ) ' N Hece, the referece curret I ca be represeted as L K I = gm =. (3.6) ( K ) R Electrical, Electroic ad Computer Egieerig 6

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed I = ' k ( W ) R K N L. (3.7) As show, the curret is idepedet of the supply voltage. If miimum legth trasistors were implemeted, the chael-legth modulatio effect becomes promiet ad the circuit behaviour is udesirable. I order to miimise the mismatch of the curret i all braches ad the ifluece of the short-chael effect, relatively large trasistors of W/L = 6.85 μm/.5 μm were chose for a referece curret of μa. The W/L ratio betwee M ad M was chose to be so as to reduce the size of M ad to limit the size of the resistor. From Equatio 3.7 the resistace was calculated to be i the regio of.46 kω. The resistor was realised with a poly resistor. As with all the other resistor types it is least process depedet ad does ot vary with voltages. Simulatio The frequecy respose of the six-stage limitig amplifier is show i Figure 3.8 ad Table 3.. The aalysis was performed with a iput voltage of mv. The voltage gai of the limitig amplifier is basically determied by the operatio of NMOS trasistors ad the badwidth ehacemet depeds o the quality of the PMOS resistors i cojuctio with the trascoductace of the iput trasistors of the differetial amplifiers. Voltage gai [V/V] 45 4 35 3 5 5 Typical-mea resistor model Worst-speed resistor model Worst-power resistor model 5 3 4 5 6 7 8 9 Frequecy [Hz] Figure 3.8 Frequecy respose of the limitig amplifier across differet resistor models with worst-speed trasistor model. Electrical, Electroic ad Computer Egieerig 7

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed Resistor model Trasistor model Table 3. LA frequecy respose across differet process coditios. Typical-mea Worst-speed Worst-power Badwidth [MHz] Voltage gai [db] Badwidth [MHz] Voltage gai [db] Badwidth [MHz] Voltage gai [db] Typical-mea 33 34.6 96.4 33.4 58 35.7 Worst-speed 875.9 3.6 766. 3.9 645.9 7 Worst-power 56.8 35.7 8.9 34.3 7.4 37.8 Worst-zero 77. 33 656. 3. 679. 3 Worst-oe 45 35.9 97.8 34.5 584.4 38 I the worst-zero coditio, NMOS trasistors are relatively weak ad the absolute threshold voltage of PMOS resistors becomes as small as.487 V. As a result, the NMOSdetermied trascoductace becomes smaller tha that i the typical-mea eviromet, ad a larger PMOS resistace is produced. I the worst-zero coditio, the system, however, barely meets the coditio for iductive peakig, as described i Equatio 3., ad results i a moderate badwidth of betwee 77 ad 656 MHz for all resistor models. Whe the NMOS trasistors are weak, the deviatio of resistor models from the typicalmea resistor coditio causes degradatio i both the badwidth ad voltage gai. The worst sceario occurs i the worst-speed trasistor models ad worst-power resistor model. The resultat badwidth ad voltage gai are 645.9 MHz ad 7 db respectively. However, this is cosidered to be acceptable. The voltage gai ad badwidth i the typical-mea simulatio are approximately equal to 34.6 db ad.3 GHz, respectively. 3.4 AUTO-DC-CONTROL CIRCUITS AND POSTAMPLIFIER [8] The DC-cotrol circuits ad postamplifier are based o the desig i [8]. They serve the fuctios as to set the commo-mode iput voltages for their succeedig circuits ad to provide a further amplificatio. The desig cosists of a strig of modified iverters biased at their threshold voltage. Through the implemetatio of offset tolerat replica biasig circuits, the bias voltage of the iverters is accomplished ad forced to the threshold voltage of its replica. Upo receivig a small iput sigal, the iverters behave as liear amplifiers ad clippig occurs at the ed of the chai. With a larger iput sigal, the first clippig at the rail-to-rail voltage is simply shifted forward ad results i a large dyamic rage. Electrical, Electroic ad Computer Egieerig 8

Chapter 3 3.4. Replica biasig cotrol Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed The correct threshold voltage settig of the iverter strig is critical. The o-optimal biasig of iverters will result i a degradatio of the duty cycle of the sigal ad ca be remedied by implemetig a replica biasig scheme. The replica uses the egative feedback to force the DC output voltage of the iverter chai V o (s) equal to the bias voltage V b by level-shiftig the sigal. Passig the output voltage sigal to a low-pass filter, the average sigal ca be measured. Oce the mea sigal is obtaied, it is preseted to the iput of the comparator ad is compared with the replica s threshold voltage. The output of the comparator is the set to a level shifter that adjusts the threshold of the iverter ad forces the DC output to V b. Iput sigal V i (s) - A (s) - Output V o (s) - A FB (s) LPF, F(s) Bias V b Figure 3.9 Mathematical model of the replica biasig cotrol. Figure 3.9 illustrates the priciple of replica biasig. The mechaism of the priciple ca be derived as FB ( s) A ( s) F( s) () s A () s F() s AFB Vi ( s) A ( s) () s A () s F() s Vb A Vo () s =, (3.8) A FB where F(s) is the trasfer fuctio of the low-pass filter (LPF). At the frequecy below the -3-dB badwidth of the low-pass filter, F(s), assume A FB (s)a (s) >> ad A FB (s) >>, the the DC bias of V o (s) is V o ( s) Vb. (3.9) Due to parameter variatios i the circuit, there is a slight deviatio from the desired bias voltage. This stadard deviatio is iversely proportioate to the square of the voltage gai A. Thus, by elargig A, the effect of mismatch ca be reduced. 3.4. Realisatio of the Postamplifier Applyig a iput photocurret of A to the preamplifier ad havig a sigle-eded differetial amplifier cascaded to the te-stage limitig amplifier, a output voltage of 566 mv is achieved. A gai of at least.9 is required to amplify this voltage to a 3.3 V rail-to- Electrical, Electroic ad Computer Egieerig 9

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed rail voltage. As a small amplificatio is required, oe replica-biased iverter strig was implemeted i the frot-ed. The feedback loop of the replica biasig cosists of three modified iverters for the postamplifier or oe modified iverter for the DC cotrol circuit, a comparator ad a level shifter that also performs a extra iversio. For the postamplifier implemetatio, due to the high speed requiremet i the sigal path, multiple iverter stages are ecessary as the gai of each stage is limited. The voltage gai of the DC cotrol circuit, typically a gai of uity, does ot have to be high as it oly has to set the biasig poit for its succeedig circuits. The biasig circuit would try to compesate for ay DC shifts preset i the sigal output. I order to avoid a degraded biasig resultig from the DC deviatio due to frequecy compoets larger tha the -3-dB frequecy of the iverters, badwidths of the iverters i the sigal path must be sufficietly larger tha the sigal s badwidth. However, the badwidth of the stadard Class B amplifier is limited by its high gai characteristic. Modificatio of the iverter is doe by coectig a diode-coupled trasistor to the output, as show i Figure 3.(a), to limit the gai ad achieve high badwidth. By replacig the diode-coupled trasistors with active iductors, a further badwidth extesio is achieved. I the cofiguratio, the NMOS trasistor is preferred over a PMOS as it is smaller for a give g m ad the o-zero bulk-source voltage further ehaces the trascoductace. As a result, this topology has a miimal icreased capacitive loadig. The shifter has the same topology (refer to Figure 3. (b)) as it is also i the sigal path ad has to provide a comparable badwidth. Thus, it serves as a level shifter ad as a ivertig amplifier with a limited gai. The NMOS i the shifter acts as the iput for the sigal ad the PMOS performs the level shiftig. Vi M M3 Vout Vbias M M3 Vout M Vi M (a) (b) Figure 3. Circuit topology of (a) the high-speed iverter; ad (b) the level shifter (adapted from [8]). Based o the topology, similar equatios are derived to describe both the iverter ad the shifter. For simplicity, assume that the MOS resistor value of the active iductor is small. The the output voltage of the iverter is Electrical, Electroic ad Computer Egieerig 3

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed g m gm V = o Vi, (3.) gm3 gm3 ad the output voltage of the level shifter is V g g m m o = Vi Vbias. (3.) gm3 g m3 As will be show later, the voltage gai determied by trasistors M ad M3 becomes overly effective i the worst-zero trasistor models. I order to reduce the effect, a small ratio (W/L) /(W/L) 3 has to be implemeted. However, the ratio (I D (W/L) )/(I D3 (W/L) 3 ) has to be large eough to achieve a adequate voltage gai while providig a adequate iverter threshold voltage. Compromisig all the factors, the trasistor sizes are set with a ratio (W/L) /(W/L) = ad relatively large widths (W = 4 μm, W = 8 μm ) are used to provide fast rise ad fall time. Settig the drai curret of trasistor M3 to I D3.4 I D, the width of M3 is calculated to be 4.45 μm. This results i a voltage gai of approximately with a.85 GHz badwidth. The major compoets of the replica feedback loop are the RC low-pass filter ad the comparator (Figure 3.). The output DC voltage of the replica biased circuit is measured by the loop filter. It is compared to the replica s threshold ad adjusted through the loop. The -3-dB frequecy of the loop filter has to be sufficietly low to esure stability as the gai of the cascaded iverters is high at the mid-bad frequecy. Ufortuately, the lower the corer frequecy the loger the settlig time is. M6 M3 Vbias M4 R M M M M M M5 CLPF M7 M8 M9 Vi Figure 3. Replica feedback loop. For a low-corer frequecy, the resistor ad capacitor values are rather large. I order to miimise the implemetatio area ad prevet excess phase shift resultig from the implemetatio of large resistors ad capacitors, the resistor was replaced by a PMOS Electrical, Electroic ad Computer Egieerig 3

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed trasistor i its triode regio ad a large capacitor was realised by utilisig the Miller effect with the comparator as gai elemet. Noetheless, the postamplifier was implemeted at the last stage of the frot-ed where the iput was large. As the iput voltage becomes large, the PMOS trasistor eters the saturatio regio ad results i a icreased resistace value. With the large iput sigal, the behaviour of the MOS trasistors becomes udesirable. I order to solve the problem of the fial postamplifier stage, a additioal NMOS trasistor was placed i parallel with the PMOS trasistor. However, the cost of a additioal trasistor is the icreased parasitic capacitace ad the degraded amplifier frequecy respose. The Miller capacitace ca be expressed as C Miller LPF ( A ) = C, (3.) where A V is the comparator gai. The comparator is realised with a simple operatioal trascoductace amplifier (OTA). The specificatios of the OTA are ot too striget. The gai V V ( r // r ) A = g, (3.3) m o o4 however, should ot be too low, about 36.9 db. The chael legths ad widths of the iput trasistors are made large (W, = μm, L, =.5 μm) to avoid systematic offset ad to reduce the effect of process variatios. A costat trascoductace is biased with a tail curret of 4 ma. With M level-shifter of the level shifter (Figure 3.(b)) coected to the output of the OTA, it defies the gate-source voltage of M level-shifter, V SG,level-shifter = V DS4,OTA. With perfect matchig ad zero iput voltages, it requires I D3,OTA = I D4,OTA D,level shifter ( W / L) 3,OTA ( W / L) 4,OTA ( W / L),level shifter = I. (3.4) This sets the size of M3 OTA ad M4 OTA to (W 3,4 ) OTA = 34 μm ad (L 3,4 ) OTA =.6 μm. As the parasitic capacitaces of the trasmissio gate, M8-M9, further icrease the output capacitive loadig to the postamplifier, it is ecessary to keep the sizes of the trasistors of the trasmissio gate small, which leads to the implemetatio of miimum width trasistors, M8-M9. For a low-pass resistace of approximately 5 kω, it sets the chael legths for trasistors M8-M9 to L 8 = 7.4 μm ad L 9 =.5 μm. To obtai a low-corer frequecy of about 5 khz, it requires a pf low-pass capacitor C LPF to be placed i the Miller cofiguratio. The output voltage of the OTA sets the biasig poit of the shifter. Electrical, Electroic ad Computer Egieerig 3

Chapter 3 3 Uiversity of Pretoria etd Che, Y-J (5) Worst-zero Worst-speed Frot-Ed Voltage gai [db] - - -3 Worst-oe Worst-power Typical-mea -4-5 -6 3 4 5 6 7 8 9 Frequecy [Hz] Figure 3. Postamplifier frequecy respose across differet trasistor process coditios with typical-mea resistor model. The characteristics of the postamplifier are illustrated i Figure 3. ad the frequecy respose across all process coditios is give i Table 3.3. Figure 3. depicts the frequecy resposes of the circuit to a mv iput voltage across all the trasistor models. It ca be see that the circuit is relatively sesitive to the process coditios. The hole mobility of PMOS trasistors is itrisically smaller tha the electro mobility of NMOS trasistors, ad thus large PMOS trasistors are required to provide a reasoable gai of g mp /g m. I the worst-zero simulatio, PMOSs become very strog ad NMOSs are relatively weak, cosequetly producig a extremely large gai. I order to prevet severe badwidth degradatio, the umber of replica biased stages is limited. The worst case speed badwidth of the postamplifier is approximately equal to GHz. For the omial trasistor models, the voltage gai is about 8.9 db ad the badwidth is.5 GHz. Table 3.3 Postamplifier frequecy respose across differet process coditios. Resistor model Trasistor model Typical-mea Worst-speed Worst-power Badwidth [MHz] Voltage gai [db] Badwidth [MHz] Voltage gai [db] Badwidth [MHz] Voltage gai [db] Typical-mea 59 8.9 59. 8.9 59. 8.9 Worst-speed 7.5.8 7.5.8 7.5.8 Worst-power 347.7 6 347. 6 347. 6 Worst-zero 688. 5. 688. 5 688 5. Worst-oe 859.3.45 859.3.45 859.3.45 Electrical, Electroic ad Computer Egieerig 33

Chapter 3.5 x 7 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed Worst-speed Typical-mea Coversio gai [V/I].5.5 Worst-power 3 4 5 6 7 8 9 Frequecy [Hz] Figure 3.3 Frot-ed frequecy resposes for differet trasistor models with typical-mea resistor model. The characteristics of the frot-ed system ca be see i Figure 3.3 ad Table 3.4. Uder the worst-speed, worst-power ad the typical-mea trasistor ad resistor model simulatios, the characteristics of the frot-ed system are withi the specificatios. Table 3.4 Frot-ed frequecy respose across differet process coditios. Trasistor model Resistor model Typical-mea Worst-speed Worst-power Badwidth [MHz] Coversio gai [dbω] Badwidth [MHz] Coversio gai [dbω] Badwidth [MHz] Coversio gai [dbω] Typical-mea 769. 45.5 6.7 46.5 866.6 4.9 Worst-speed 66.3 45.9 569. 47.9 76. 4.9 Worst-power 876.5 45 558.6 35.5 39 43.8 3.5 LAYOUT The layout of the frot-ed circuit was completed ad is show i Figure 3.4. The commo-cetroid method was used wherever matchig betwee trasistors was required to cacel the effect of first-order process-related gradiets across the die alog both vertical ad horizotal axes. It was implemeted by decomposig the iput devices ito two halves which were cross-coected [5]. Wide devices were decomposed ito multifiger trasistors to reduce the gate resistace. For curret mirrors, uit trasistors were used Electrical, Electroic ad Computer Egieerig 34

Chapter 3 Uiversity of Pretoria etd Che, Y-J (5) Frot-Ed wherever possible to obtai better curret matchig ad o-miimum legths were implemeted to further suppress mismatches. 5 µm 566 µm Figure 3.4 Layout of the frot-ed. Electrical, Electroic ad Computer Egieerig 35

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER 4 CLOCK AND DATA RECOVERY CIRCUIT 4. INTRODUCTION The clock ad data recovery circuit forms the core of the receiver. It cosists of a phaselocked loop ad a frequecy-locked loop. I order to recover the origial data sequece ad reduce the itersymbol iterferece, it is ecessary to retime ad sychroise the iput sigal with a extracted clock sigal. I the CDR circuit, a clock sigal is geerated so that samplig of the iput data occurs at the optimum poit. The frequecy-locked loop performs the coarse adjustmet of the clock frequecy ad provides a large rage for frequecy acquisitio. The phase-locked loop provides a fie cotrol for the clock sigal. I this chapter, the implemetatios ad results of the CDR system are give. 4. CLOCK AND DATA RECOVERY PRINCIPLE Decisio circuit Recovered data Icomig NRZ data Phase detector VI coverter LPF VCO Frequecy detector Charge pump LPF Figure 4. Dual-loop clock ad data recovery circuit. The phase-lockig clock ad data recovery circuit with a frequecy acquisitio scheme is show i Figure 4.. Durig the CDR operatio, the locatio of the data trasitio is compared to the clock edge. If the data sigal leads the clock, the clock speeds up. The clock frequecy is decreased if the data sigal lags the clock. Whe the data zero crossigs coicide with the clock edge, the clock is kept costat, esurig phase lock. Phase drift ca cause a false data extractio. Stable operatio must therefore be maitaied for radom iput sigal icludig cosecutive iput data bits. 36

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit I the recovery circuit, a clock sigal is geerated by the voltage-cotrolled oscillator. The VCO s frequecy iformatio is compared to that of the icomig data. The differece i frequecies is utilised by the FLL to coarsely adjust the voltage-cotrolled oscillator frequecy util the differece is sufficietly small ad the FLL becomes iactive. The phase ad the frequecy of the VCO clock sigal are the compared to that of the data i the phase detector. A error sigal is geerated ad used to set the voltage required by the VCO to oscillate at the frequecy of iterest. Whe the data phase ad the clock phase differ by a small costat offset, the phase-locked loop remais locked. Oce the clock sigal is recovered, it is used to retime the data i the decisio circuit. 4.. Phase-Locked Loop 4... Voltage Cotrolled Oscillator [] The VCO desig [] impacts directly o the jitter performace ad reproducibility of the CDR. LC oscillators have potetially lower jitter. However, it is difficult to obtai a target frequecy due to their limited tuig rage ad the fact that they are ot practical i the MHz to GHz frequecy rage [9, 3]. Thus, a rig oscillator, due to its speed ad ease of itegratio, was implemeted to compesate for process ad temperature variatios. V i (jw) - H(jw) V out (jw) Figure 4. Negative feedback system. The oscillator ca be modelled liearly as illustrated i Figure 4. [3]. This ca be expressed as V V out i ( jw) ( jw) ( jw) ( jw) H =, (4.) H where H(jw) is the trasfer fuctio of the gai stages of the oscillator. At the frequecy ω o of iterest, the amplifier experieces sufficiet phase shift to cause the feedback to become positive ad for a oscillatio to occur. Thus, for the oscillatio to occur, the egative feedback system must satisfy the two Barkhause criteria simultaeously [5], which ca be defied as H ( jw) o H ( jw) = 8. (4.) Electrical, Electroic ad Computer Egieerig 37

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit The CDR circuit was icorporated with a frequecy-locked loop. The oscillator was desiged to geerate quadrature outputs as a provisio for the frequecy detector. A rig oscillator is formed by N delay stages. Each gai stage must cotribute a phase shift of 8 /N. For a differetial rig oscillator, a eve umber of stages must be implemeted to produce outputs with the quadrature phase. The phase iversio is achieved by ivertig two feedback coectios. The differetial implemetatio results i a area overhead ad power pealty. It is, however, ecessary to be traded off to achieve high-speed operatio with low sesitivity ad low jitter geeratio. I the oscillator, as the umber of delay stages icreases, it becomes difficult to achieve the required speed with a give CMOS techology ad it has a high power cosumptio. However, a sigle stage rig does ot produce sufficiet phases ad oscillatio caot occur. Thus, at least a two-stage topology is ecessary for quadrature outputs. I a two-stage rig oscillator, each stage must establish a phase shift of 9 withi its uity-gai badwidth. With covetioal differetial delay stages, the overall phase shift aroud the loop ca achieve 8 oly at ifiite frequecy []. The loop gai drops to zero at very high frequecies. The oscillator, thus, fails to oscillate. By itroducig a additioal phase i each stage, a greater phase shift ca be achieved aroud the loop. C M3 M4 R R C Vo Vo Vi M M Vi CL CL Ibias Mc Figure 4.3 Differetial delay cell. The sigle stage differetial delay cell is show i Figure 4.3 is the. Each load cosists of a resistor, a PMOS trasistor ad a capacitor. The parasitic capacitace determied by the drai juctio capacitace of the MOS devices, the iput capacitace of the ext stage ad the iput capacitaces of the isolatio buffers, results i the load capacitace of the differetial stage. Choosig proper parameters ad trasistor sizes, the composite load becomes iductive ad produces excess phase shift to allow oscillatio. Electrical, Electroic ad Computer Egieerig 38

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit The trasfer fuctio of each delay stage is derived as [] V V o i () s () s m3 The trasfer fuctio exhibits a zero at ad has two poles with a sum of gm ( src ) ( C CL RC ro 3 ) s RC CL =. (4.3) g s ω z =, (4.4) R C C C L ω p ω p =. (4.5) RC CL At every pole frequecy there is a -45 phase shift ad at every zero frequecy a 45 phase shift occurs. Thus, i order to provide a sufficiet phase shift of -9 withi the uity-gai badwidth, the sum of the two pole frequecies must be less tha the frequecy of zero. The, from Equatios 4.4 ad 4.5, it is required that [] C < C L 65 ff. (4.6) For a N-stage rig oscillator, the frequecy of oscillatio is iversely proportioal to the umber of stages N ad the delay per stage T d. The frequecy of oscillatio ca be defied as [] f osc =. (4.7) NT Cosider a oscillator to be a system that coverts the curret ad voltage to a phase that ca be directly related to the delay. Applyig a step curret to a oscillator, time delay ca be defied as the time it takes to respod from whe the oscillator output voltage is at its mid poit to whe it is at its maximum amplitude [36]. Thus, T d ca be expressed as [6] T d d V out, (4.8) SR where V out is the sigle-eded oscillator output peak voltage ad SR = I/C L is the slew-rate of the differetial pair with I beig the maximum curret that charges the load capacitor C L. Usig Equatios 4.7 ad 4.8, a oscillatio frequecy of approximately.5 GHz ca be achieved with a 8 ua tail curret ad a 5 mv peak-to-peak voltage. As show i Equatio 4.7, the frequecy of oscillatio ca be varied either by alterig the effective umber of stages or the delay of each stage. However, alterig the effective umber of stages may require a difficult logic, while the delay ca be easily adjusted through the tail curret. Electrical, Electroic ad Computer Egieerig 39

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit I order to avoid the uecessary logic, while compesatig for the process ad temperature variatios, the VCO icorporates delay iterpolatio, providig a wide tuig rage. To esure oscillatio ad high speed operatio, a gai of approximately.5 was implemeted i the desig. A relatively large bias curret was implemeted to keep the output voltage swig costat ad to miimise the output jitter of the oscillator. Delay Iterpolatio The coceptual illustratio of delay iterpolatio is depicted i Figure 4.4. Each oscillator stage cosists of a fast path ad a slow path with shared output odes. The voltage gais of the two paths are adjusted through the differetial delay cotrol voltage. By differetially varyig the delay cotrol voltage, the curret steered betwee the fast ad slow paths ca be adjusted ad hece the voltage gais of the two paths adjusted. Sice the large-sigal slew rate that is related to the curret drive ad capacitace results i the delay of each stage, therefore, adjustig the gais leads to delay variatios ad thus iflueces the oscillatio frequecy. Fast path V i V out Delay Delay cotrol Slow path Figure 4.4 Delay iterpolatio. The trasistor implemetatio of each delay stage is show i Figure 4.5. Each stage is realised with differetial amplifiers, as described i Figure 4.3, where outputs are summed i the curret domai. As show i the circuit, the slow path cosists of the differetial pairs M5-M6 ad M7-M8. The differetial pair M-M describes the fast path. The outputs of the two paths are summed i the curret domai. Electrical, Electroic ad Computer Egieerig 4

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit R M3 M4 R C C Vout Vi M M CL CL Ifast Mc_fast M9 M M5 M6 M7 M8 Vi Icost Mc_cost Islow Mc_slow Figure 4.5 Trasistor implemetatio of the delay iterpolatio. For the small sigal equivalet circuit, the summed curret is [5] I = g V g V. (4.9) out m, i m5, 6 i By varyig the tail currets I D of M-M ad M5-M6 i opposite directios, the trascoductace of the respective stage g m ' W = K I D, (4.) L ad thus the weighted sum of the delays of the slow path ad the fast path is altered. Assume that a impulse curret cosistig of Δq coulombs is applied to oe of the outputs of the two-stage rig oscillator. It causes a istataeous chage i the voltage ad results i a shift i the trasitio time [34]. This istataeous chage i the voltage ca be expressed as Δ V = Δq, (4.) where C O is the effective capacitace at that output. Timig jitter ca therefore be improved by itroducig a larger capacitace at the outputs of each VCO stage. This ca be doe by implemetig wide trasistors to suppress timig jitter ad to provide the adequate drivig capability that is required to drive a large umber of latches i the CDR circuit. Cosequetly, large currets ad miimum gate legth (.35 µm) implemetatio C O Electrical, Electroic ad Computer Egieerig 4

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit are ecessary to achieve high speed performace. Assume that the delay cotrol voltage of Figure 4.4 lies midway betwee the two extremes so that both the slow ad fast paths are o. A tail curret I D,Mc_cost = 5 µa was chose for the costat curret M7-M8 differetial stage. For the M-M ad M5-M6 differetial stages, the tail currets are set at I D,Mc_fast I D,Mc_slow = 56 µa, providig a two-to-oe tuig rage. The overdrive voltages (V GS V TH ) for the iput trasistors (M-M, M5-M6 ad M7-M8) are set low (at approximately.5 V) to esure the operatio of trasistors i saturatio. This traslates to trasistor widths of W, = µm, W 5,6 = 6 µm ad W 7,8 = 8 µm. A voltage gai of approximately.5 is set for the fast path. This requires a voltage gai of from the differetial stage M7-M8 to achieve a total gai of.5 per delay stage. As a result the load trasistor widths are set to W 3,4 = µm, ad W 9, = 6 µm. Stackig differetial pairs uder the delay stages makes it difficult i a low supply eviromet. I order to avoid voltage headroom cosumptio, curret foldig topology (as show i Figure 4.6) was implemeted to steer the currets of M-M ad M5-M6. Two PMOS differetial pairs were used to drive the curret mirrors. Iputs to the differetial pairs are cotrolled by a fie cotrol ad a coarse cotrol. The two cotrols set the curret flows ito their relative curret mirrors, which are fed ito the delay cells, thus adjustig the oscillatio frequecy. The fie tuig sesitivity of the oscillator is miimised by miimisig the trascoductaces of the fie cotrol iput trasistors of the curret foldig circuit. This is achieved by settig a small tail curret, I D,Mc_fie, with a small (W/L), ratio. Large trascoductaces for trasistors M5 ad M6 were implemeted to obtai a high sesitivity ad thus a wide coarse tuig rage. The dimesios of curret mirror trasistors are chose large with L = µm to provide a good curret matchig. Ifie Mc_fie Icoarse Mc_coarse Ifast M Vfie M M M5 M6 Vcoarse Islow M M9 M3 M4 M7 M8 M Figure 4.6 Coarse ad fie cotrols with the curret foldig topology. Electrical, Electroic ad Computer Egieerig 4

Chapter 4 Clock ad Data Recovery Circuit Electrical, Electroic ad Computer Egieerig 43 The fast path of the oscillator oly cosists of oe delay cell per stage, as show i Figure 4.4. Cosequetly, the maximum oscillatio frequecy of the implemeted VCO is determied by the delay cell i the fast path. Icorporatig the first criterio i Equatio 4. ad the trasfer fuctio i Equatio 4.3, the maximum oscillatio frequecy ca be derived as ( ) ( ) ( ) ( ) { ( ) ( ) [ ( ) ( ) ( ) ( ) ( ) ( ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )] 3 3 3 3 3 3 3 4 3 3 3 4 3 4 3 3 3 4 3 4 4 3 4 3 3 3 3 3 3 4 3 4 4 π = m m L o L o L o o m L m o o L o L o m o L o L o L o L o m o m o L o L L m o o m L o max g / g R C C r C C R C r C C r R C r g R C C C g... R r R C R C r C C r C C R C r g r C C R C... R C r C C r C C R C r C C R C r g R C r g... R C R C r C C r C C R C C g r R C r g R C C r f (4.) Whe the cotrol voltage is at oe extreme so that all the tail curret is steered to the fast path, the slow path is disabled. From Equatio 4., a maximum oscillatio frequecy of approximately. GHz (with R = 5 kω, C =.94 ff, g m = 3.76 ms ad g m3 =.535 ms) is yielded. Coversely, disablig the fast path ad eablig oly the slow path due to a extra delay cell i the slow path, the miimum oscillatio frequecy results. The weighted sum of the delays of the two delay cells i the slow path costitutes the total delay of each stage. Thus, the delay of the slow path per stage ca be expressed as [3] T d = (/g m9, ) C L,c (R /( R g m3,4 )) C L, (4.3) where C L,c.3 pf is the output capacitace of the differetial pair with the costat tail curret. Usig Equatio 4.3 ad 4.7, the miimum oscillatio frequecy is approximately equal to 834. MHz with g m9, =.878 ms ad g m3,4 =.6 ms, Phase Noise ad Jitter i the Rig Oscillator [3] I optical commuicatio systems, the clock sigal is geerated to drive the samplig circuits i which phase oise performace is critical. The oise requiremets are more striget as system speed icreases. I a sigle chip itegrated circuit substatial oise is produced by differet fuctioal circuits [33]. Nevertheless, the reductio of jitter due to VCO fluctuatios has bee show [33] to be the key desig factor for low-jitter CDR circuits. The VCO is assumed to be the domiat jitter source i the closed loop coditios. With the implemetatio of differetial circuit techiques, the power supply oise ca be miimised. Uiversity of Pretoria etd Che, Y-J (5)

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Cosider that the voltage amplitude chage caused by the curret impulse is small ad the phase shift is liearly proportioal to the ijected charge [34]. Furthermore, assume that the phase oise is much smaller tha the period of the oscillatio. The loop ca be cosidered to be liear ad oise cotributios ca be expressed by the trasfer fuctio [35]. The liearised model of rig oscillators i Figure 4. was employed to estimate the phase oise at the output of the oscillator [3]. I the aalysis, white, urelated oise sources are assumed ad the amplitude of the oise sigal is assumed to be much smaller tha the clock sigal. Assume that various oise compoets are ijected ito the sigal path. From Equatio 4., the oise power spectral desity at a frequecy Δω offset from the oscillatio frequecy ω ca be expressed as [ j( ω Δω) ] [ j( ω Δω) ] Vout. (4.4) Vi dh ( Δω) dω The trasfer fuctio of oe delay stage is described i Equatio 4.3. As metioed earlier, two delay stages are required for oscillatio with quadrature outputs. The the oscillator trasfer fuctio ca be writte as ad its derivative is dh jgm RC = dω ω RCC ω L j C C gm ( src ) ( C C R C r ) H ( jω) =, (4.5) gm3 s L o3 s RC CL ( jωg RC g ) m L m RC g ro 3 m3 ( jωg RC g ) m ω RCC m L ω RCC jω C C L L j C C L RC g ro 3 RC r o3. (4.6) 3 m3 The three types of phase oise that have bee idetified [3] are subsequetly discussed. Additive Noise The oise of each differetial pair ad the load trasistors is represeted by the additive oise ad is modelled as curret sources, I ad I, at the outputs of the delay stages. Relatig oise currets to the VCO stages, sice capacitors do ot cotribute oise [36], the effective output resistace of each stage ca be described by ( R /( g R )). Therefore, at a frequecy i the viciity of the oscillatio frequecy, ω = ω Δω, the total additive output phase oise power desity is expressed as m3 Electrical, Electroic ad Computer Egieerig 44

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit V [ j( Δω) ] [ j( ω Δω) ] [ j( ω Δω) ] R Vout I, ( gm3r ) Vi ω. (4.7) The oscillatio frequecy is usually also modulated by the flicker /f oise of the trasistors. However, whe the VCO is placed withi a PLL, the /f oise is rejected by the PLL loop filter [35]. Hece, the thermal oise per uit badwidth of MOS trasistors is expressed as [36] I 4kT g 3 = m, (4.8) where k is Boltzma s costat, ad at room temperature 4kT =.66 x - V-C. Thus, V [ j( ω Δω) ] ( g g ) 6kT 3 m m3 R ( g R ) m3 V V out i [ j( ω Δω) ] [ j( ω Δω) ]. (4.9) High-Frequecy Multiplicative Noise This oise is caused by the oliearity that exists i differetial stages. Whe a white oise with a amplitude of A at a frequecy of ω is ijected at the VCO iput i a differetial cofiguratio, V i (t) = A cos(ω t) A cos(ω t), the output sigal V out () t α A A ( ω )t (4.) 3 cos ω becomes a sigificat cross-product. Due to the oliear behaviour of the circuit, the lowfrequecy oise is up-coverted to the regio above ω ad high-frequecy oise is dowcoverted to the regio below ω. As a result, as idicated from simulatio results [3], the oise power spectrum estimated i Equatio 4.9 is effectively doubled. Low-Frequecy Multiplicative Noise I the implemeted VCO, the oscillatio frequecy is adjusted by varyig the tail curret. Thus, oise i the tail curret ca cause frequecy modulatios ad cotribute to the output jitter. The curret compoets I ( 4) I cos ( ω ± )t s = exist i the sigal path whe 3 ω the frequecy is corrupted by the tail curret oise, I = I cos(ω t), produced by the tail curret source trasistors. The the output phase oise power desity is expressed as V [ j( Δω) ] [ j( ω Δω) ] [ j( ω Δω) ] 3 R V out I 4 ( gm3r ) Vi ω. (4.) Electrical, Electroic ad Computer Egieerig 45

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Estimatio ad Simulatio Usig Equatios 4.9 ad 4., V tot [j(ω Δω)] = V [j(ω Δω)] V [j(ω Δω)], the total output phase oise power of.476 x -7 V /Hz was estimated at the output of the oscillator. Simulatios were doe o the VCO circuit. Figure 4.7 depicts the frequecy characteristic of the voltage-cotrolled oscillator versus both coarse ad fie cotrol voltage. It ca be see that the fie ad coarse cotrol sesitivities of the VCO for the typical-mea trasistor models are K Fie = 37.5 MHz/V ad K Coarse = 537.875 MHz/V respectively. As show, the lock rage is approximately equal to 3 MHz. Oscillatio frequecy [GHz] aaa.5.4.3...9.8.7.6.5 Kcoarse Kfie - -.8 -.6 -.4 -...4.6.8 Cotrol voltage [V] Figure 4.7 VCO characteristic. Figure 4.8 depicts the VCO coarse cotrol sesitivity across the four corers ad the typical-mea simulatio models. It idicates that the VCO is typically sesitive to the worst-speed ad worst-power trasistor models. However, the qualities of resistors ad capacitors do ot have ay obvious effect o the VCO sesitivity. I the simulatio, the tail curret was varied differetially, where the sum of the two tail curret remais as 8 μa. As show i the figures, i the worst-power trasistor simulatio, the tuig rage is about 5 MHz i the egative directio aroud the ceter frequecy, ad about 4 MHz i the positive directio i the worst-speed trasistor simulatio. If less curret is partitioed to the slow path, a greater rage ca be obtaied i the worst-power trasistor simulatio. Ufortuately, i a o-ideal eviromet, the frequecy rage aroud the ceter frequecy is udesirably decreased, although it is still operatioal at Gb/s. Electrical, Electroic ad Computer Egieerig 46

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Frequecy [GHz] aaaaa.5.3..9.7.5.3..9.7 WS WP TM WO WZ Frequecy [GHz] aaaa Frequecy [GHz] aaaaa.5.3..9.7.5.3..9.7.5.3.5.3..9.7.5.3..9.7.5 3 4 5 6 7 8 Cotrol curret [ua] (a) WS WP TM WO WZ 3 4 5 6 7 8 Cotrol curret [ua] (b) WS WP TM WO WZ 3 4 5 6 7 8 Cotrol curret [ua] (c) Figure 4.8 Free ruig characteristics of VCO at differet trasistor process coditios with (a) typical-mea resistor ad typical-mea capacitor models; (b) worst-speed resistor ad worst-speed capacitor models; ad (c) worst-power resistor ad worst-power capacitor models. Electrical, Electroic ad Computer Egieerig 47

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit The frequecy rage ca be icreased by icreasig the sesitivity of coarse cotrollig trasistors i the curret foldig circuit. However, i a certai tuig rage there is a ievitable icrease i the VCO gai. The oscillator becomes more susceptible to the curret icrease ad udesirably ad tremedously decreases the frequecy of oscillatio. The free ruig output spectrum of the oscillator is illustrated i Figure 4.9. It was obtaied by processig the simulated time domai output waveform i Matlab. The additive oise, high-frequecy multiplicative oise ad tail oise curret were modelled by siusoidal voltage ad curret sources superimposed at the output braches ad to the tail curret sources of the oscillator. As ca be see, the phase oise i the VCO is approximately equal to -9.8 dbc/hz at a MHz offset relative to the carrier frequecy. - Output voltage [dbv] - -3-4 -5-6 -7-8.94.96.98..4.6 Frequecy [Hz] x 9 Figure 4.9 Free-ruig spectrum of the oscillator. 4... Liear Phase Detector The phase detector is the key compoet for geeratig the phase error betwee the VCO clock sigal ad the data sequece. Whe the differece betwee the clock frequecy ad the data rate is small eough for the VCO clock sigal to fall withi the capture rage of the phase detector, the frequecy detector is disabled ad the phase detector takes over. Oce the phase lock is achieved, the cotrol voltage to the VCO should stay costat ad should ot be corrupted by the phase detector output. Thus, a low jitter phase detector is required. Electrical, Electroic ad Computer Egieerig 48

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit I digital mode operatios, the biary ature of the phase detector creates sigificat jitter o the cotrol lie i the locked loop ad at the CDR output [37]. I order to miimise jitter geeratio, the aalogue phase detector was implemeted to provide a liear behaviour. The phase detector cosists of two sample-ad-hold circuits as described i [] ad a multiplexer. VCO clock Data C P Multiplexer V PD Data C P Figure 4. Liear phase detector. Figure 4. illustrates the geeral topology of the sample-ad-hold phase detector. The geeral operatio of the phase detector is described i Figure 4.. At each risig data trasitio, oe sample-ad-hold circuit tracks the data ad the other holds the istataeous sampled voltage level. At every fallig data trasitio, the uit that was i the trackig mode switches to the hold mode ad stores the voltage level, while i the other it switches to the trackig mode. At every data trasitio, the multiplexer oly selects the sample-adhold uit that is i the hold mode, thus avoidig a trasparet path from the iput to the output ad geeratig a output that is liearly proportioal to the phase differece withi the lockig rage. Holdig time Holdig time Samplig time Samplig time Figure 4. Samplig example. Figure 4. depicts the circuit implemetatio of the phase detector. The tail currets of the sample-ad-hold circuits ad of the multiplexer are cotrolled by a curret foldig circuit allowig a low-supply voltage operatio. I the curret foldig circuit, trasistors Electrical, Electroic ad Computer Egieerig 49

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit M-M4 act as switches. They are desiged with large widths ad short chaels to provide high speed ad high drivig capability. The sample-ad-hold circuits were implemeted with differetial pairs ad source followers. I the hold mode, the tail curret ad the load devices tur off simultaeously ad the istataeous voltage of the VCO is stored i the parasitic trasistor capacitors of source followers that are coected at the outputs of the differetial pairs. Whe trasistor M is o, trasistors M8 ad M9 operate i the triode regio. The same applies to trasistors M ad M9-M. Takig the rise ad fall time ad the drivig capability ito accout, a gate-source voltage of approximately V was chose for trasistors M ad M. At the drai curret I D, = I D, = ma, this sets the dimesios of M ad M to (W/L) = (W/L) 8 µm/.35 µm. I order to process the VCO sigal at high speed, a small voltage gai of approximately.5 was chose for the differetial pairs of the sample-ad-hold circuit. Settig the trascoductaces at (g m ) 6,7 = (g m ) 7,8.5 ms, it requires a load resistace of. kω that is give by ( V V ) ' W R o = K P SG TH, P, (4.) L where K P ad V TH,P are the gai factor ad threshold voltage of the PMOS trasistor respectively. The dimesios of the load trasistors are thus set at (W/L) 8,9 = (W/L) 9, 3 µm/.35 µm. Ibias M5 M M8 M9 M3 M5 Vout M3 M33 M6 M4 M9 M M Data M3 M4 M6 M7 M8 M9 M3 M3 M7 M8 M M M M Ibias M4 M6 M34 M35 M7 M5 Ibias M M3 clock switches sample-ad-hold circuit multiplexer sample-ad-hold circuit Figure 4. Sample-ad-hold phase detector. 4...3 Voltage-to-Curret (V-I) Coverter ad Loop Filter The V-I coverter (as show i Figure 4.3) is ecessary for liearly covertig the PD output voltage to a curret that charges the loop filter that atteuates high frequecy compoets of the loop ad provides a fie cotrol voltage to the oscillator. As depicted i Electrical, Electroic ad Computer Egieerig 5

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit the figure, the phase detector output voltage is fed ito the iputs of the PMOS differetial pair ad thus defies the curret flows ito the NMOS curret mirrors that charge the loop filters. The output of the V-I coverter is folded up to produce a output commo-mode (CM) level that is compatible with the VCO cotrol voltage. The matchig ad chaellegth modulatio of the trasistors i the V-I coverter stage impact o the static phase error betwee the data ad the VCO output i locked coditio. To miimise static error, a V-I coverter with high output impedace ad trasistors with relatively large legths ad widths are required. The phase detector gai has a direct impact o the loop badwidth [33]. Settig a large K PD will result i a large loop badwidth that ca provide a good jitter reductio but is uable to provide a good suppressio of the exteral iput oise. However, settig a small loop badwidth by implemetig a small K PD, the exteral iput jitter ca be sigificatly reduced but much of the VCO oise remais ureduced [35]. Compromisig the two factors ad the requiremet of high output impedace, the V-I coverter gai was chose to be : the differetial pair M3-M4 had a gai of.5 ad the commo-source amplifiers (M8 ad M9 stages) had a gai of approximately 8.5. For trasistor matchig, the trasistor legths of curret mirrors (M, M, M8 ad M9) were chose as µm to reduce the effect of chael legth modulatio. The speed of the V-I coverter is ot striget. The circuit oly has to ru at a frequecy equal to the differece betwee the data rate ad the VCO frequecy. A small bias curret of 5 µa was chose for the differetial pair. Set g m3,4 to 7 µs, the dimesios of trasistors M-M4 with (W/L) 3,4 =.5 µm/.5 µm ad (W/L), = 4 µm/ µm are required. To achieve high output impedaces, the bias currets of the commo-source stages are halved. This sets the R o,6-7 of M6-M7 PMOS trasistors to 63 kω, which traslates to a (W/L) 6,7 ratio of.. Ibias M5 M6 M7 Vpd M3 M4 Vp V M M M8 M9 Figure 4.3 V-I coverter. Electrical, Electroic ad Computer Egieerig 5

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit A commo-mode feedback circuit was icluded to provide correctio to the output CM level. The CM level is adjusted by couteractig the commo-mode variatios o the differetial lies (Vp ad V) of the loop filter, at which the DC output level is set at a value of approximately of V DD /, prevetig trasiets from creatig steady-state compoets o parasitic lie capacitors. Figure 4.4 illustrates the commo-mode feedback (CMFB) circuit topology. Trasistors M4-M7 sese the commo-mode voltage of Vp ad V. Whe the CM voltage is higher tha V DD /, the gate-source voltages V GS,6 ad V GS,7 icrease ad cause NMOS trasistors M8 ad M to sik more curret, thus dischargig the two lies similarly ad decreasig the commo mode DC level. If the CM voltage is lower tha V DD /, V GS,4 ad V GS,5 decrease, trasistor M respods accordigly ad the curret is mirrored to M ad M3. It causes M ad M3 to source more curret, therefore pullig up the commo-mode voltage level of the loop filter outputs. At Vp = V = V DD /, the suke ad sourced currets of the NMOS (M8-M) ad PMOS (M-M3) etworks, respectively, are set at a small value of µa to limit the static power dissipatio. The dimesios of uit trasistors were implemeted with (W/L) -5 = 7.4 µm/ µm ad (W/L) 6- =.5 µm/ µm, for PMOS ad NMOS trasistors respectively, esurig small overdrive voltages, thus the operatio of trasistors i saturatio. No-miimum legths were implemeted to reduce the effect of process variatios. M M M3 Vp M4 M5 V M6 M7 M8 M9 M Figure 4.4 Commo-mode feedback circuit. The iput/output characteristic of the phase detector is show i Figure 4.5. The phase detector gai is equal to K PD =.534 V/rad i its liear rage. Due to the systematic error Electrical, Electroic ad Computer Egieerig 5

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit ad differet propagatio delays betwee the data ad the clock sigal, as show i the figure, a small phase error persists..5 Output voltage [V]aaa.5 -.5 - -.5 - -8-6 -4-4 6 8 Phase differece [degree] Figure 4.5 Iput/output characteristic of the phase detector with the V/I coverter. Loop Filter [33] Jitter characteristics of the phase-locked loop are strogly depedet o the dampig factor ζ ad the atural agular frequecy ω [3]. Thus, the loop parameters of the PLL must be optimised to achieve good jitter characteristics. The implemetatio of the PLL low-pass filter, as show i Figure 4.6, was based o the desig method of optimisig the PLL parameters described i [33]. A small loop badwidth ad high dampig factor are commoly implemeted to reduce the iput oise. R VCC_CIRCLE VCC_CIRCLE C R Figure 4.6 Lead-lag loop filter. Based o the phase-trasfer fuctio, the jitter trasfer fuctio of the CDR with a simple lead-lag filter ca be expressed as H ( jω) ω ω ω j ζω = K, (4.3) ω ω jζω ω Electrical, Electroic ad Computer Egieerig 53

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit where K is the ope loop gai of the PLL. By settig ζω = Z W, H(jω) is approximated by ( jω) ( ZW ζ) ( Z ζ) 4 4ZW ω H =. (4.4) ( ω ) 4Z ω W To alleviate jitter accumulatio o the fibre lik, it is recommeded that the jitter peakig should be below. db. Thus, at ω = ω, the jitter trasfer curve ca be expressed as H ( jω). db. (4.5) 4ζ The the dampig factor is set by Equatio 4.3 as ζ 4. (4.6) By examiig Equatio 4.4, it ca be proved that the jitter trasfer curve becomes idepedet of the dampig factor whe ζ is larger tha or equal to 4. As will be show later, the value of ζ directly impacts o the choices of the size of the loop filter s compoets. With the miimum value of ζ = 4, the jitter trasfer fuctio for differet values of Z W is show i Figure 4.7. As illustrated, i order to meet the jitter specificatio, Z W MHz has to be implemeted. W 5 Gigabit fiber chael jitter specificatio Jitter Gai [db] -5 - -5 - Zw = MHz Zw = MHz Zw = 4 MHz Zw = 3 MHz -5-3 4 5 6 7 8 Frequecy [Hz] Figure 4.7 Jitter trasfer fuctio. Electrical, Electroic ad Computer Egieerig 54

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit It has bee show [33] that the output jitter of the CDR circuit is maily caused by the additive oise at the iput ad the oise geerated i the circuit. Assumig the additive white Gaussia oise, jitter geeratio (i phase deviatio) is approximated by N ηπ σ out ZW [rad], (4.7) A O m ξπ ZW ZW where N O is the white oise power spectral desity at the iput, A m is the iput sigal amplitude, η is the power spectral desity of Gaussia white oise frequecy modulatio ad ξ is the power spectral desity of Gaussia flicker oise frequecy modulatio. As show i Equatio 4.7, by maximisig Z W, a low output jitter CDR circuit ca be obtaied. Choosig the upper limit of Z W = MHz ad with ζ = 4 set, the loop filter time costat τ is give as τ ζ = CR = 6 μs. (4.8) = Z W The pull-i rage (capture rage) is related to the time costats, τ ad τ, of the loop filter ad is defied as τ Ω P = Z W. (4.9) τ For a give system, it is desirable to have a large pull-i rage that ca be obtaied by maximisig the ratio τ /τ. However, it is limited by the ope loop gai ad the limited phase compariso rage τ K cr = Z W. (4.3) τ The ope loop gai of the PLL is defied as K = K PD K Fie, (4.3) where the phase detector gai is K PD =.534 V/rad ad the VCO fie cotrol gai is K Fie = 37.5 MHz/V. As show i Figure 4.5, the trasfer characteristic of the phase comparator has a limited rage. I order to obtai phase lock, the phase differece betwee the VCO frequecy ad the data sigal must be less tha ±4 degree. Thus, the gai related to the capture rage is defied as K cr = K(π/9). (4.3) Equatig formulae 4.3 ad 4.3, the ratio of the two time costats is τ /τ 9. (4.33) The, Electrical, Electroic ad Computer Egieerig 55

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Choosig C = 5 pf, the R = 6 kω ad R = 854 kω..4 τ = C(R R ) 44 μs. (4.34) Differetial Cotrol Voltage [V]...8.6.4. -. Time [s] 3 4 5 x -7 Figure 4.8 PLL differetial cotrol voltage output durig phase acquisitio. A - pseudoradom bit sequece (PRBS) was geerated by a gold-sequece geerator i Simulik i Matlab. Figure 4.8 depicts the behaviour of the overall phase-locked loop circuit at the trasistor level i respose to the Gb/s - PRBS data. Durig the acquisitio period, the phase betwee the VCO sigal ad the iput data is compared ad adjusted through the feedback loop. A trasitio of approximately 4 s is required before phase lock. Jitter [38] Ideally, the spacig betwee clock trasitios should be costat. However, the oise sources ivolved cause the trasitio spacig to be variable ad ucertai. This ucertaity results i a difficulty for the estimatio of the statistics of jitter. Noetheless, jitter ca be idirectly determied from its relatioship with the associated phase oise, as its correspodig free-ruig phase oise ca be more easily approximated. Assume that the phase oise is a result of oly white oise sources. The the closed-loop jitter of a phaselocked oscillator ca be approximated by Δω ΔTPLL = Sφ( Δω) [s], (4.35) πf ω u where S φ (Δω) is the relative phase oise power at a offset frequecy of Δω ad f u is the -3 db frequecy of the PLL. Electrical, Electroic ad Computer Egieerig 56

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit The -3-dB frequecy of a secod-order PLL with a zero ca be described as [36] ω f = u K PDK Fie, (4.36) ω where ω ad ω deote the pole ad the zero of the loop filter respectively. With the desig parameters, the closed-loop uity-gai badwidth was computed to be approximately equal to MHz ad the closed-loop jitter performace at GHz is equal to.3 ps rms. 4.. Frequecy-Locked Loop Systems i the fibre optical commuicatio etwork have to esure a exact data rate operatio required. However, process ad temperature variatios result i a large deviatio betwee the VCO frequecy ad the iput data rate, which may cause a false clock sigal extractio. I order to guaratee the VCO oscillatio at the data rate with a tolerable discrepacy, the oscillator was desiged with a wide frequecy tuig rage. Due to the small capture rage of the phase detector, the PLL CDR circuit caot acquire lock whe the data rate ad the VCO s startig oscillatio frequecy differ greatly. This problem was relaxed by the implemetatio of a frequecy-locked loop. The frequecy detector compares the VCO oscillatio frequecy ad the data rate, ad adjusts the VCO frequecy to a value where the differece betwee the two frequecies is small eough for acquirig phase lock. The frequecy detector the becomes iactive ad the phase detector takes over to alig the phase. 4... Frequecy Detector [4] Figure 4.9 Schematic of the frequecy detector. I the project, the frequecy detector was realised with a digital quadricorrelator [7, 4], the operatio of which is based o the bag-bag cocept. The i-phase ad the quadrature clock sigals are sampled at the risig ad fallig edges of the NRZ data sigal, geeratig Electrical, Electroic ad Computer Egieerig 57

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit the correspodig i-phase ad quadrature basebad compoets, V I ad V Q (as show i Figure 4.9). Durig the operatio, whe there is a frequecy differece, a beat frequecy proportioal to this differece is geerated at the output of the detector. The directio of the differece is determied by the relative zero crossigs of the V I ad V Q sigals. The operatio of the circuit ca be iterpreted as follows. If V Q leads V I, the VCO frequecy is too slow, ad the VCO frequecy is too fast whe V Q lags V I. The compariso of the two sigals is doe through a sychroous trasitio detector which guaratees that the gai of the frequecy detector is ot affected by the iput data rate. After the trasitio detector, combiatioal cells were implemeted to realise the logic operatio. At the output of the detector, a UP pulse is geerated whe the VCO frequecy is slow ad a DOWN pulse is geerated whe the VCO frequecy is fast. If there is o frequecy discrepacy, o output pulses are geerated by the frequecy detector. Thus, it does ot affect the operatio of the phase detector. Table 4. describes the operatio scheme of the detector ad was realised by the logic cells as show i Figure 4.. Table 4. Truth table of the frequecy detector (adapted from [4]). A C B D VCO frequecy RESET UP UP UP RESET DOWN DOWN DOWN RESET RESET A' C UP B' D' A C' DOWN Figure 4. Circuit implemetatio of the combiatioal logic. Electrical, Electroic ad Computer Egieerig 58

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit As show i Figure 4.9, the data sigal is used to clock the VCO sigal, which oscillates at full-rate, at the two iputs of the frequecy detector. For a faster lockig, the two iput detectors were implemeted usig double-edge-triggered flip-flops (DETFFs) to icrease the correctio rate of the CDR circuit ad reduce the output jitter. The subsequet detectors were implemeted with sigle-edge-triggered logic, sice the full-rate VCO sigal is applied to the triggers. Double-edge-triggered flip-flops, described i [4], were implemeted for the two flip-flops at the iput of the frequecy detector. The desig is show i Figure 4.. Due to the large umber of subcircuits ivolved, it is expected to have a relatively high oise eviromet withi the itegrated circuit. Thus, as show i the figure, trasmissio gates are used as pass trasistors to alleviate the effect of charge ijectio. clocki clocki D gd vdd M M clocki vdd gd M5 M6 clocki clocki vdd gd M3 M4 clocki clocki clocki Q gd vdd M7 M8 clocki vdd gd M M clocki vdd gd M9 M clocki clocki Figure 4. Double-edge-triggered flip-flop. M M4 M7 M M clocki D M M5 M8 Q Q M3 M6 M9 M M3 Figure 4. Positive edge-triggered TSPC flip flop. Electrical, Electroic ad Computer Egieerig 59

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit I order to achieve a high clock frequecy, true-sigle-phase-clock (TSPC) flip-flops [4], as show i Figure 4., were implemeted i place of the sigle-edge-triggered logic. The flip-flop show i Figure 4. could have bee modified to perform a sigle-edgetriggered operatio. However, with this implemetatio, oe of the outputs at the frequecy detector is iitialised to high ad results i almost rail-to-rail voltages at the charge pump s outputs. These high differetial sigals cause oliearities i the FLL ad large trasiets are ecessary before frequecy lockig. To avoid the problem of iitial voltages at the FD outputs, the TSPC flip-flops were utilised. By makig the TSPC logic trasistors strog, the flip-flop operatig frequecy was maximised. Ufortuately, the TSPC logic requires several clocked trasistors ad results i a relatively high power cosumptio. Figure 4.3 depicts the characteristics of the digital frequecy detector. Simulatios idicate that the detector is relatively isesitive to differet process coditios. The percetage duty cycle at the output of the detector was represeted by the pulse desity. I the figure, the positive pulse desity correspods to a UP sigal ad the egative pulse desity correspods to a DOWN sigal. As show, the frequecy detector ca correct the oscillatio frequecy error to approximately ±3% of the data rate. Pulse desity [%] 4 3 - - -3-4 TM WS WP WO WZ -4-3 - - 3 4 Frequecy error [%] Figure 4.3 Frequecy detector trasfer fuctio across differet process corers. Figure 4.4 illustrates the frequecy detector s resposes to a fast clock ad to a slow clock. I respose to a faster clock sigal, the sigal V I leads V Q ad the DOWN pulses are produced at the output of the FD, as show i Figure 4.4(a), to adjust the faster VCO frequecy. I Figure 4.4(b), sigal V Q leads V I ad the FD outputs UP pulses to correct Electrical, Electroic ad Computer Egieerig 6

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit the slower VCO frequecy. I respose to a bit rate VCO clock sigal, both the UP ad DOWN outputs are quiet, as show i Figure 4.4(c), providig o correctio to the VCO frequecy. (a) (b) Figure 4.4 Frequecy detector timig diagrams with (a) a slow clock sigal; (b) a (c) fast clock sigal; ad (c) a bit rate clock sigal. Electrical, Electroic ad Computer Egieerig 6

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit 4... Charge Pump ad Loop Filter Traditioal charge pump circuits (Figure 4.5) have bee realised by directly replacig the ideal switches with MOS trasistors. Due to the oideality of the PMOS ad NMOS switches, charge ijectio occurs ad a mismatch betwee the currets from the PMOS ad NMOS trasistors is geerated []. I A B PFD UP DOWN S S I C P V out Figure 4.5 Traditioal charge pump (adapted from [5]). The charge pump implemeted i this project was based o the circuit proposed i []. It employs a switched curret source with a positive ad a egative curret pump (as show i Figure 4.6) to drive a floatig loop filter. I the circuit, switchig is doe by meas of a 3-state frequecy detector where the UP ad DOWN logic sigals are coverted by the charge pump ito a VCO low frequecy cotrol sigal. Figure 4.6 Differetial charge pump (adapted from []). As illustrated i the figure, the circuit uses differetial, curret steerig techiques to allow fast switchig ad alleviates charge-sharig problems. The differetial topology also provides a high commo-mode oise rejectio ad thus further reduces phase oise ad spurs i the VCO. Two idetical output paths are provided to charge ad discharge loop filters i order to solve the problem of the curret discrepacy geerated i traditioal Electrical, Electroic ad Computer Egieerig 6

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit charge pump circuits. The operatio of the charge pump ca be explaied as follows. Iput trasistors M ad M act as curret switches. Durig frequecy lockig, whe the UP iput sigal is asserted ad the DOWN sigal is low, trasistor M is o ad all the tail curret is steered to M providig a costat bias curret to M4, which is the mirrored to trasistors M8-M9, with a mirrorig ratio of 5. The NMOS curret mirrors the force I D, A ad I D, 5 µa ad thus direct the flow of the output curret i the positive directio through the floatig loop filter. Whe DOWN is high ad UP is uasserted, the tail curret is steered to M ad mirrored to M6-M7 forcig I D, 5 µa ad I D, µa. Therefore, the curret is pumped oto the loop filter i the egative directio. If both UP ad DOWN iputs are asserted, the NMOS curret mirror pairs esure that the sourced ad suke currets are idetical, creatig zero static phase offset. For full tail curret steerig, it requires the iput trasistors i saturatio. This ca be doe by settig the overdrive (V ov,- = V GS,- V TH, ) voltage small. However, with a rail-to-rail switchig sigal, this desig costrait is relaxed. The overdrive voltages for M-M were chose to be approximately.5 V, with a bias curret of 5 µa. This sets the (W/L), ratio to.5. To esure operatio i saturatio, the gate-source voltage of the curret mirror load (M3-M4) must satisfy the coditio: V V V V, (4.37) SG, 3 4 DD DS_sat, DS_sat,5 where V DS_sat represets the drai-source voltage for which the trasistor operates i the saturatio regio. With V DS_sat,- (V GS,- V TH, ).5 V ad V DS_sat,5 (V GS,5 V TH, ).3 V, it requires V SG,3-4.5 V. For V SG,3-4 =.V, the (W/L) 3,4 ratio is.5. With mirrorig ad perfect matchig, V ov,3 = V ov,4 = V ov,6 = V ov,7 = V ov,8 = V ov,9 =.55V. This sets the margi for the gate-source voltage of trasistors M ad M3 to (V GS,, V GS,3 ).75V. Sice the currets are mirrored to M ad M ad the output commo-mode voltage is set midway betwee the supplies, V ov, ad V ov, have to be less tha V DD / to esure the trasistors to operate i the saturatio regio. The overdrive voltage was therefore chose as V ov, = V ov, = V ov, = V ov,3 V to meet the above-metioed coditios. This results i a small (W/L) -3 ratio of.5, which ca coserve layout area. I the desig, log chael legth trasistors were used to miimise the mismatch betwee output currets. The loop filter was implemeted to elimiate the udesired high-frequecy oise sigals ad to provide a stable cotrol voltage to the VCO. The filter cosists of a series RC Electrical, Electroic ad Computer Egieerig 63

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit etwork i parallel with a secod capacitor (as show i Figure 4.6), resultig i a type II third-order frequecy-locked loop. Rp Cp Cs Figure 4.6 Floatig loop filter used i the FLL. A shut capacitor is icluded to suppress the discrete voltage step at the VCO cotrol voltage due to the istataeous chages i the output curret of the charge pump [5]. Whe C P >> C S, secod-order approximatios ca be made []. As capacitors are the most area-cosumig elemet, the floatig loop filter was implemeted to miimise the layout area. From Figure 4.6, the impedace of the passive filter ca be derived as Z () s s = CSCPR s s CS CP ( C R ) P P P ( C C ) S P. (4.38) Defie the time costats which determie the pole ad zero of the trasfer fuctio as τ τ P Z = R = R P P CSCP C C the the resultig ope loop gai of the FLL ca be expressed by C S P P, (4.39) I PKCoarse sτz G () s H () s =, (4.4) π s ( C C )( sτ ) where I P is the charge pump curret i phase cotrol mode ad K coarse 537.9 MHz/V is the VCO coarse cotrol sesitivity. S P P From Equatio 4.4, the cross-over frequecy ca be approximated by ω C I P K π coarse R P. (4.4) I [43], it is stated that the maximum capture rage ca be approximated by the ope-loop badwidth which is a fuctio of loop filters. Usig Equatio 4.9, a capture rage of 7.89 MHz is estimated. For a charge pump curret of 5 μa ad K coarse = 537.9 MHz/V, a resistor value of.67 kω ca be derived usig Equatio 4.4. Electrical, Electroic ad Computer Egieerig 64

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Let the zero frequecy be approximately a factor of 5 below the cross-over frequecy, the C P = RP 6.6 pf. (4.4) τz From the ope loop gai trasfer fuctio, the phase margi ca be defied as φ ω ω 8. (4.43) ( ω) = ta ta ωz ωp To esure loop stability, a maximum phase margi is desirable. The frequecy at which the maximum phase margi occurs ca be foud by settig the derivative of Equatio 4.43 equal to zero, dφ τ = dω τ Z P = Z P ( ωτ ) ( ωτ ) Solvig the equatio, the maximum phase margi is at C Z P. (4.44) ω = ω ω. (4.45) Therefore the pole frequecy is at ω P = 5ω C ad the value of the shut capacitor is C S = ωprp.pf. (4.46) CP From the above desig parameters, as show i Figure 4.7, a phase margi ad a cutoff frequecy of approximately 67.4 degree ad 7. MHz ca be achieved respectively. Magitude [db] 5-5 - -9 Phase [deg] - -5 Phase margi: 67.4 deg -8 5 6 7 8 9 Frequecy [Hz] Figure 4.7 FLL ope loop gai bode plot. Electrical, Electroic ad Computer Egieerig 65

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit As ca be see, the resultig C S is much smaller tha C P. Secod-order approximatio ca be made ad the delay time costat ca the be approximated by [5] = ζω R C P 4π I K p coarse.9 s. (4.47) The commo-mode feedback was implemeted to defie a loop-filter output CM level that is compatible with the VCO cotrol voltage for stable frequecy acquisitio. The implemetatio of the CMFB circuit is show i Figure 4.4. Simulatio I simulatio, load capacitace of ff was used i place of the iput capacitaces of the coarse cotrol iput trasistors of the VCO circuit. (a) (b) Figure 4.8 (a) Chargig ad (b) dischargig actio of the charge pump circuit. Electrical, Electroic ad Computer Egieerig 66

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Figure 4.8 illustrates the fuctioig of the charge pump. Whe the UP sigal is high ad the DOWN sigal is low, as show i Figure 4.8(a), the charge is deposited oto the loop filter raisig the differetial output voltage. Whe the DOWN sigal is activated ad the UP sigal is low, as show i Figure 4.8(b), the NMOS curret mirrors sik the curret dischargig the loop filter ad decreasig the output voltage. It ca be see from both figures that whe both of the iput sigals are low, the output voltage remais almost costat util the ext iput pulse is activated. 4.3 LAYOUTS 6 µm 9 µm 65 µm (a) 34 µm (b) Figure 4.9 Layout: (a) PLL circuit without the loop filters; (b) Frequecy detector ad charge pump. Electrical, Electroic ad Computer Egieerig 67

Chapter 4 Uiversity of Pretoria etd Che, Y-J Clock (5) ad Data Recovery Circuit Figures 4.9(a) ad 4.9(b) depict the layouts of the PLL ad frequecy detector circuits respectively. The commo cetroid method was applied to all differetial circuits ad the same orietatio was used for all trasistors i order to alleviate the effect of ay diffusio gradiets that might be preset ad to miimise the offset voltage of differetial pairs. I additio, a substrate cotact was placed betwee the sesitive small sigal circuits ad the large sigal circuits to seal the oise geerated i the circuits [33] ad to create low resistace i the substrate. Uit trasistors were used wheever curret matchig is ecessary. The Metal 4 layer was used as far as possible for the routig as it has the least capacitace ad resistaces of all routig metals. Electrical, Electroic ad Computer Egieerig 68

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER 5 OPTICAL RECEIVER 5. INTRODUCTION All circuits required for a optical receiver have bee discussed separately thus far. The detector seses the photo iput ad trasforms it ito a electric curret. The trasimpedace amplifier, preamplifier ad postamplifier that followed covert the curret ito a voltage ad amplify it to a large eough swig for the clock ad data recovery circuit. The CDR circuit, the core of the receiver, recovers the clock sigal ad uses this clock sigal to retime the icomig data, thus improvig the sigal-to-oise ratio of the receiver. I this chapter, the performace of the complete system is discussed. 5. OPTICAL RECEIVER SYSTEM Table 5. summarises the performace of the system. Table 5. Performace summary of the optical receiver. Bit rate Gb/s Frot-ed Wavelegth 77 m ~ 86 m Photodetector resposivity at a wavelegth = 86 m.38 A/W Detector capacitace 56 ff Detector speed 8.5 GHz Trasimpedace gai 69.7 dbω Equivalet iput referred oise curret 8 A Sesitivity at a BER of - -9.7 dbm Overall frot-ed gai 45.5 dbω Overall frot-ed badwidth 769. MHz Clock ad data recovery circuit Capture rage 7.89 MHz Lock rage 3 MHz Tuig rage 6 MHz Phase oise at MHz offset -9.8 dbc/hz RMS jitter for - PRBS data.3 ps Total power dissipatio 55 mw Chip core area.853.35 mm Techology AMS.35 μm CMOS 69

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver The capture rage is depedet o the type of the PLL loop filter used ad is difficult to predict aalytically [36]. For the lead-lag loop filter, however, the capture rage ca be estimated usig Equatio 4.9. Substitutig desig parameters ito the equatio, a capture rage of approximately 7.89 MHz was estimated. The lock rage is idepedet of the properties of the loop filter [36] ad is determied by the VCO fie tuig rage. The fie tuig rage of the VCO i Figure 4.7 idicates that the PLL system has a lock rage of approximately 3 MHz..6.4 Voltage [V]. -. -.4 -.6 4 6 8 Time [s] x - 3.5 (a) 3.5 Voltage [V].5.5..4.6 Time [s].8 x -9 (b) Figure 5. Eye diagram of (a) the frot-ed differetial output; ad (b) the retimed data output i respose to Gb/s - PRBS data. Assumig a oiseless eviromet, Figure 5.(a) shows the simulated eye diagram at the frot-ed output i respose to a - PRBS NRZ data sequece represeted by a iput Electrical, Electroic ad Computer Egieerig 7

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver curret of A peak-to-peak. As show, the iverse scalig ad iductive peakig produce a complete ope eye, however, at the cost of high power cosumptio. The retimed data eye diagram is illustrated i Figure 5.(b). Usig the output show i Figure 5.(b), the BER of the system was calculated. With a - Gb/s pseudoradom bit patter, the BER is better tha -. The implemetatio of the auto-biasig circuit i the frot-ed madates a sufficiet low corer frequecy to esure stability which uavoidably prologs the settlig time of the whole system. Equatio 4.47 deotes that the FLL is capable of lockig at the data rate of withi approximately 5 s. Ufortuately, the correct frequecy capture ca oly occur after the iput data sigal has bee properly biased..5 Differetial output voltage [V] -.5 -. -.5.5 Time [s].5 x -6 (a). Differetial output voltage [V].5 -.5 -..5.5 3 3.5 Time [s] x -6 (b) Figure 5. Lock trasiets of the (a) frequecy-locked loop; ad (b) phase-locked loop. Electrical, Electroic ad Computer Egieerig 7

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver As show i Figure 5.(a), upo receivig a Gb/s PRBS sequece of legth - the adequate frot-ed sigal biasig together with frequecy capture is oly achieved after about.4 μs. Oce the frequecy is captured, the PLL loop requires a trasitio of approximately μs before it locks. The voltage ripple of the PLL cotrol lie is approximately mv. Figures 5.3(a) ad 5.3(b) depict the recovered clock sigal i both the time ad frequecy domais i respose to a Gb/s radom data sequece of legth -. The phase oise at a MHz offset is approximately equal to -98.8 dbc/hz as show i Figure 5.3(b). With a radom sequece of legth -, the rms jitter is. ps... Voltage [V].9.8.7.6 4 6 8 Time [s] x - (a) Output voltage [dbv] - -4-6 -8 -.94.96.98..4.6 Frequecy [GHz] (b) Figure 5.3 (a) Recovered clock sigal i time domai; ad (b) recovered clock spectrum. Electrical, Electroic ad Computer Egieerig 7

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver The followig figures demostrate a example of the expected output whe a certai amout of oise is ijected ito the system. White Gaussia oise with a sigal-to-oise ratio of 8 db was geerated with a wg commad i MATLAB. The sample oise was the superimposed oto the iputs of the fot-ed. As show i the figures, the Gb/s eye opeig at the output of the frot-ed is still well defied i the presece of a oise source with a SNR of 8 db..8.4 Voltage [V] -.4 -.8 4 6 8 4 Time [s] x - 3.5 (a) 3 Voltage [V].5.5.5.8..4.6.8 Time [s] x -9 (b) Figure 5.4 Eye diagram of (a) the frot-ed differetial output; ad (b) the retimed data output i the presece of oise sources i the system. Figure 5.5 depicts the phase oise for a radom data sequece of legth -. The phase oise is approximately equal to -94.8 dbc/hz at a MHz offset, ad the resultig closedloop jitter is.6 ps rms. Electrical, Electroic ad Computer Egieerig 73

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver Output voltage [dbv] - -4-6 -8 - -.94.96.98..4.6 Frequecy [GHz] Figure 5.5 Recovered clock spectrum i the presece of oise sources i the system. As show, oise sigificatly degrades the eye opeig of the frot-ed output ad the jitter performace of the system. As ca be expected, the system BER performace ad operatig frequecy will be limited by the amout of oise preset. The total power cosumed by the circuit is 55 mw from a 3.3 V supply. The frot-ed, the VCO, the PLL ad the frequecy detector circuits cosume 6 mw, 7.43 mw, 5.6 mw ad 5.3 mw respectively. Ufortuately, due to the low photo-geerated iput curret, log-chai voltage amplifiers with large tail currets are ecessary to amplify the iput sigals to adequate amplitudes ad results i high power cosumptio i the frot-ed circuit. 5.3 LAYOUT The complete system was realised i a four-metal double-poly.35 μm CMOS process with a supply voltage of 3.3 V. I order to suppress oise ad iterferece, loop filters are itegrated moolithically. Loop filter capacitors for both the PLL ad FLL are itegrated o chip usig liear double-poly capacitors. Resistors are implemeted usig poly-silico resistors. As discussed i the previous chapters, poly-silico is least process coditios depedet ad is ot voltage depedet. The frot-ed circuit ad the CDR system are separated by a substrate cotacts to prevet iterferece. Figure 5.6 shows the layout of the complete system. The core area is. mm. Electrical, Electroic ad Computer Egieerig 74

Chapter 5 Uiversity of Pretoria etd Che, Y-J (5) Optical Receiver 853 µm 35 µm Figure 5.6 Layout of the optical receiver. Electrical, Electroic ad Computer Egieerig 75

Uiversity of Pretoria etd Che, Y-J (5) CHAPTER 6 CONCLUSION 6. PHOTODETECTOR A low cost, moolithic photodetector is feasible. With spatially modulated light methodology, the photodetector with the p-juctio formed by the active implatatio ad the p- substrate realised i a stadard.35 μm CMOS process ca be used i optical commuicatio operatig up to a data rate of 4.5 Gb/s i the oretur-to-zero mode. Despite the high speed respose obtaiable, the detector resposivity is traded off. At the wavelegth of 86 m, the detector resposivity is relatively low (.38A/W) for a 59% active area detector. Noetheless, this o-optimal resposivity is partially compesated by the iheret low detector capacitace that greatly profits high speed fibre optical systems. 6. FRONT-END Research has bee doe o devisig high speed, high gai trasimpedace amplifiers. However, ot much has bee doe to miimise the equivalet iput oise curret. At the frot-ed of a high speed operatig system, a desig challege arises i achievig high speed, moderate trasimpedace gai, low equivalet iput oise curret simultaeously. I order to achieve the sesitivity specificatio stipulated for gigabit fibre chael systems, the badwidth of the trasimpedace amplifier is compromised. The preamplifier exhibits a sesitivity better tha -7 dbm at a bit-error-rate of -. The high badwidth ad further amplificatio is achieved by the limitig amplifier based o the iverse scalig topology. The amplifier operates from a sigle voltage supply ad exhibits a badwidth greater tha the miimum requiremet. To obtai high operatig frequecy, the system results i relatively high power dissipatio. Nevertheless, i may LAN systems power supply is substatial. The postamplifier was implemeted as part of the DC cotrol to esure a reasoable performace of the frot-ed circuit at differet process coditios. The low-filter corer frequecy required for the stability issue results i a log settlig time. Ufortuately, it cosequetly prologs the trasiet time for the CDR circuit. The voltage gai stages, high 76

Chapter 6 Uiversity of Pretoria etd Che, Y-J (5) Coclusio speed iverters, are modified from the push-pull amplifier. To achieve reasoable gai ad ' ' output bias, the iequality K ( W L) K ( W L) p p must be satisfied. Typically, the mobility of PMOS trasistors is much slower tha that of the NMOS trasistors. To satisfy the above-metioed coditio, strog PMOS trasistors ad weak NMOS devices are required. As a result, the effect of strog PMOS trasistors becomes promiet ad degrades the frequecy respose sigificatly i the worst-zero case simulatio. 6.3 CLOCK AND DATA RECOVERY CIRCUIT To achieve high speed ad low power cosumptio, a two-stage differetial rig oscillator was implemeted. The phase shift requiremet is established by itroducig additioal delays i each stage. Uder process, voltage ad temperature variatios, the oscillatio is sustaied by the wide tuig rage of the oscillator. The ability of maitaiig the output hold level at the sample-ad-hold phase detector makes the system tolerat to the cosecutive data bits ad allows the cotrol voltage for the VCO to be kept relatively costat. Nevertheless, phase compariso is a amplitude sesitive process. Ay fluctuatio i the iput sigals may cause a slight shift of the paradigm of phase compariso. As it is difficult to maitai costat VCO voltage swigs, VCO frequecy fluctuatio due to oise i the loop or phase lockig istataeously leads to VCO amplitude fluctuatio. As a result, a small ripple persists o the cotrol lie i phase lock. The frequecy detector exhibits reliable frequecy acquisitio if the frequecy differece is withi ±3% of the data rate. Durig frequecy acquisitio, false lockig oto harmoics or subharmoics is suppressed by the low-gai charge pump ad low pulse desity at the output of the detector. If the iitial VCO frequecy is close to a harmoic or subharmoic frequecy, false lockig may still occur. However, with the iitial cotrol voltages set at V DD /, as estimated i Figure 4.8, the occurrece is ulikely uder process variatios. Oce the clock frequecy is brought to the viciity of the data rate, the outputs of the frequecy detector stays uasserted. Cosequetly, a steady cotrol voltage ca be maitaied to suppress the jitter beig added to the VCO output. Electrical, Electroic ad Computer Egieerig 77

Chapter 6 Uiversity of Pretoria etd Che, Y-J (5) Coclusio The complete system is itegrated i a stadard.35 μm CMOS process without ay process modificatios. Frequecy sychroisatio, phase lockig ad data regeeratio is performed withi the CDR circuit. As show i Chapter 5, the eye opeig of the retimed data i respose to a Gb/s radom data sequece of legth - is sufficietly wide ad a reasoable jitter performace at GHz may be achieved. 6.4 FUTURE WORK Itegratig silico photodetectors i a stadard CMOS process is a feasible solutio for a high-speed optical commuicatio etwork. I order to operate i a high-speed eviromet, however, the resposivity of the detector is ievitably traded off. As a result, the frot-ed, viz. the trasimpedace amplifier ad the limitig amplifier, requires a comparatively high coversio gai to amplify the small iput curret to a reasoable voltage swig. A overall gai of approximately 95 dbω has ofte bee implemeted i a stadard.35 μm CMOS process for systems operatig betwee Gb/s ad.5 Gb/s. Realisig a system with a gai of approximately 3 dbω, while achievig a high badwidth, demads a log chai implemetatio which udesirably icreases the group delay ad degrades the phase respose. With a.35 μm CMOS process, the realisatio of high-speed operatig systems with a extremely high gai becomes impeded. Give this difficulty, a lower CMOS process techology could be implemeted to ease the badwidth while achievig a large coversio gai. Aother solutio is the implemetatio of active feedback together with iductive peakig ad egative Miller capacitace techiques [44]. However, each stage requires four iductors i the rage of H for gigabit badwidth i a.35 μm CMOS process that will result i eormous area overhead. Furthermore, the magetic crosstalk amog coils may severely ifluece ad degrade the CDR performace [45]. The oise performace of the rig oscillator is relatively poor. However, it is still capable of meetig the gigabit fibre chael specificatio. I a system where lower oise is madatory, the LC oscillator has to be used at the cost of a large area ad arrow tuig rage. The ability of LC oscillators to more accurately predict the resoace frequecy could suppress frequecy fluctuatios ad ease the phase compariso. Furthermore, differetial curret steerig logic [46] could also be implemeted istead of voltage switchig flip-flops to suppress the commo-mode oise. Electrical, Electroic ad Computer Egieerig 78

REFERENCES Uiversity of Pretoria etd Che, Y-J (5) [] G. Keiser, Optical Fiber Commuicatios, McGraw-Hill Iteratioal Editios, Third Editio, Sigapore, pp. 45-48, 68 ad 36,. [] T.K. Woodward ad A.V. Krishamoorthy, -Gb/s Itegrated Optical Detectors ad Receivers i Commercial CMOS Techologies, IEEE Joural of Selected Topics i Quatum Electroics, Vol. 5, No., pp. 46-56, March/April 999. [3] H. Zimmerma, T. Heide ad A. Ghazi, Moolithic high-speed CMOSphotoreceiver, IEEE Photoics Techology Letters, Vol., pp.54-56, February 999. [4] J. Geoe, D. Coppée, J.H. Steis, R.A. Vouckx ad M. Kuijk, Calculatio of the Curret Respose of the Spatially Modulated Light CMOS Detector, IEEE Trasactio o Electro Devices, Vol. 48, No. 9, pp. 89-9, September. [5] C. Toumazou ad S.M. Park, Widebad low oise CMOS trasimpedace amplifier for gigahertz operatio, Electroics Letters, Vol. 3, No. 3, pp. 94-96, th Jue 996. [6] M. Igels, G. Va der Plas, J. Crols, ad M. Steyaert, A CMOS 8 THzΩ 4 Mb/s Trasimpedace Amplifier ad 55 Mb/s LED-Driver for Low Cost Optical Fiber Liks, IEEE Joural of Solid State Circuits, Vol. 9, No., pp. 55-558, December 994. [7] S.M. Park ad C. Toumazou, A Packaged Low-Noise High-Speed Regulated Cascode Trasimpedace Amplifier Usig a.6 μm N-Well CMOS Techology, Europea Solid State Circuits Coferece, pp. 43-435, September. [8] J. Lee, S-J. Sog, S.M. Park, C-M. Nam, Y-S. Kwo ad H-J. Yoo, Q Multichip o Oxide of Gb/s 8dB Fully-Differetial CMOS Trasimpedace Amplifier for Optical Itercoect Applicatios, ISSCC /Sessio 4/Backplae Itercoected ICs/4.7. 79

Refereces Uiversity of Pretoria etd Che, Y-J (5) [9] S.M. Park, J. Lee ad H-J. Yoo, -Gb/s 8-dBΩ Fully Differetial CMOS Trasimpedace Amplifier i Multichip o Oxide Techology for Optical Itercoects, IEEE Joural of Solid State Circuits, Vol. 39, No. 6, pp. 97-974, Jue 4. [] K. Schrodiger, J. Stimma, ad M. Mauthe, A Fully Itegrated CMOS Receiver Frot-Ed for Optic Gigabit Etheret, IEEE Joural of Solid State Circuits, Vol. 37, No. 7, pp. 874-88, July. [] B. Razavi, A 6Mb/s 4.5pA/ Hz CMOS Trasimpedace Amplifier, ISSCC Digest of Techical Papers, pp. 6-63, February. [] T. Yoo ad B. Jalali, Gbit/s fiber chael CMOS trasimpedace amplifier, Electroics Letters, Vol. 33, No. 7, pp. 588-589, 7 th March 997. [3] T. Nakahara, H. Tateo, N. Ishihara ad C. Amao, High sesitivity -Gb/s CMOS receiver itegrated with a III-V photodiode by wafer-bodig, preseted at the LEOS sprig Meetig. [4] L. Bouzerara, M.B. Guermaz, H. Escid, ad M.T. Belaroussi, High Badwidth ad Low Noise Optimized Trasimpedace Amplifier i.8 µm CMOS Techology, PROC. 4th Iteratioal Coferece o Microelectroics, Vol., NIS, Serbia ad Moteegro, pp. 555-558, 6-9 May 4. [5] B. Razavi, Desig of Aalog CMOS Itegrated Circuits, McGraw-Hill, New York, pp. 8, 379, 483, 55-56 ad 64,. [6] E. Sackiger ad W.C. Fischer, A 3-GHz 3-dB CMOS Limitig Amplifier for SONET OC-48 Receivers, IEEE Joural of Solid State Circuits, Vol. 35, No., pp. 884-888, December. [7] H. Werker, S. Mechig, C. Holuigue, C. Eber, G. Mitteregger, E. Romai, F. Roger, T. Blo, M. Moyal M. Vea, A. Melodia, J. Fisher, G. le Grad de Mercey, ad H. Geib, A -Gb/s SONNET-Compliat CMOS Trasceiver With Low Crosstalk ad Electrical, Electroic ad Computer Egieerig 8

Refereces Uiversity of Pretoria etd Che, Y-J (5) Itrisic Jitter, IEEE Joural of Solid State Circuits, Vol. 39, No., pp. 349-358, December 4. [8] M. Igels ad M.S.J. Steyaert, A -Gb/s,.7-μm CMOS Optical Receiver with Full Rail-to-Rail Output Swig, IEEE Joural of Solid State Circuits, Vol. 34, No. 7, pp. 97-977, July 999. [9] N. Ishihara ad Y. Akazawa, A Moolithic 56 Mb/s Clock ad Data Recovery PLL Circuit Usig the Sample-ad-Hold Techique, IEEE Joural of Solid State Circuits, Vol. 9, No., pp. 566-57, December 994. [] S.B. Aad ad B. Razavi, A CMOS Clock Recovery Circuit for.5-gb/s NRZ Data, IEEE Joural of Solid State Circuits, Vol. 36, No. 3, pp. 43-439, March. [] J. Savoj, B. Razavi, A -Gb/s CMOS Clock ad Data Recovery Circuit, Digest of Symposium o VLSI Circuits, pp. 36-39, Jue. [] H. Djahashahi, C. Adre, T. Salama, Differetial CMOS Circuits for 6- MHz/933-MHz Clock ad Data Recovery Applicatios, IEEE Joural of Solid State Circuits, Vol. 35, No. 6, pp. 847-855, Jue. [3] NCITS workig draft, Fibre chael physical iterfaces (FC-P), Rev. 3, America Natioal Stadard for Iformatio Techology, pp. 56, December. [4] IEEE Std 8.3-, Part 3: Carrier sese multiple access with collisio detectio (CSMA/CD) access method ad physical layer specificatios, Sectio Three, The Istitute of Electrical ad Electroics Egieers, Ic., New York, pp. 3-3, March. [5] M. Kuijk, D. Coppee ad R. Vouckx, Spatially Modulated Light Detector i CMOS with Sese-Amplifier Receiver Operatig at 8 Mb/s for Optical Data Lik Applicatio ad Parallel Optical Itercoects Betwee Chips, IEEE Joural of Selected Topics i Quatum Electroics, Vol. 4, No. 6, pp. 4-45, November/ December 998. Electrical, Electroic ad Computer Egieerig 8

Refereces Uiversity of Pretoria etd Che, Y-J (5) [6] R.C. Jaeger, Microelectroic Circuit Desig, McGraw-Hill Iteratioal Editio, pp. 5-6, 59 ad 533, 997. [7] Austriamicrosystems (AMS),.35 µm CMOS C35 Desig Rules ENG-83, Revisio #:.,. [8] S.M. Sze, Semicoductor Devices Physics ad Techology, Bell Telephoe laboratories, Ic., New York, pp. 56, 985. [9] J.A. McNeill, Jitter i Rig Oscillators, IEEE Joural of Solid State Circuits, Vol. 3, No. 6, pp. 87-879, Jue 997. [3] J.K. Kow, T.K. Heo, S-B. Cho, ad S.M. Park, A 5-Gb/s /8 Rate CMOS Clock ad Data Recovery Circuit, Proceedigs of the 4 Iteratioal Symposium o Circuits ad Systems, Vol. 4, pp. IV-93-IV-96, 3-6 May 4. [3] B. Razavi, Aalysis, Modelig, ad Simulatio of Phase Noise i Moolithic Voltage-Cotrolled Oscillators, IEEE Custom Itegrated Circuits Coferece, Vol. 36, No. 3, pp. 33-36, 995. [3] J.G. Maeatis, Low-Jitter Process-Idepedet DLL ad PLL based o Self-Biased Techiques, IEEE Joural of Solid State Circuits, Vol. 3, No., pp. 73-73, November 996. [33] K. Kishie, K. Ishii ad H. Ichio, Loop-Parameter Optimizatio of a PLL for a Low-Jitter.5-Gb/s Oe-Chip Optical Receiver IC With :8 DEMUX, IEEE Joural of Solid State Circuits, Vol. 37, No., pp. 38-5, Jauary. [34] A. Hajimiri, S. Limotyrakis ad T.H. Lee, Jitter ad Phase Noise i Rig Oscillators, IEEE Joural of Solid State Circuits, Vol. 34, No. 6, pp. 79-84, Jue 999. [35] K. Lim, C-H Park, D-S Kim ad B. Kim, A Low-Noise Phase-Locked Loop Desig by Loop Badwidth Optimizatio, IEEE Joural of Solid State Circuits, Vol. 35, No. 6, pp. 87-84, Jue. Electrical, Electroic ad Computer Egieerig 8

Refereces Uiversity of Pretoria etd Che, Y-J (5) [36] P.R. Gray, P.J. Hurst, S.H. Lewis ad R.G. Meyer, Aalysis ad Desig of Aalog Itegrated Circuits, Fourth Editio, Joh Wiley & Sos, Ic., New York, pp. 68, 79-736 ad 759-76,. [37] K. Vichiechom ad W. Liu, Aalysis of Phase Noise due to Bag-Bag Phase Detector i PLL-based Clock ad Data Recovery Circuits, Proceedigs of the 3 Iteratioal Symposium o Circuits ad Systems, Vol., pp. I-67-I-6, 5-8 May 3. [38] B. Razavi, Prospects of CMOS Techology for High-Speed Optical Commuicatio Circuits, IEEE Joural of Solid-State Circuits, Vol. 37, No. 9, pp. 35-45, November. [39] M. Masuri ad C-K K. Yag, Jitter Optimizatio Based o Phase-Locked Loop Desig Parameters, IEEE Joural of Solid State Circuits, Vol. 37, No., pp. 375-38, November. [4] B. Stillig, Bit rate ad protocol idepedet clock ad data recovery, Electroic Letters, Vo. 36, No. 9, pp. 84-85, 7 th April. [4] R. Hossai, L.D. Wroski ad A. Albieki, Low Power Desig Usig Double Edge Triggered Flip-Flops, IEEE Trasactios o Very Large Scale Itegratio Systems, Vol., No., pp. 6-65, Jue 994. [4] M. Afghahi ad J. Yua, Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits, IEEE Joural of Solid State Circuits, Vol. 6, No. 8, pp. 68-7, August 99. [43] J. R. Smith, Moder Commuicatio Circuits, Secod Editio, McGraw-Hill Iteratioal Editio, Sigapore, pp. 33, 998. [44] S. Galal ad B. Razavi, -Gb/s Limitig Amplifier ad Laser/Modulator Driver i.8-µm CMOS Techology, IEEE Joural of Solid State Circuits, Vol. 38, No., pp. 38-46, December 3. Electrical, Electroic ad Computer Egieerig 83

Refereces Uiversity of Pretoria etd Che, Y-J (5) [45] M.A.T. Saduleau ad E. Stikvvort, Iductor-less, Gb/s Limiter with mv Sesitivity ad Offset/Temperature Compesatio i Baselie CMOS8, Proceedigs of the 9th Europea Solid-State Circuits Coferece, pp. 53-56, 6-8 September 3. [46] J. Lee, K. S. Kudert, ad B. Razavi, Aalysis ad Modelig of Bag-Bag Clock ad Data Recovery Circuits, IEEE Joural of Solid State Circuits, Vol. 39, No. 9, pp. 57-58, September 4. [47] C.H. Edwards, Jr., ad D.E. Pey, Elemetary Differetial Equatios With Boudary Value Problems, Third Editio, Pretice-Hall, New Jersey, pp. 69-69, 993. Electrical, Electroic ad Computer Egieerig 84

85 APPENDIX A: DERIVATION FOR THE MINORITY CARRI- ER CONCENTRATION The cotiuity equatio for electios i a p-type regio of a illumiated detector has the form [4] ( ) x p p p p e y t g y D x D t α τ =, (A.) with: x depth of the material y width of the material t time p cocetratio of electros iitial cocetratio of electros D Diffusio costat of electros τ miority carrier lifetime α absorptio coefficiet g(t,y) electro geeratio rate The boudary coditios are p (,y,t) =, for -b < y < b ad t > p (a,y,t) =, for -b < y < b ad t > p (x,-b,t) =, for < x < a ad t > p (x,b,t) =, for < x < a ad t > p (x,y,) =, for < x < a ad -b < y < b where a ad b deote the depth ad the legth of a sigle detector figer. I order to solve the ohomogeeous formula of equatio A., Modificatio is applied by lettig [47] p (x,y,t) = v(x,y,t) ψ(x,y) to chage the depedet variable. The, t v t y y v y x x v x p p p = = = ad, ψ ψ (A.) Substitutig these coditios ito equatio A. results i ( ) ( ) ( ) ( ) x e y t g y x t y x v y y v D x x v D t v α τ ψ τ ψ ψ =,,,, (A.3) Uiversity of Pretoria etd Che, Y-J (5)

Appedix A Uiversity of Pretoria etd Derivatio Che, for Y-J the (5) Miority Carrier Cocetratio A homogeeous equatio ca be obtaied if the followig coditio is applied ψ ψ D ψ x y τ τ αx ( x, y) g( t, y) e = Agai applyig a chage of depedet variable by lettig ψ(x,y) = s(x,y) ζ(x) By substitutio, equatio A.4 becomes (A.4) (A.5) s s ( (, ) ) αx ζ s x y ζ g( t, y) e = (A.6) x y D τ D τ D Equatio A.6 becomes homogeeous whe (, ) α ζ ζ g t y e x = (A.7) D τ D τ D The complemetary fuctio of equatio A.7 is ζ c ( x) = Aexp x B exp x Dτ Dτ Set the particular solutio to ζ p (x) = C exp(-αx) D with ζ p = -αc exp(-αx) ad ζ p = α C exp(-αx) Substitutio yields α C exp D τ D τ αx ( αx) ( C exp( αx) D) = g( t,y) e Equatig the coefficiets of like terms, it yields the particular solutio ζ p (x) = g(t,y) exp(-αx)/(α D (/ τ )) ad the geeral solutio ζ ( x) = Aexp D τ x B exp D τ x D ( t,y) g α D αx e τ (A.8) The iitial coditios are Provided p (,y,t) = v(,y,t) ψ(,y) = p (a,y,t) = v(a,y,t) ψ(a,y) = p (x,-b,t) = v(x,-b,t) ψ(x,-b) = p (x,b,t) = v(x,b,t) ψ(x,b) = ψ(,y) = ad ψ(a,y) = ψ(x,-b) = ψ(x,b) = Electrical, Electroic ad Computer Egieerig 86

Appedix A Derivatio for the Miority Carrier Cocetratio Electrical, Electroic ad Computer Egieerig 87 The, v(,y,t) = v(a,y,t) = v(x,-b,t) = v(x,b,t) = Furthermore, lettig s(,y) = s(a,y) =, the ζ() = ad ζ(a) = v Applyig the iitial coditios of ζ to equatio A.8, it yields ( ) ( ) = ) exp( exp exp ) exp( sih sih sih sih x D x D a a D a D x D t,y g D a D x x α τ τ α τ τ τ α τ τ ζ The iitial coditios ψ(x,-b) = s(x,-b) ζ(x) ad ψ(x,b) = s(x,b) ζ(x) imply s(x,-b) = s(x,b) = -ζ(x). It is the required to solve s(x,y) with the adopted boudary coditios, the boudary-value problem is described by ( ), = y x s D y s x s τ, < x < a, -b < y < b s(,y) = s(a,y) =, -b < y < b (A.9) s(x,-b) = s(x,b) = -ζ(x) < x < a This Dirichlet problem cosists of two ohomogeeous iitial coditios ad is ot directly susceptible to the method of separatio of variables. The boudary-value problem i (A.9) is split ito two problems each with a ohomogeeous boudary coditio. The sum of the solutios s ad s is the solutio of the origial problem. Substitutio of s(x,y) = XY, the the separatio of variables leads to λ τ = = D Y Y X X (A.) where λ is a costat. The boudary coditios of both the sigle ohomogeeous boudary-value problems have X() = X(a) =. The the eigevalue ad the associated eigefuctio for X λx = for both solutios are λ = π /a, X = si(π/a) for =,, 3 Equatio A. gives a secod eigevalue problem = Y D Y λ τ Uiversity of Pretoria etd Che, Y-J (5)

Appedix A Derivatio for the Miority Carrier Cocetratio Electrical, Electroic ad Computer Egieerig 88 The geeral solutio to the above differetial equatio is = y a D B y a D A y Y sih cosh ) ( π τ π τ (A.) Let the first sigle ohomogeeous boudary-value problem have a ohomogeeous boudary coditio at s(x,-b) = -ζ(x), the s(x,b) =. Applyig the iitial coditio s(x,b) = to equatio A., the ( ) = y b a D c y Y sih ) ( π τ where = b a D A c sih / π τ. The power series solutio is therefore of the form ( ) ( ) = = sih si, y b a D x a c y x s π τ π The coefficiets {c } is calculated by settig y = -b, ( ) ( ) ( ) ( ) = = = sih si, x b b a D x a c b x s ζ π τ π Thus, ( ) ( ) = a dx x a x b a D a c si sih π ζ π τ Similarly, the solutio to the secod sigle ohomogeeous boudary-value problem with the boudary coditios s(x,b) = -ζ(x) ad s(x,-b) = is ( ) ( ) = = sih si, y b a D x a c y x s π τ π with ( ) ( ) = a dx x a x b a D a c si sih π ζ π τ Therefore the fial solutio to the fuctio s is s(x,y) = s (x,y) s (x,y), which is simplified to Uiversity of Pretoria etd Che, Y-J (5)

Appedix A Uiversity of Pretoria etd Derivatio Che, for Y-J the (5) Miority Carrier Cocetratio π π cosh y si x = D τ a a s = a π cosh b Dτ a a ( x, y) ζ ( x) π si x dx. a The solutio for ψ(x,y) is obtaied by addig s(x,y) to ζ(x), i.e. ψ(x,y) = s(x,y) ζ(x). The fial step is to solve the ew boudary-value problem described by v = D t v D x v v y τ v(,y,t) =, for -b < y < b ad t > v(a,y,t) =, for -b < y < b ad t > v(x,-b,t) =, for < x < a ad t > v(x,b,t) =, for < x < a ad t > v(x,y,) = - ψ(x,y), for < x < a ad -b < y < b Substitutig v(x,y,t) = XYT i equatio A., the followig is obtaied X Y T = X Y D T τ D If each term of the above equatio is described by a costat, the, where λ ad μ are costats. X λ X = Y μ Y =, ad T ((/D τ ) λ μ ) D T = (A.) With the boudary coditios, the eigevalues ad the associatedeigefuctios for X ad Y are λ = mπ/a, X = c si(mπx/a), m =..3 μ = (-)π/b, Y = c cos((-)πy/b), =..3 ad the geeral solutio for T has the form T = c 3 exp(-((/d τ ) λ μ ) D t) Applyig the superpositio priciple, the power series solutio is v( x, y, t) = m= = A m (( / Dτ ) ( mπ / a) (( ) π / b) e ) mπ ( π si x cos y a b D t ) Equatig equatio A.3 to - ψ(x,y) at t =, the coefficiets {A m } is b a mπ ( ) ( ψ ( x, y) ) si b x cos π ydxdy ab a b Am = Fially, the solutio of the origial problem is p (x,y,t) = p,illu (x,y,t) = ψ(x,y) v(x,y,t) (A.3) Electrical, Electroic ad Computer Egieerig 89

Appedix A Uiversity of Pretoria etd Derivatio Che, for Y-J the (5) Miority Carrier Cocetratio = s(x,y) ζ(x,y) v(x,y,t) (A.4) where ψ(x,y) = s(x,y) ζ(x) is the steady-state solutio ad v(x,y,t) is the trasiet solutio. I order to determie the miority carrier distributio after the illumiatio was cut off, the cotiuity equatio for the miority carriers i a p-type regio is rewritte i the form p t = D p x αx with the carrier geeratio rate ( ) D p y g t, y e equals to zero. p τ At the time the illumiatio was cut off, the iitial cocetratio of the miority carriers at time zero is described by p,illu (x,y,t ), equatio A.4, with t deotig the duratio of illumiatio. Thus, the boudary coditios for the boudary value problem are p (,y,t) =, for -b < y < b ad t > p (a,y,t) =, for -b < y < b ad t > p (x,-b,t) =, for < x < a ad t > p (x,b,t) =, for < x < a ad t > p (x,y,) = p,illu (x,y,t ), for < x < a ad -b < y < b Applyig the same argumet as previously described i the fist boudary value problem, the ew ζ(x) ad v(x,y,t) are with v ( x, y, t) v ζ v ( x) = m= = A = sih x, ad Dτ sih a Dτ m (( / Dτ ) ( mπ / a) (( ) π / b) e ) mπ ( π si x cos y a b D t ) ( ( x, y, t ) s ( x, y) ζ ( x) ) b a mπ ( ) b p, ILLU v v si x cos π ydxdy ab a b Am = The, the miority carrier cocetratio profile after the illumiatio was cut off is p (x,y,t) = ψ v (x,y) v v (x,y,t) = s v (x,y) ζ v (x) v v (x,y,t) Electrical, Electroic ad Computer Egieerig 9

Uiversity of Pretoria etd Che, Y-J (5) APPENDIX B: FREQUENCY DETECTOR LOGIC The logic cell desig of the frequecy detector is described i this sectio. Oly the ivertig logics were implemeted, sice it require less digital cells ad occupy less circuit area. From table 4., the miimum sum of products for the UP ad DOWN sigals were derived as follows UP = A C(B D B D BD ) = A CB D = (A C ) (BD) = [(A C ) (BD) ] = [(A C) (B D ) ] Ad, DOWN = AC (B D B D BD ) = AC B D = [(AC ) (B D ) ] 9

Uiversity of Pretoria etd Che, Y-J (5) APPENDIX C: CIRCUIT DIAGRAMS SML detector TIA TIA Auto DC cotrol Auto DC cotrol First stage of LA Auto DC cotrol Auto DC cotrol Secod stage of LA Postamplifier V out Figure C. Frot-ed overview. Rf M W = 6u.35u I RPOLYH W = u L = u Rf Vo RPOLYH W = u L = u M W = u Figure C. Trasimpedace amplifier. 9

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams W = 4.3u W = 4.3u W = u W = u W = 3.6u L = u L = u W =.5u L = u W = 3.6u W =.5u W =.7u L = u W =.4u L = u W =.4u L = u W = 6.u W = 6.u M = W = 3.5u W = 3.5u W =.u W =.u W = 7u L = u M = 8 W = 7u L = u M = 4 W = 7u L = u M = 8 W =.85u W =.u L = u W =.u L = u W =.85u W =.55u W =.5u L = u W =.5u L = u W =.55u Vo Vo A W = 7u W = 7u B W = 5.9u.35u Vi Vi Vbias Vbias Vbias W = 5.9u Vbias W = 7u Vbias L = u M = W = 7u L = u M = W =.7u W =.5u W =.3u L = u W =.3u L = u W =.5u A B W = 8.4u W = 8.4u Vbias W = 7u L = u M = 5 Figure C.3 First stage of the limitig amplifier. Electrical, Electroic ad Computer Egieerig 93

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams W =..7u W =.4u L = u W =.4u L = u W =.7u W =.5u W =.3u L = u W =.3u L = u W =.5u W =.85u W =.u L = u W =.u L = u W =.85u W =.55u W =.5u L = u W =.5u L = u W =.55u A B W =.u W =.u W = 8.4u W = 8.4u W = 7u W = 7u W = 5.9u.35u W = 5.9u Vbias W = 7u Vbias L = u M = 8 Vi Vi W = 7u L = u M = 5 Vbias W = 7u Vbias L = u M = W = 7u L = u M = W = u L =.5u W =.u M = Vo A B W = 5.9u W = 5.9u Vbias W = 7u L = u M = Figure C.4 Secod stage of the limitig amplifier. Electrical, Electroic ad Computer Egieerig 94

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams W =.9u L = u W =.9u L = u W =.9u L = u W =.9u L = u W = 8u W = 8u W = 8u W = 8u W = 4.45u W = 4.45u W = 4.45u W = 4.45u W = 4u W = 4u W = 4u W = 4u W = 7u L =.6u M = W = 7u L =.6u M = W = u L = u W = 8u W =.45u W = u L =.5u M = W = u L = u M = W = u L =.5u M = Vi CPOLY AREA =.5 PERI = 6u RPOLY W =.5u L = 8u W = 5u L = u W =.4u L = 7.4u W =.4u L =.5u W = 8u W =.45u W = 8u W =.45u W = u W = 3.75u W = u Vo W = 3.75u Figure C.5 Postamplifier Electrical, Electroic ad Computer Egieerig 95

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams W =.9u L = u W =.9u L = u W = 8u W = 4u W = 8u W = 4u Vo Vi W = 4u W = 4u W = 7u L =.6u M = W = 7u L =.6u M = CPOLY W = u L = u AREA =.5 PERI = 6u W =.8u L = 4u W = 8u L = u W = u L =.5u M = W = u L =.5u M = W = u L = u W = u L = u M = Figure C.6 Auto DC-cotrol. W = 5u L = u W = 6.85u L =.5u I=uA W = 6.85u L =.5u Vbias_p Vbias W = 7u L = u I=5uA W = 7u L = u Vbias W = 4u L = u I=5uA W = 4u u Vbias_p Vbias_ W = 6.85u L =.5u W = 3.7u L =.5u W = 7u L = u W = 4u L = u W = 4u L = u W = 8u L = u RPOLY W = u L = 56u RPOLY W = u L = 6u RPOLY W = u L = 56u Figure C.7 Curret referece circuits. Electrical, Electroic ad Computer Egieerig 96

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams Upll Uf ll Uvco data_ac data_ac VCOI VCOI data data VCOI VCOI VCO_f iep VCO_f ie fiep fie data_dc data_dc VCOI VCOI VCOQ VCOQ data data VCOI VCOI VCOQ VCOQ clocki clockq cp cp clocki clockq coarsep coarse fiep fie coarsep coarse PD PD FD FD VCOI VCOI VCOQ VCOQ VCOI VCOI VCOQ VCOQ PLL FLL Figure C.8 CDR system. VCO data data VCOI VCOI data data VCOI VCOI VCO_fiep VCO_fie VCO_fiep VCO_fie U U data data VCOI VCOI Vi Vi VCOI VCOI Vopd Vopd Vopd Vopd Vv io Vv io VCO_fiep VCO_fie PD PLLChargePump Figure C.9 Phase locked loop. VCOI VCOI VCOQ VCOQ data data VCOI VCOI VCOQ VCOQ data data VCOhigh_dow VCOlow _up clocki clockq cp cp VCOhigh_dow VCOlow _up clocki clockq cp cp Ula VCOI Vi VCOI Vi Vo Vo Ula3 Vi Vi Vo Vo U Vi Vo Uiv Vi Vo clocki VCObuffer VCObuffer PAvco iv_chai Ula VCOQ Vi VCOQ Vi Vo Vo Ula Vi Vi Vo Vo U Vi Vo Uiv Vi Vo clockq VCObuffer VCObuffer PAvco iv_chai data data clocki clockq Uf d data data clocki clockq UP DOWN VCOlow _up VCOhigh_dow Ucharge_pump VCOlow_up VCOhigh_dow cp cp cp cp TSPDFF_FD FLLcharge_pump Figure C. Frequecy locked loop. Electrical, Electroic ad Computer Egieerig 97

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams gd cost gd cost cost Vbias_ VCOQ VCOQ gd VCOI W = 4u M = W = 6u W = 3u M = 4 W = 6u W = 4u M = W = 4u L = u M = 5 W = 4u L = u M = 5 W = 4u W = 4u W = 4u M = 3 M = 3 M = 3 RPOLY RPOLY RPOLY CPOLY AREA = 5p PERI = 6u L=u W = u L = u W = u CPOLY AREA = 5p PERI = 6u CPOLY AREA = 5p PERI = 6u L = u W = u W = 3u M = 4 W = 3u M = 4 gd W = 3u M = 4 W = 6u M = W = 6u M = W = 3u M = W = 3u M = W = 3u M = fast gd fast VCOI VCOQ slow W = 4u M = gd cost W = 4u M = VCOQ Vbias_p W = 7u L = u Vbias_p W = 4u L = u M = 4 PD W = 3u L = u W = 3u L = u W = u L = u W = u L = u FD PD FD fast fast W = 5u L = u W = 5u L = u slow L = u W = u W = u L = u slow W = 4u L = u M = 4 W = 5u L = u M = W = 4u L = u M = 4 W = 5u L = u M = W = 5u L = u M = W = u L = u M = W = 5u L = u M = W = u L = u M = W = 3u M = gd slow W = 4u M = 3 RPOLY L = u W = u CPOLY AREA = 5p PERI = 6u VCOI VCOI Figure C. Voltage cotrolled oscillator. Electrical, Electroic ad Computer Egieerig 98

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams VCOI VCOI Vbias_p W = u Vo Vbias M = W = u ckt W = 6.85u L =.5u M = W = 8u W = u M = ckt W = u M = 8 W = 6.65u Vo Voa W = 6.85u L =.5u M = 4 Vbias W = 3u W = 3u W = 8u W = 3u W = 3u W = 3u W = 3u Voz Voz Vo Vo Voa Voa VCOI W = 6u W = 6u W = 4u W = 4u VCOI VCOI VCOI Voa Voa Voaa Voaa W = 6u ckt W = 6u W = 4u W = 4u W = u W = 5u W = u W = 5u.35u ckt W = 5u ckt W = 5u M = 8 W = 6.65u VCOI VCOI Vi Voa Vi M = 8 W = 6.65u Voa M = 8 W = 6.65u Voz M = 5 W = 6.65u Voz M = 5 W = 6.65u Voa Voaa Voaa Vopd Vopd W = 6.85u L =.5u M = 4 Vbias W = 6.85u L =.5u M = 4 Vbias W = 6.85u L =.5u M = 4 Vbias W = 6.85u L =.5u M = 3 Vbias W = 6.85u L =.5u M = 3 Figure C. PLL uit: Phase detector. Electrical, Electroic ad Computer Egieerig 99

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams Vopd Vopd Vbias_p W =.5u L =.5u W = 4u L = u W = 6.85u L =.5u W =.6u L = 8u W = 4u L = u W =.5u L =.5u W = u L = u W =.6u L = 8u Vobs W = u L = u Vobs Vvio W = 7.4u L = u L = u W = 7.4u L = u W =.5u W =.5u L = u W = 7.4u L = u L = u W = 7.4u L = u W =.5u W =.5u L = u L = u W = 7.4u Vobs Vvio Vobs W =.5u L = u RPOLYH W = u L = 4u RPOLYH W = u L = 4u Vvio RPOLYH W = u L = 88u Vvio Vvio CPOLY AREA = 7.5 PERI =.66m RPOLYH W = u L = 88u Vvio CPOLY AREA = 7.5 PERI =.66m Figure C.3 PLL uit: Charge pump ad loop filter. data data clocki clockq data data clocki clockq clocki U6 D clocki Q U D clocki Q Q Q3 Q3 U5 D clocki Q Q Q5 Q5 Q3 Q5 Uad A C B Uor clocki NAND Uor3 A B C UP DETFF U7 clockq D data clocki data clocki Q TSPDFF U4 D clocki Q Q Q4 Q4 TSPDFF U3 D clocki Q Q Q6 Q6 Q4 Q6 Q3 Q5 A C B NOR Uad A C B NOR Uor A B NOR C DOWN DETFF TSPDFF clocki TSPDFF NAND Figure C.4 FLL uit: Frequecy detector. W = 3u W = 3u A W = 3u A W = 3.5u C B W = 3u C B W = 3.5u W = u W = u Figure C.5 FLL uit: NAND gate. Figure C.6 FLL uit: NOR gate. Electrical, Electroic ad Computer Egieerig

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams D clocki gd Mdt W =.u W =.4u W = 8u W = 4u clocki gd W =.4u W =.u clocki clocki gd W =.4u W = 8u clocki W = 8u Q W = 4u clocki gd clocki W =.u W =.4u clocki clocki W =.u W =.4u W = 8u W = 4u W = 4u W = 8u clocki gd clocki W =.4u W =.u gd clocki W =.u W = 4u Figure C.7 FLL uit: Double-edge triggered Flip-flop. W = 4.u W = 4.u W = 4.u W = 4.u W = 4.u clocki D W = 4.u W = u W = u Q Q W = u W = u W = u W = u W = u Figure C.8 FLL uit: Positive-edge triggered true sigle phase clocked flip-flop. Vi W = 8u W =.45u W = u W = 3.75u W = 4u W = u W = 4u M = W = u M = Vo Figure C.9 FLL uit: iverter chai. Electrical, Electroic ad Computer Egieerig

Appedix C Uiversity of Pretoria etd Che, Y-J (5) Circuit Diagrams W =.7u L =.4u L = u W =.5u L = u W =.5u W =.7u L =.4u Vo Vo Vi W = 5.9u W = 5.9u Vi Vbias W = 7u L = u M = Figure C. FLL uit: VCO buffer. W = u L = 4u M = 5 W = u L = 4u M = 5 W = u L = 4u W = u L = 4u W = u L = 4u W = u L = 4u W = u L = 4u M = 5 W = u L = 4u M = 5 VCOhigh_dow W = 5u L = u W = 5u L = u VCOlow _up cp Vbias_ W = 4u u cp W =.5u L = u W =.5u L = u W =.5u L = u W =.5u L = u W = 7.4u L = u W = 7.4u L = u L = u W = 7.4u cp cp cp L = u W = 7.4u L = u W = 7.4u cp cp RPOLY W = u L = 33.4u CPOLY AREA = 3.65 PERI = 7u CPOLY AREA =.65 PERI = 4u L = u W =.5u L = u W =.5u cp RPOLY W = u L = 33.4u W =.5u L = u W =.5u L = u W =.5u L = u Figure C. FLL uit: charge pump ad loop filter. Electrical, Electroic ad Computer Egieerig