AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APPLICATION TIME IN CORE BASED SOC

International Journal of Electronics and Communication Engineering & Technology (IJECET) Volume 7, Issue 2, March-April 2016, pp. 09-17, Article ID: IJECET_07_02_002 Available online at http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=7&itype=2 Journal Impact Factor (2016): 8.2691 (Calculated by GISI) www.jifactor.com ISSN Print: 0976-6464 and ISSN Online: 0976-6472 IAEME Publication AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APPLICATION TIME IN CORE BASED SOC Harikrishna Parmar ECC Department, Nirma University Ahmedabad, India Dr.Usha Mehta ECC Department, Nirma University Ahmedabad, India ABSTRACT System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today s integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That s why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their internal structural details. Such modular testing triggers the need of a special test access mechanism (TAM) to build communication between core I/Os and TAM and promises to minimize overall test time. In this paper, various issues are analyzed to optimize the Wrapper and TAM, which comprises the optimal partitioning of TAM width, assignment of cores to partitioned TAM width etc. Key words: TAM; SOC; Core Assignment; Test Bus Architecture, Test Wrapper Cite this Article: Harikrishna Parmar and Dr.Usha Mehta. An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application Time In Core Based SOC. International Journal of Electronics and Communication Engineering & Technology, 7(2), 2016, pp. 09-17. http://www.iaeme.com/ijecet/issues.asp?jtype=ijecet&vtype=7&itype=2 1. INTRODUCTION A conceptual modular testing is presented in [1], which includes three structural elements. 1. Test pattern source, 2. Sink and 3. The TAM and the test wrapper. Now a day, In large SoC, embedded cores are commonplace. Since embedded cores are not straight away approachable through chip s inputs and outputs, the special TAM is http://www.iaeme.com/ijecet/index.asp 9 editor@iaeme.com

Harikrishna Parmar and Dr.Usha Mehta needed to test the core at the system level [1] [2]. TAM establishes communication between the cores and chip input-output and does the job of transferring test data from chip input-output to the core and vice versa. Test wrapper establishes an interface between the core and its environment. TAM is essential for modular testing, because it instantly influences testing time of SoC. The present IEEE 1500 standard describes wrapper design only and leaves optimization of TAM to the system designer. Therefore, optimization of TAM is a functional area of research. A number of TAM architectures, which are working on different heuristics and algorithm, are proposed in [3]-[18]. The main motto of all these TAM architecture is to reduce testing time of SoC. Here, in this paper, an improved TAM is presented for the test bus architecture to get optimal testing time of SoC. The whole paper is organized as follows. Section II discusses the prior work on TAM in 2D SoC. The Problem statement is described in section III. Mathemtical model referred to establish the problem statement is shown in section IV, whereas section V discusses the experimental result analysis. Finally, section VI draws the conclusion. 2. PRIOR WORK Mainly there are three kinds of test access architectures [3]. 1. Multiplexing, 2. Distribution and 3. Daisychain architecture [4]-[7]. By using these architectures, a test bus and TestRail architecture were proposed in [8] and [9] respectively. A novel approach to reduce the test time of SoC is proposed in [10], which is based on genetic local search algorithm. The proposed method resolves the problem of TAM under the restriction such as core cluster and core placement cluster. The method allows the system designer to improve TAM and helps to make appropriate choices. Another approach to reduce test time based on the bandwidth matching concept is shown in [11], which emphasizes the multi-frequency TAM design. Using the method of serialization and deserialization, a high bandwidth source and sink are connected to the low bandwidth source and sink until bandwidth matches. In the second approach, the problem with the post-silicon validation method, which has limited debug access bandwidth to access internal signals, is described in [12]. The TAM based on flexible width architecture is shown in [13]. In this method, first lower bound of test time is set which does not depend on TAM structure and then the test bus assignment is done in such a way that, it achieves that lower bound. A TAM for the multiple identical cores is shown in [14], which utilize the uniform nature of the core and applies test simultaneously, which helps to minimize test time for core under test. In an another approach, testing of multiple identical core is done in such a way that, instead of taking typical test response data from the core, it takes a majority based value. The TAM architecture introduced in this paper is based on-chip comparator and majority analyzer [15] [16]. Reconfiguration of the multiple scan chain to minimize test application time for SoC is presented in [17]. Here, the whole paper is designed for the optimization of TAM for the test bus architecture. The architecture and results discussed in [18] and [19] is taken as a reference. The algorithm described to optimize Wrapper and TAM in test bus architecture is again developed and improved to get a further reduction in the test application time. http://www.iaeme.com/ijecet/index.asp 10 editor@iaeme.com

An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application Time In Core Based SOC 3. PROBLEM STATEMENT For the given N C number of cores for the SoC, including n i number of inputs, m i number of outputs, TAM width W, S C number of scan chain and length of scan chain li k for each core and P i number of test patterns, determine (i) The improved width of TAM bus (ii) ideal partition for TAM bus (iii) The assignment of cores to the partitioned TAM bus and (iv) The test schedule for the entire SoC, such that overall test application time is minimized. 4. MATHEMATICAL MODEL Initialization Let the total number of cores are N C Total number of input for a particular core is - n Total number of output for a particular core is m Number of test pattern given in a particular core is - P TAM width allocated is W Number of partition taken for TAM width W is B So, Width distribution is taken as if partition factor is two W 1 (i) = i W 2 (i) = W- i Where i varies from 1 to W/2 Here, a new variable ø is defined as Ø(i) = max(n(i),m(i)) Where i varies from 1 to N C Balance Wrapper Scan Chin Lets number of scan chain inside a particular core is Sc. Length of each scan chain is given as l1,l2..lsc Number of scan chain of length l1,l2 lsc is Z 1,Z 2.Z sc Now divide number of scan chain Z 1,Z 2..Z n by width W and find quotient an remainder. Q1=Z 1 /W R1 = Z 1 %W Q2=Z 2 /W R2= Z 1 %W Qn=Z n /W Rn=Z n %W Here, Quotient indicates that these many scan chain can be equally distributed on TAM width W. Remainder indicates that these many scan chains are needed to be distributed separately. Now take the sum of the remainder R sum = http://www.iaeme.com/ijecet/index.asp 11 editor@iaeme.com

Harikrishna Parmar and Dr.Usha Mehta If R sum <W, Then Sum2(i)= + R(i) Now, distribute and add number of I/O to sum2(i) such that the balance wrapper scan chain is formed. Sum3(i) = + m/w Now find longest and shortest scan chain length Si max = max(sum3(i)) Where i varies from 1 to Sc Si min = min(sum3(i)) Where i varies from 1 to Sc If R sum >W, Then Now, distribute and add remainders and number of Inputs to sum2(i) such that the balance wrapper scan chain is generated. Sum3(i) = + m/w + R(i) Now find longest and shortest scan chain length Si max = max(sum3(i)) Where i varies from 1 to Sc Si min = min(sum3(i)) Where i varies from 1 to Sc Si max and Si min is the balance input wrapper scan chain Repeat this procedure for Balance output wrapper scan chain to find out So max and So min Test Time Calculation Calculate test application time of each core for width W 1 as per the equation given below and store it in array A A(i) = (1+max(Si max,so max ))*P + min(si min,so min ) Where i varies from 1 to N C Calculate test application time of each core for width W 1 as per the equation given below and store it in array B B(i) = (1+max(Si max,so max ))*P + min(si min,so min ) Where i varies from 1 to N C Test Scheduling Sort array A and array B in Descending order. Calculate cumulative test time of all cores from array A P1 = Calculate cumulative test time of all cores from array P2 = http://www.iaeme.com/ijecet/index.asp 12 editor@iaeme.com

An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application Time In Core Based SOC P=min(P1,P2) Take P as a upper bound for further procedure Now, add array A and B C(i)= + If number of cores is greater than 10 then distribute cores into number of segments. The first segment must contain 10 cores. The succeeding each segment may contain up to 10 cores. Here, the model is shown for 3 segments with assumption that there are 30 cores in a SoC. Store the test time for the first 10 core in an array X X1(k)=C(i) Where i and k varies from 1 to 10 X2(k)=C(i) Where i varies from 11 to 20 and k varies from 1to 10 X3(k)=C(i) Where i varies from 21 to 30 and k varies from 1to 10 Test scheduling for segment 1: Upper bound for test time is P H = P Lower bound of the test time is given as P L = Find the sum of the test time of the cores in array X1 for a given limit of upper and lower bound and store it in array D1. Find the sum of the test time of the cores in array X1a for a given limit of upper and lower bound and store it in array D2. Find the sum of the test time of the cores in array X1b for a given limit of upper and lower bound and store it in array D3. Find the length of D1. L1=length(D1) Find maximum from array D1, D2 and D3 E H1 = max(d1) E H2 = max(d2) E H3 = max(d3) Test scheduling for segment 2: Upper bound = E H1 Lower bound = E L = Where i varies from 21to 30 Find the sum of the test time of the cores in array X2 for a given limit of upper and lower bound and store it in array F1. Find the sum of the test time of the cores in array X2a for a given limit of upper and lower bound and store it in array F2. http://www.iaeme.com/ijecet/index.asp 13 editor@iaeme.com

Harikrishna Parmar and Dr.Usha Mehta Find the sum of the test time of the cores in array X2b for a given limit of upper and lower bound and store it in array F3. Find the length of F1. L1=length(F1) Test scheduling for segment 3: Initialize a variable k1=1 Upper bound = F1(i) Where i varies from 1to L2 Lower bound = E L = C(Nc) Find the sum of the test time of the cores in array X3 for a given limit of upper and lower bound and store it in array G1(k1) and update array for every iteration from i =1 to L2. Also update k1. Find the sum of the test time of the cores in array X3a for a given limit of upper and lower bound and store it in array G2(k1) and update array for every iteration from i =1 tol2. Also update k1. Find the sum of the test time of the cores in array X3b for a given limit of upper and lower bound and store it in array G3(k1) and update array for every iteration from i =1 tol2. Also update k1. Find the length of G1 and update the values of last array. L3=length(G1) H1(j)= H2(j)= H3(j)= Update j and H1,H2,H3 for every iteration. Now, take P, E H2 and E H3 from segment 1 J1(i) = ) J2(i)=P- Find maximum from two array J1 and J2 J(i)= max(j1(i),j2(i)) Where i varies from 1 to L3 Find Minimum value fro array J Q=min(J(i)) Where i varies from 1 to L3 Find Minimum value fro array J Q=min(J(i)) Where i varies from 1 to L3 Q is the final answer 5. EXPERIMENTAL RESULT ANALYSIS Here SoC d695 and P93791 is taken as a running example throughout this paper to understand the fundamental of test optimization methodology. Here the experimental results are shown in table I, II and III when TAM bus width is partitioned by 2. Also, the proposed method is compared with the reference http://www.iaeme.com/ijecet/index.asp 14 editor@iaeme.com

An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application Time In Core Based SOC approach [18] and [19] which shows the optimality of the proposed method. Simulation results achieved in this paper are done in MATLAB. 6. CONCLUSION In this paper, an improved algorithm for the test bus architecture is presented and the simulation is done on SoC d695 and P93791. Through extensive simulation on given SoC, it is observed that with the proposed algorithm, the testing time is reduced significantly as compared to the approach given in the reference. It has also been noticed that the achieved TAM bus width distribution and core assignment is an optimum value for the testing time earned with the proposed algorithm. Total TAM Width Table I Simulation results for SoC D695 Optimal Width Distribution From ref paper [18] From proposed algo Difference 16 (7,9) 45055 44116 939 20 (4,16) 34444 34437 7 24 (5,19) 29501 29240 261 28 (8,20) 26964 26828 136 32 (12,20) 25442 24779 663 36 (16,20) 25312 23193 2119 40 (8,32) 21359 21314 45 44 (9,35) 20883 20232 651 48 (10,38) 19938 19707 231 52 (18,34) 19087 18783 304 56 (20,36) 18434 18130 304 60 (20,40) 18205 18019 186 64 (20,44) 18205 17946 259 Total TAM Width Table II Simulation results for SoC P93791 (Comparision with ref paper [18]) Optimal Width Distribution From ref paper[18] From proposed algo Difference 16 (8,8) 1806550 1683418 123132 20 (8,12) 1453170 1356828 96342 24 (12,12) 1217630 962058 255572 28 (5,23) 1031200 868112 163088 32 (9,23) 899807 867746 32061 36 (12,24) 820232 781852 38380 40 (16,24) 751345 707549 43796 44 (17,27) 711256 694132 17124 48 (23,25) 634488 589031 45457 52 (6,46) 600218 534109 66109 56 (9,47) 533752 505877 27875 60 (13,47) 505885 483857 22028 64 (16,48) 475598 464905 10693 http://www.iaeme.com/ijecet/index.asp 15 editor@iaeme.com

Harikrishna Parmar and Dr.Usha Mehta Table III Simulation results for SoC P93791 (Comparision with ref paper [19]) Total TAM Width Optimal Width Distribution From ref paper[19] From proposed algo Difference 16 (8,8) 1854566 1683418 171148 24 (12,12) 1272220 1134381 137839 32 (9,23) 940318 868112 72206 40 (16,24) 765715 706617 59098 48 (23,25) 640488 587775 52713 56 (9,47) 551849 494999 56850 64 (16,48) 473726 449967 23759 REFERENCES [1] Y. Zorian, E. Marinissen, and S. Dey, Testing embedded-core-based system chips, Computer, vol. 32, no. 6, pp. 52 60, 1999. [2] J. Marinissen, Y. Zorian, R. Kapur, T. Taylor and T. Whetsel, Towards a standard for embedded core test: an example, Proceeding of the International Test conference, pp.616~627, 1999. [3] K. Chakrabarty, Optimal test access architectures for system-on-chip, ACM Transactions on Design Automation of Electronic System, Vol.6, no.1. January 2001, pp. 26~49 [4] V Iyengar, K. Chakrabarty, and E Marinissen, Test wrapper and test access mechanism co-optimization for system-on-chip, Journal of Electronic Testing: Theory and Applications, vol. 18, pp. 213 230, 2002. [5] N. Nicolici and Xu, Resource-constrained system-on-a-chip test: a survey, IEE Proc. Computers and Digital Techniques, vol.152, no. 1, pp. 67 81, 2005. [6] Z. Peng, E. Larsson, K. Arvidsson and H. Fujiwara, Efficient test solutions for core-based designs, TCAD, vol.23,no.5,pp.758 775, 2004. [7] S Goel and E Marinissen, Effective and Efficient Test Architecture Design for SOCs, In Proceedings IEE(ITC), pages 529 538, Baltimore, MD, Oct. 2002. [8] S Bhatia and P Varma, A Structured Test Reuse Methodology for Core-based System Chips, In Proc. ITC pages 294 302, 1998. [9] J. Marinissen, A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, In Proceedings IEEE International Test Conference (ITC), pages 284 293, Oct. 1998. [10] W. Huang, Y Wang, Optimizing Test Access Mechanism Under Constraints by Genetic Local Search Algorithm, Proc. ATS, 2003. [11] N. Nicolici,Q. Xu, Multi-frequency Test Access Mechanism design for Modular SOC Testing, In Proceedings 13th ATS, pp. 2-7, Nov. 2004. [12] X Liu, Q Xu, On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation, Proceeding IEEE Asian Test Symposium, pp-303-308, 2008 [13] F Jianhua, L Jieyi, X Wenhua and Y Hongfei, An Improved Test Access Mechanism Structure and Optimization technique in System-on-Chip, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, Pages 23-24,2005 http://www.iaeme.com/ijecet/index.asp 16 editor@iaeme.com

An Efficient Algorithm For Wrapper and Tam Co-Optimization To Reduce Test Application Time In Core Based SOC [14] G. Giles, J. Wang, A. Sehgal, K. Balakrishnan, and J. Wingfield, Test access mechanism for multiple identical cores, in Proc. IEEE Int. Test Conf., Oct. 2008, pp. 1 10. [15] A Han, I Choi, and S Kang, Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores, IEEE transaction on VLSI Ssystems, pp-1, 2014 [16] H Ke, D Zhongliang, H Jianming, Boundary Scan with Parallel Test Access Mechanism, The Ninth International Conference on Electronic Measurement & Instruments, pp 16-19,2009 [17] J Rau, P Wu, W Huang, C Chien and C Chen, Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs, Tamkang Journal of Science and Engineering, Vol. 13, No. 3, pp. 305_314, 2010 [18] K Chakrabarty V. Iyengar, A. Chandra, Test resource partitioning for systemon-a-chip. Frontiers in Electronic Testing, Vol. 20, 2002. [19] S Goel, J Marinissen, A Sehgal and K Chakravarti Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling IEEE Transactions On Computers, Vol. 58, No. 3, March 2009 http://www.iaeme.com/ijecet/index.asp 17 editor@iaeme.com