Closing the Loop in High-Frequency Amplifier Design Processes

1 Session E 220 Closing the Loop in High-Frequency Amplifier Design Processes Andrew Rusek and Barbara Oakley Department of Electrical and Systems Engineering Oakland University, Rochester, MI 48309 Email: rusek@oakland.edu Abstract Unexpected and intractable problems can arise in the verification of high-frequency amplifier performance through simulation. This paper presents a simple method of conducting and interpreting amplifier simulation testing processes using a simulated PSpice network analyzer, coupled with Serenade SV software. The circuits and processes discussed here were developed using free software packages, and can be profitably used in any course involving high frequency electronic design. I. Introduction Oakland University has been involved in teaching and developing a high frequency electronics course (EE 626) for a number of years. 1,2,3,4 Amplifier design, an important aspect of this course, often entails the use of a network analyzer to obtain s-parameters for transistors to be used in the final circuit. Network analyzers are expensive devices, so for purposes of classroom and experimental use, we have developed a simulated network analyzer using PSpice 5.6, 7, 8 to extract the s-parameters from a given transistor These parameters can in turn be supplied to Serenade SV software 9 to finalize the amplifier design. In this paper, we discuss the processes of design and verification of an amplifier designed to operate at 500 MHz using circuit models developed using PSpice and Serenade. The main points of the design cycle are as follows. The last step leads, in many cases, to final circuit adjustments. II. Amplifier Design 1. Scattering matrix parameter extraction from PSpice transistor model. 2. Parameter transfer to Serenade and subsequent stability testing. 3. Matching network design. 4. Amplifier parameter verification. Fig. 1 illustrates a PSPICE schematic of a simulated network analyzer circuit serving as an s-parameter extractor for a transistor chosen for this example to be an MRF501. The PSpice model of this transistor is described in terms of Gummel-Poon nonlinear parameters. The internal structure of the Fig. 1 modules HB6 (replicated as HB7) and HB2 (replicated as

2 HB3) are shown in Figs. 2 and 3. S-parameters as a function of frequency for selected DC operating conditions are shown in Figure 4. After extraction using the network analyzer simulation, the s-parameters were transferred to Serenade to test transistor stability. Table 1 shows the list of s-parameters used as the Serenade data entry for the transistor MRF501. During the first steps of the design process, the stability of the transistor was checked at the frequency of interest, 500 MHz. The circuit used for this step is shown in Fig. 5. Since the transistor appears to be stable for all loads within the Smith chart, it is possible to design the amplifier for any value of gain between 0 db and 16.07 db. Fig. 6 shows two stability circles located outside the Smith chart area with the source circle on the left, and the load circle on the right. Several gain circles are plotted inside the Smith chart. The source (left) and the load (right) circles for 15 db and 16.06 db are shown. Serenade s Smith Tool, used to activate the calculations, establishes a stability factor K of Table 1: S-parameters obtained from PSpice Filename: EE626_MRF501.S2P Version: 2.0! OU part #: EE626TR FEB2002 Date: Feb 2002! Bias condition: Vce=12 V, Ic=5.0 ma! # MHz S MA R 50! Freq S11 S21 S12 S22!GUM [db] 100.747-83.0 10.29 134.5.0168 44.7.886-9.11! 300.682-138.7 4.630 106.2.0226 16.5.787-9.70! 500.670-154.5 2.880 97.30.0234 7.9.771-10.9! 800.666-163.8 1.79 90.70.0240 1.3.765-14.3! III. Design Verification with PSpice and Serenade 1.69, and maximum gain, GMAX, of 16.07 db. Further processes illustrated in Figs. 7 and 8 lead to the design of the input and output matching networks, composed of L and C elements. The conjugate network matching process is applied here. Figs. 9 and 10 show the structures of the networks generated with the aid of Serenade. The results of the design described above require final verification as well as possible corrections. The first criterion to be checked is the quality of the conjugate matching the amplifier should not produce any visible mismatch related to output and input networks. Applying the s-parameter simulated network analyzer the same one used previously to determine transistor parameters can effectively test these qualities (Fig. 11). This time, s11 and s22 are the input and output reflection coefficients for the amplifier under design (Figs. 12, 13, 14). Very low values for these parameters should be observed at 500 MHz. The power gain can be verified by plotting the s21 parameter. The power gain can then be simply expressed as s21 2, rather than as a complex function of transistor parameters (Fig. 15). IV. Conclusions Free PSpice software such as that available from Cadence, along with the free student version of Serenade from Ansoft, can be very effective educational tools for teaching high frequency electronic courses, especially in the areas related to high frequency amplifier design. These software packages can help extract transistor s-parameters, can aid in the determination of the values of amplifier components, and can also be used to verify circuit parameters. Additionally, a combination of both software packages allows linking two different classes of transistor models such that a complete amplifier design can be easily achieved and verified.

3 Figure 1: Simulated circuit design of overall system that uses S-parameter extraction circuits to detect phase shifts in the associated cables. Figure 2: Illustration of the internal structures of modules HB6 and HB7 shown in the previous figure. This circuit is used to evaluate s11 and s22.

4 Figure 3: Internal structure of blocks HB2 and HB3 of Fig. 1. This circuit is used to evaluate s21 and s12. Figure 4: S parameters for transistor MRF501 versus frequency (magnitudes and phases).

5 Figure 5: The circuit to evaluate transistor stability and to start designing amplifier using Serenade. Figure 6: Serenade results using the parameters obtained from the circuit of Fig. 1 applied to verify amplifier performance. The Smith Chart shows results of a stability check (the internal areas of the circles outside the Smith chart show instability regions) as well as the source and load power gain circles (the green circles on the left and right, respectively, inside the Smith chart). The blue line on the left inside the Smith chart is s11, while s22 is the red line inside the Smith chart on the right). Points inside the load and source circles are also load and source circles with r = 0 for conditions approximating maximum power gain.

Figure 7: Design of the source-matching network using the Smith Tool from Serenade. 6

7 Figure 8: Design of the load-matching network using the Smith Tool from Serenade. Figure 9: Designed matching circuit for the source side

8 Figure 10: Designed matching circuit for the load side Figure 11: Circuit as in Fig 1 applied to verify amplifier performance.

9 Figure 12: Amplifier parameters. The top illustration shows the input and output reflection coefficients as a function of frequency, the middle shows the gain, and the bottom shows the reverse voltage transfer, which is about 50 mv at the frequency of interest. Figure 13: Serenade circuit applied to verify amplifier performance.

10 Figure 14: Input and output reflection coefficients. Figure 15: Gain of the amplifier, the square of which is equal to the power gain.

11 Bibliography 1 Andrew Rusek and Barbara Oakley, PSpice Applications in the Teaching of Communications Electronics, Proceedings of the 2001 American Society for Engineering Education Annual Conference & Exposition, (CDROM), Albuquerque, NM. 2 Andrew Rusek and Barbara Oakley, PSpice Applications in the Teaching of Wireless and High Frequency Electronics, Proceedings of the 2001 American Society for Engineering Education Annual Conference & Exposition, (CDROM), Albuquerque, NM. (Nominated for best paper.) 3 Andrew Rusek and Barbara Oakley, Demonstrating CDMA, Frequency Hopping, and Other Wireless Techniques with PSPICE, to be published in the Proceedings of the 2002 American Society for Engineering Education Annual Conference & Exposition, Montreal, Canada. 4 Andrew Rusek and Barbara Oakley, Software Tools for Teaching High Frequency Electronics Courses, Second IEEE EIT Conference Proceedings, Oakland University, Rochester, MI, June 2001 5 The edition used is that produced by Cadence Design Systems, 2655 Seely Avenue San Jose, CA 95134. A downloadable student version is available at http://pcb.cadence.com/product/simulation/pspice/eval.asp. 6 D. Ballo, Network Analyzer Basics, HP 1997, Back to Basics Seminar. 7 S-Parameter Design, HP Application Note 154. 8 Obtain S-Parameter Data from Probe, Application Notes Manual, Microsim Corporation, 1994. 9 Serenade SV is produced by Ansoft Corporation, Four Station Square, Suite 200, Pittsburgh, PA 15219-1119. It is a free, feature-limited version of Ansoft's commercially distributed Serenade 8.5, and is available for download at http://www.ansoft.com/about/academics/sersv/index.cfm ANDREW RUSEK Andrew Rusek is a Professor of Engineering at Oakland University in Rochester, Michigan. He received an M.S. in Electrical Engineering from Warsaw Technical University in 1962, and a PhD. in Electrical Engineering from the same university in 1972. His post-doctoral research involved sampling oscillography, and was completed at Aston University in Birmingham, England, in 1973-74. Dr. Rusek is very actively involved in the automotive industry with research in communication systems, high frequency electronics, and electromagnetic compatibility. He is the recipient of the 1995-96 Oakland University Teaching Excellence Award. BARBARA OAKLEY Barbara Oakley is an Assistant Professor of Engineering at Oakland University in Rochester, Michigan. She received her B.A. in Slavic Languages and Literature, as well as a B.S. in Electrical Engineering, from the University of Washington in Seattle. Her M.S. in Electrical and Computer Engineering was received from Oakland University in 1995, and her Ph.D. in Systems Engineering, also from Oakland, was received in 1998. Her research involves biomedical applications and electromagnetic compatibility. She is a recipient of the NSF FIE New Faculty Fellow Award, was designated an NSF New Century Scholar, and has received the John D. and Dortha J. Withrow Teaching Award.