LT6 High Speed, Quad niversal Filter Building Block FETRES High Speed, p to 5kHz enter Frequency Four Identical Filters in a." Wide Package lock-to-enter Frequency Ratio of : Double-Sampling, Improved liasing Operates from ±.7V to ±8V Power Supplies ustomized Version with Internal Resistors vailable Low Noise Low Harmonic Distortion vailable in -Pin DIP and SO Wide Packages PPLITIO S Digital ommunications Spread Spectrum ommunications Spectral nalysis Loran Receivers Instrumentation, LT and LT are registered trademarks of Linear Technology orporation. ll other trademarks are the property of their respective owners. DESRIPTIO The LT 6 consists of four identical, high speed nd order switched-capacitor filter building blocks designed for center frequencies up to 5kHz. Each building block, together with three to five resistors, can provide nd order functions like lowpass, highpass, bandpass and notch. The center frequency of each nd order section is tuned via an external clock. The clock-to-center frequency ratio is internally set to :, but it can be modified via external resistors. The aliasing performance of the LT6 is improved by double-sampling each nd order section. Input signal frequencies can reach up to twice the clock frequency before any alias products will be detectable. For Q 5 and for T < 85, the maximum center frequency is 6kHz. For Q, the maximum center frequency is 5kHz. p to 8th order filters can be realized by cascading all four nd order sections. customized monolithic version of the LT6 including internal thin film resistors can be obtained. TYPIL PPLITIO lock-tunable 8th Order Bandpass Filter, f ENTER = f LK / IN 5k k 5k 5k INV B INV HPB/NB HP/N BPB BP k 5k Gain vs Frequency khz Bandpass, f db Bandwidth = f ENTER / MXIMM f ENTER 6kHz khz 6kHz POWER SPPLY ±7.5V ±5V Single 5V.µF LPB SB LT6 V S LP S V LK SD f LK.µF GIN (db) 5 5k k LP BP HP/N INV LPD BPD HPD/ND INV D 5k k OT 6 7 8 k k FREQENY (Hz) M 5k 5k 6 T 6 T 6fb
LT6 BSOLTE XI RTI GS (Note ) W W W Total Supply Voltage (V to V )... 6V Input Voltage (Note )... (V.V) to (V.V) Output Short-ircuit Duration... Indefinite Power Dissipation... mw Burn-In Voltage... 6V Operating Temperature Range... to 85 Storage Temperature Range... 65 to 5 Lead Temperature (Soldering, sec)... PKGE/ORDER I FOR INV B HPB/NB BPB LPB SB 5 6 V 7 S 8 LP 9 BP HP/N INV TOP VIEW INV HP/N BP LP S 9 V 8 LK 7 SD 6 LPD 5 BPD HPD/ND INV D W TIO ORDER PRT NMBER LT6N LT6SW ELETRIL HRTERISTIS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 5.(Internal Op mps) T = 5, unless otherwise noted. PRMETER ONDITIONS MIN TYP MX NITS Operating Supply Range ±.75 ±8 V Voltage Swings V S = ±.75V, = 5k ±.5 V V S = ±5V, = 5k ±. ±.7 V ±. V V S = ±7.5, = 5k ±6 V Output Short-ircuit urrent (Source/Sink) m D Open-Loop Gain 8 db GBW Product 7 MHz Slew Rate V/µs (omplete Filter) V S = ±5V, f LK = MHz, all sides mode, f O = 5kHz, Q = 5, T = 5, unless otherwise noted. PRMETER ONDITIONS MIN TYP MX NITS enter Frequency Range, f O (Note ), T < 85, Q <. - 5 khz V S = ±5V, T < 85, Q <. - khz V S = ±.5V, T < 85, Q <. - khz lock-to-enter Frequency Ratio, f LK /f O : enter Frequency Error (Note ) ±. ±.7 % ±.8 % V S = ±5V ±. ±.8 % ±. % V S = ±.75V.6 % lock-to-enter Frequency Ratio, V S ±5V..8 % Side-to-Side Matching. % Q ccuracy V S = ±5V.7 % 7. % f O Temperature oefficient f LK < MHz ± ppm/ Q Temperature oefficient f LK < MHz 5 ppm/ N PKGE SW PKGE -LED PLSTI DIP -LED PLSTI SO (WIDE) T JMX =, θ J = 65 /W (N) T JMX =, θ J = 85 /W (S) Order Options Tape and Reel: dd #TR Lead Free: dd #PBF Lead Free Tape and Reel: dd #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ onsult LT Marketing for parts specified with wider operating temperature ranges. 6fb
ELETRIL HRTERISTIS LT6 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 5. (omplete Filter) V S = ±5V, f LK = MHz, all sides mode, f O = 5kHz, Q = 5, unless otherwise noted. PRMETER ONDITIONS MIN TYP MX NITS D Offset Voltage (Note ) V OS (D Offset of Input Inverter) ± mv V OS (D Offset of First Integrator) ±5 mv V OS (D Offset of Second Integrator) ±5 mv lock Feedthrough (f LK is a Square Wave) 6 µv RMS V S = ±5V (f LK is a Square Wave) µv RMS V S = ±.75V (f LK is a Square Wave) 9 µv RMS Maximum lock Frequency, T = 5 6 MHz Power Supply urrent V S = ±5V 9 m 6 m Note : bsolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : Please refer to Typical Maximum Q vs lock Frequency graphs. Note : alculations of output D offsets of one nd order section. lso see Block Diagram. Note : The center frequency f O, error is calculated as: f O (measured) f O (ideal) f O (ideal) V OSN V OSBP V OSLP MODE PINS,,, PINS,, 5, PINS, 9, 6, V OS [(Q) H OLP ] V OS /Q V OS V OSN V OS b V OS [(/Q) /] V OS /Q V OS (V OSN V OS )( R5/R6) [V OS ( / / /) V OS (/)] V OS V OSN V OS [/( )] V OS [/( )] V OS V OS V OS [ / / /] V OS (/) V OS (/) TYPIL PERFOR W E HRTERISTIS TYPIL MXIMM Q Typical Maximum Q vs lock Frequency 6 8 6 B 8 6.5 T 85. MODES, b B. MODES, a..5..5..5 5. LOK FREQENY (MHz) 6 G TYPIL MXIMM Q Typical Maximum Q vs lock Frequency 6 8 6 B 8 6. V S = ±5V T 85. MODES, b B. MODES, a.5..5..5. LOK FREQENY (MHz) 6 G TYPIL MXIMM Q 8 6 8 6 Typical Maximum Q vs lock Frequency. B V S = SINGLE 5V T 85. MODES, b B. MODES, a...6.8. LOK FREQENY (MHz) 6 G 6fb
LT6 TYPIL PERFOR W E HRTERISTIS TYPIL BNDPSS GIN ERROR (db) 5 Typical Bandpass Gain Error vs lock Frequency MODE Q = T = 5 V S = ±5V TYPIL BNDPSS GIN ERROR (db) 5 Typical Bandpass Gain Error vs lock Frequency MODE Q = T = 5 V S = ±5V TYPIL BNDPSS GIN ERROR (db) 5 Typical Bandpass Gain Error vs lock Frequency MODE V S = SINGLE 5V T = 5 Q = Q =...8..6. LOK FREQENY (MHz) 6 G...8..6. LOK FREQENY (MHz) 6 G5..,5.6.7.8 LOK FREQENY (MHz).9. 6 G6 TYPIL BNDPSS GIN ERROR (db) 5 Typical Bandpass Gain Error vs lock Frequency MODE Q = T = 5 V S = SINGLE 5V V S = ±5V f LK /f O.5..... 9.9 9.8 9.7 9.6 Ratio (f LK /f O ) vs lock Frequency BNDPSS OT MODE Q = Q = Q = LOK FREQENY (MHz) 9.5 LOK FREQENY (MHz) 6 G5 6 G NOISE (µv RMS ) 6 5 Noise vs / Ratio MODE Q = flk fo =...6.8 RESISTOR RTIO (/) 6 G. POWER SPPLY RRENT (m) Power Supply urrent vs Supply Voltage 8 6 8 55 5 6 5 8 6 8 6 8 POWER SPPLY VOLTGE (V V ) 6 G 6fb
LT6 PI F TIO S V, V (Pins 7, 9): Power Supply Pins. The V (Pin 7) and the V (Pin 9) should each be bypassed with a.µf capacitor to an adequate analog ground. The filter s power supplies should be isolated from other digital or high voltage analog supplies. low noise linear supply is recommended. sing a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than V/µs. When V is applied before V and V is allowed to go above ground, a diode should clamp V to prevent latch-up. Figures and show typical connections for dual and single supply operation. (Pin 6): nalog Ground Pin. The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, Pin 6 should be connected to the analog ground plane. For single supply operation, Pin 6 should be biased at / supply and should be bypassed to the analog ground plane with at least a µf capacitor (Figure ). For single 5V operation and f LK greater than MHz, pin 6 should be biased at V. This minimizes passband gain and phase variations. NLOG GROND PLNE 5 6 9 7.5V *.µf NLOG GROND PLNE V 5k *5 V / 6 * 9 7.5V.µF 7 8 9 LT6 8 7 6 µf 5k V 7 *8 9 LT6 8 7* 6 5 5 STR SYSTEM GROND DIGITL GROND PLNE Ω LOK SORE STR SYSTEM GROND DIGITL GROND PLNE Ω LOK SORE * OPTIONL, N8, N589 6 F * FOR MODE, THE S NODE PINS 5, 8, 7, SHOLD BE TIED TO PIN 6 6 F Figure. Dual Supply Ground Plane onnections Figure. Single Supply Ground Plane onnections 6fb 5
LT6 PI F TIO S LK (Pin 8): lock Input Pin. ny TTL or MOS clock source with a square wave output and 5% duty cycle (±%) is an adequate clock source for the device. The power supply for the clock source should not be the filter s power supply. The analog ground for the filter should be connected to clock s ground at a single point only. Table shows the clock s low and high level threshold values for a dual or single supply operation. Table. lock Source High and Low Threshold Levels POWER SPPLY HIGH LEVEL LOW LEVEL Dual Supply = ±7.5V.8V.5V Dual Supply = ±5V.5V.5V Dual Supply = ±.5V.7V.V Single Supply = V 7.8V 6.5V Single Supply = 5V.5V.5V pulse generator can be used as a clock source provided the high level on-time is greater than.µs. Sine waves are not recommended for clock input frequencies less than khz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time µs). The clock signal should be routed from the right side of the I package and perpendicular to it to avoid coupling to any input or output analog signal path. Ω resistor between clock source and Pin will slow down the rise and fall times of the clock to further reduce charge coupling (Figures and ). HPB/NB, BPB, LPB, LP, BP, HP, HPD, BPD, LPD, LP, BP, HP/N (Pins,,, 9,,,, 5, 6,,, ): Output Pins. Each nd order section of the LT6 has three outputs which typically source m and sink m. Driving coaxial cables or resistive loads less than k will degrade the total harmonic distortion performance of any filter design. When evaluating the distortion or noise performance of a particular filter design implemented with an LT6, the final output of the filter should be buffered with a wideband noninverting high slew rate amplifier (Figure ). 5k LT 6 F Figure. Wideband Buffer INV B, INV, INV D, INV (Pins,,, ): Inverting Input Pins. These pins are the high impedance inverting inputs of internal op amps and they are susceptible to stray capacitive connections to low impedance signal outputs and power supply lines. SB, S, SD, S (Pins 5, 8, 7, ): Summing Input Pins. The summing pins connections determine the circuit topology (mode) of each nd order section. Please refer to Modes of Operation. W ODES OF OPERTIO For the definition of filter functions please refer to the LT6 data sheet. Mode In Mode, the ratio of the external clock frequency to the center frequency of each nd order section is internally fixed at :. Figure illustrates Mode providing nd order notch, lowpass, and bandpass outputs. Mode can be used to make high order Butterworth lowpass filters; it can also be used to make low Q notches and for cascading nd order bandpass functions tuned at the same center frequency. Mode is faster than Mode. 6 Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. Mode b Mode b is derived from Mode. In Mode b (Figure 5) two additional resistors R5 and R6 are added to alternate the amount of voltage fed back from the lowpass output into the input of the S (SB, S or SD) switched-capacitor summer. This allows the filter s clock-to-center frequency ratio to be adjusted beyond :. Mode b maintains the speed advantages of Mode and should be considered an 6fb
LT6 W ODES OF OPERTIO optimum mode for high Q designs with f LK to f TOFF (or f ENTER ) ratios greater than :. Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. V IN f i = N S BP LP f LK Σ / LT6 ; f O = f i ; f n = f O Q = ; H ON = ; H OBP = H OLP = H ON Figure. Mode, nd Order Filter Providing Notch, Bandpass and Lowpass Outputs R6 R5 6 F Mode In Mode, the ratio of the external clock frequency to the center frequency of each nd order section can be adjusted above or below :. Figure 6 illustrates Mode, the classical state variable configuration, providing highpass, bandpass, and lowpass nd order filter functions. Mode is slower than Mode. Mode can be used to make high order all-pole bandpass, lowpass, and highpass filters. Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. Mode Mode is a combination of Mode and Mode, shown in Figure 7. With Mode, the clock-to-center frequency ratio, f LK /f O, is always less than :. The advantage of Mode is that it provides less sensitivity to resistor tolerances than does Mode. s in Mode, Mode has a notch output which depends on the clock frequency, and the notch frequency is therefore less than the center frequency, f O. Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. V IN N S BP LP Σ / LT6 NOTE: R5 5k f f i = LK ; f O = f i ; f n = f R6 (R6 R5) O Q = ; H ON = ; H OBP = R6 (R6 R5) R6 R5 H OLP = R6 6 F5 Figure 5. Mode b, nd Order Filter Providing Notch, Bandpass and Lowpass Outputs V IN HP S BP LP / LT6 Σ 6 F6 f LK f i = ; f O = f i ; Q =.5 ( 6. ) H OHP = ; H OBP = ; H OLP = 6. Figure 6. Mode, nd Order Section Providing Highpass, Bandpass and Lowpass Outputs 6fb 7
LT6 W ODES OF OPERTIO V IN N S BP LP Σ / LT6 f LK f i = ; f O = f i ; f n = f O Q =.5 6. H OHP = ( GIN, f > f n ); H OHPn = H OBP = ( 6. ) ; H OLP = H OHPn 6 F7 (D GIN, f < f n) Figure 7. Mode, nd Order Filter Providing Highpass Notch, Bandpass and Lowpass Outputs Mode a This is an extension of Mode where the highpass and lowpass output are summed through two external resis- tors and to create a notch. This is shown in Figure 8. Mode a is more versatile than Mode because the notch frequency can be higher or lower than the center frequency of the nd order section. The external op amp of Figure 8 is not always required. When cascading the sections of the LT6, the highpass and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. Mode n This mode extends the circuit topology of Mode a to Mode (Figure 9) where the highpass notch and lowpass outputs are summed through two external resistors and to create a lowpass output with a notch higher in frequency than the notch in Mode. This mode, shown in Figure 8, is most useful in lowpass elliptic designs. When cascading the sections of the LT6, the highpass notch and lowpass outputs can be summed directly into the inverting input of the next section. Please refer to the Maximum Frequency of Operation paragraph under pplications Information for a guide to the use of capacitor. V IN HP S BP LP Σ / LT6 R G f f i = LK ; f n = f i ; f O = f i Q =.5 ( 6. ) R H G OHPn (f = ) = ; H OLPn (f = ) = HIGHPSS OOWPSS NOTH OTPT R G EXTERNL OP MP OR INPT OP MP OF THE LT6, SIDES, B,, D 6 G8 Figure 8. Mode a, nd Order Filter Providing a Highpass Notch or Lowpass Notch Output 8 6fb
LT6 W ODES OF OPERTIO V IN HP S BP LP Σ / LT6 R G f f i = LK ; f n = f R i H f O = f i R R H OLPn (f = )= G G ( )( ) ( ) Q =.5 6. LOWPSS NOTH OTPT EXTERNL OP MP OR INPT OP MP OF THE LT6, SIDES, B,, D 6 G9 Figure 9. Mode n, nd Order Filter Providing a Lowpass Notch Output BLOK DGR I W INV 6 HP/N BP LP 9 7 Σ 8 9 V LK V INV B 8 HPB/NB BPB LPB S Σ INV 5 HP/N SB BP LP Σ INV D HPD/ND S Σ BPD LPD 5 6 7 SD 6 BD 6fb 9
LT6 PPLITI O S I FOR W TIO Operating Limits The Typical Maximum Q vs lock Frequency and Bandpass Gain Error graphs, under Typical Performance haracteristics, define an upper limit of operating Q for each LT6 nd order section. These graphs indicate the power supply, f LK and Q value conditions under which a filter implemented with an LT6 will remain stable when operated at temperatures of 85 or less. For a nd order section, a bandpass gain error of db or less is arbitrarily defined as a condition for stability. When the passband gain error begins to exceed db, the use of capacitor will reduce the gain error (capacitor is connected from the lowpass node to the inverting node of a nd order section). Please refer to Figures through 9. The value of can be best determined experimentally, and as a guide it should be about 5pF for each db of gain error and not to exceed 5pF. When operating LT6 very near the limits defined by the Typical Performance haracteristics graphs, passband gain variations of db or more should be expected. Speed Limitations To avoid op amp slew rate limiting, the signal amplitude should be kept below a specified level as shown in Table. Table. Maximum V IN vs V S and lock V S MXIMM LOK MXIMM V IN ±7.5V MHz to 5MHz.5V RMS f IN khz ±5V MHz to MHz.5V RMS f IN 5kHz Single 5V MHz to MHz.5V RMS f IN 6kHz lock Feedthrough lock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter s output pins. The clock feedthrough is tested with the filter s input grounded and it depends on P board layout and on the value of the power supplies. With proper layout techniques, the typical values of clock feedthrough are listed under Electrical haracteristics. ny parasitic switching transients during the rise and fall edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough, if bothersome, can be greatly reduced by adding a simple R lowpass network at the final filter output. This R will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device s noise spectral density and it is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter passband and it cannot be reduced with post filtering. The total wideband noise (µv RMS ) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. For a specific filter design, the total noise depends on the Q of each section and the cascade sequence. Table shows typical nd order section noise (gain = ) for Q values and supplies operating at 5. Noise increases by % at the highest operating temperatures. Table. nd Order Section Noise (µv RMS ) for Modes, b, or ( = ) Q V S = ±.5V V S = ±5V µv RMS 5 6 5µV RMS 6 75 6µV RMS 75 95 75µV RMS 9 5 5 9µV RMS 5 liasing liasing is an inherent phenomenon of switched-capacitor filters and it occurs when the frequency of input signals approaches the sampling frequency. The input signals that produce the strongest aliased components have a frequency, f IN, such as (f SMPLING f IN ) falls into the filter s passband. For the LT6 the sampling frequency is twice f LK. If the input signal spectrum is not band-limited, aliasing may occur. 6fb
LT6 PPLITI O S I FOR W TIO For example, for an LT6 bandpass filter with f ENTER = khz and f LK = MHz, a.9mhz, mv input will produce a khz, mv output. st or nd order prefilter will reduce aliasing to acceptable levels in most cases. GIDE TO BNDPSS DESIGN Filter design tools like FD require design specification inputs such as passband ripple, attenuation, passband width and stopband width in order to calculate filter parameters f O, Q, f n or poles and zeroes. The results of these filter approximations most often require Q values which make excessive demands on the gain-bandwidth products of active filter realizations. The active filter designer should define a gain response so that the filter s mathematical approximation has practical requirements. Table is a guide to practical design specifications for realizing bandpass filters with LT6 (please also refer to the Typical Maximum Q vs lock Frequency and Bandpass Gain Error graphs under Typical Performance haracteristics). Table. Bandpass Design Specifications (f ENTER is center frequency of passband.) PSSBND PSSBND STOPBND TTEN- RIPPLE WIDTH WIDTH TION (db) (Hz) (Hz) (db) db for Butterworth f ENTER / 5 Passband to 6. for hebyshev f ENTER / 5 Passband to 6 Note: Reducing passband ripple or attenuation will decrease Q values. The filter order may also increase. Table 5. alculated Filter Parameters STGE f O Q 8.kHz.6.976kHz.6 5.68kHz.5.89kHz.5 Table 6. alculated Mode b Resistors to Nearest % Value sing Table 5 Filter Parameters and Figure Equations STGE R5 R6 5.k k 56.k 5k 6.98k 7.5k k 5.k 5k.8k 56.k k 7k 5k 5.k.k k 8k 5k.5k Bandpass Design Example Filter Type: Bandpass Filter Response: Butterworth Passband Ripple: db ttenuation: 6dB enter Frequency: khz (f ENTER ) Passband Width: khz Stopband Width: 6kHz Implementing the Bandpass Design With the LT6 in Mode b, Butterworth and hebyshev bandpass designs with f LK to f ENTER ratios greater than : are possible. First choose the clock frequency which in Mode b must be greater than times the bandpass center frequency of khz. For this example, let s choose f LK to be MHz. Table 6 lists the resistors for for the bandpass design example and Figure shows the complete circuit. = k R5 = 5k f f i = LK = (FOR BNDPSS) H OBP R5 f R6 = O ( f i f O ) H OBP = Q f O f ENTER f ENTER f O = Q R6 R6 5 6 F Figure. Equations for Resistors in Mode b Operation 6fb
LT6 PPLITI IN STGE STGE R5 R6 R6 R5 O S I FOR W INV B HPB/NB BPB LPB INV HP/N BP LP SB V S LP BP LT6 S V LK SD LPD BPD HP/N INV HPD/ND INV D TIO Figure. Mode b Bandpass Filter Figures and show the gain response graphs of the khz Butterworth bandpass design described above. The passband gain response graph (Figure ) shows a khz gain of.db and a tilted passband from 7kHz to khz. These errors are due to the % resistors used and the sideto-side matching of the LT6 f LK -to-f ENTER ratio which typically is.%. To adjust for db gain at khz, reduce the value of in the first stage by 5%. To adjust for a flat passband, adjust by ±% the value of R6 in stages and. djusting R6 compensates for the side-to-side matching errors. Please refer to Figure 5 equations defining f O and Q as a function of R6. The sequence of nd order stages and the bandpass gain H OBP of each stage will determine the gain peaks at the filter s intermediate outputs. given internal output can have several db more gain than the final filter output. Gain peaks occur around the corners of the passband. The gain peaks can be reduced by increasing the resistor of the f LK R5 R6 R6 R5 STGE STGE OT 6 F first stage and decreasing the resistor of the last stage by the same amount (multiplying the resistor of the first stage and dividing the resistor of the last stage by for narrowband filter, and by 5 for wideband filter is a good rule of thumb). This adjustment may, however, increase the filter s passband noise. GIN (db) GIN (db)..5.5..5..5..5 MODE b f LK = MHz f LK /f ENTER = 5:. 6 8 6 8 5 FREQENY (khz) 6 F Figure. Passband Gain vs Frequency khz Butterworth Bandpass 5 6 7 8 MODE b f LK = MHz f LK /f ENTER = 5: 9 8 6 5 58 66 7 8 9 FREQENY (khz) Figure. Gain vs Frequency khz Butterworth Bandpass 6 F 6fb
LT6 TYPIL PPLITI O S Linear Phase lock-tunable to khz, Dual th Order Lowpass Filter Gain vs Frequency IN 8V IN.µF INV B HPB/NB BPB LPB SB LT6 V S LP BP INV HP/N BP LP S V LK SD LPD BPD HP/N HPD/ND INV INV D f LK.µF OT 8V OT GIN (db) 5 6 7 8 k k FREQENY (Hz) 6 Tb M LT6 SIDE MODE B 7.8k 7.k 9.6k 5.k 5pF k 7.k k 75k 5pF 7.8k 7.k 9.6k 5.k 5pF D k 7.k k 75k 5pF f LK MHz MHz MHz 5MHz T 5 f db (V S = ±8V) 5kHz khz 75kHz khz 6 Ta lock-tunable, f ENTER = f LK /, khz, th Order Bandpass and Notch Filters Gain vs Frequency BNDPSS IN 7.5V NOTH IN.µF INV B HPB/NB BPB LPB SB LT6 V S LP BP INV HP/N BP LP S V LK SD LPD BPD HP/N HPD/ND INV INV D f LK MHz.µF BNDPSS OT 7.5V NOTH OT GIN (db) 5 6 7 8 k f LK = MHz k FREQENY (Hz) 6 T5b M LT6 SIDE MODE B k k k k k k k k k pf D k k k pf 6 T5a 6fb
LT6 TYPIL PPLITI O S khz, 8th Order Notch Filter, f LK /f ENTER = : Gain vs Frequency IN INV B HPB/NB BPB LPB INV HP/N BP LP GIN (db) 7.5V.µF SB LT6 V S LP BP S V LK SD LPD BPD HP/N HPD/ND INV INV D f LK MHz.µF 7.5V OT LT6 SIDE MODE B 6.5k k 5k.9k k 7.k pf 7.5k k 5k 5 6 7 8 k D 9.9k k 5k pf f LK = MHz k FREQENY (Hz) 6 T6b M 6 T6a lock-tunable, 8th Order Elliptic Lowpass Filter, f LK /f TOFF = : Gain vs Frequency IN 7.5V.µF INV B HPB/NB BPB LPB SB LT6 V S LP BP HP/N INV 6 Ta POWER SPPLY ±7.5V ±5V SINGLE 5V INV HP/N BP LP S V LK SD LPD BPD HPD/ND INV D.µF f LK MHz OT MXIMM f LK.6MHz ( = pf).mhz ( = pf).6mhz ( = pf) 7.5V LT6 SIDE MODE B a 7.k.7k k 8k 7k 7.k n k 7.k k k.6k pf GIN (db) n k 7.k k k.k pf 5 6 7 8 k D 9.k 9.k 8.7k k FREQENY (Hz) f LK = MHz 6 Tb M 6fb
LT6 PKGE DESRIPTIO N Package -Lead PDIP (Narrow. Inch) (Reference LT DWG # 5-8-5).8* (.5) MX 9 8 7 6 5.55 ±.5* (6.77 ±.8) 5 6 7 8 9..5 (7.6 8.55). ±.5 (. ±.7).5.65 (..65).8.5 (..8).5.5.5.889 ( 8.55.8) NOTE:. (.58) MIN. (.8) MIN INHES. DIMENSIONS RE MILLIMETERS *THESE DIMENSIONS DO NOT INLDE MOLD FLSH OR PROTRSIONS. MOLD FLSH OR PROTRSIONS SHLL NOT EXEED. INH (.5mm). (.5) BS.8 ±. (.57 ±.76) N 5.65 (.65) TYP SW Package -Lead Plastic Small Outline (Wide. Inch) (Reference LT DWG # 5-8-6). ±.5 TYP N.5 BS.5 ±.5.598.6 (5.9 5.6) NOTE 9 8 7 6 5 N. MIN.5 ±.5 NOTE.9.9 (.7.6) N/ N/ REOMMENDED SOLDER PD LYOT.5 (.7) RD MIN.9.99 (7.9 7.595) NOTE..9 5 (.5.77) 8 TYP.9. (.6.6) 5 6 7 8 9.7.5 (.9.).5.9. (.7) (.9.) NOTE BS..9.6.5 (.56.8) (.6.7) NOTE: TYP INHES. DIMENSIONS IN (MILLIMETERS). DRWING NOT TO SLE. PIN IDENT, NOTH ON TOP ND VITIES ON THE BOTTOM OF PKGES RE THE MNFTRING OPTIONS. THE PRT MY BE SPPLIED WITH OR WITHOT NY OF THE OPTIONS. THESE DIMENSIONS DO NOT INLDE MOLD FLSH OR PROTRSIONS. MOLD FLSH OR PROTRSIONS SHLL NOT EXEED.6" (.5mm) Information furnished by Linear Technology orporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology orporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights... (..5) S (WIDE) 5 6fb 5
LT6 TYPIL PPLITI O 8th Order Bandpass Filter, Linear Phase V IN 7.5V.µF INV B INV HPB/NB HP/N BPB BP LPB LP SB LT6 V S LP BP S V LK SD LPD BPD HP/N HPD/ND MHz 7.5V.µF LT6 SIDE MODE f LK MHz.5MHz.MHz B a 97.6k.7k 9.k.k.k 9.k.7k 5.6 5.k a.k.7k.k.5k pf 5pF pf D.k 9.k.k 7.k.k 6 T7a INV INV D V OT GIN (db) 5kHz Bandpass Filter, Linear Phase Gain vs Frequency 5 6 7 8 9 k k FREQENY (Hz) f LK = MHz 6 T7b M GIN (db) 6 9 5 8 7 Passband Gain and Group Delay GIN 9 8 DELY 7 6 5 6 8 5 5 5 56 58 6 FREQENY (khz) 6 T7c GROP DELY (µs) RELTED PRTS PRT NMBER DESRIPTION OMMENTS LT68 Very Low Noise, High ccuracy, Quad niversal Filter Four nd Order Filter Sections in 8-Pin SSOP, 56kHz Max enter Building Block Frequency, µv RMS Noise per nd Order Section, Operation.V to ±5V LT68-5 High Speed, High ccuracy, Quad niversal Four nd Order Filter Sections in 8-Pin SSOP, khz Max enter Filter Building Block Frequency, Operation.V to ±5V LT68-5 Low Power, High ccuracy, Quad niversal Four nd Order Filter Sections in 8-Pin SSOP, khz Max enter Filter Building Block Frequency,.5m at Single 5V, Operation.V to ±5V LT56 Very Low Noise, Low Distortion, ctive R Quad Four nd Order Filter Sections, No lock Required, 5kHz Max enter niversal Filter Frequency, SSOP 6 Linear Technology orporation 6 Mcarthy Blvd., Milpitas, 955-77 (8) -9 FX: (8) -57 www.linear.com 6fb LT/LT 85 REV B PRINTED IN S LINER TEHNOLOGY ORPORTION 99