LTC Bit Rail-to-Rail Micropower DAC in MSOP DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

Transcription

1 -Bit Rail-to-Rail Micropower DAC in MSOP FEATRES -Bit Resolution 8-Lead MSOP Package Buffered True Rail-to-Rail Voltage Output V or V Single Supply Operation Very Low Power: I CC(TYP) = 7µA Power-On Reset -Wire Cascadable Serial Interface is Compatible with SPI and MICROWIRE TM Maximum DNL Error: LSB Low Cost APPLICATIONS Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones DESCRIPTION The LTC 68 is a single supply, rail-to-rail voltage output, -bit digital-to-analog converter (DAC) in an 8-lead MSOP package. It includes an output buffer amplifier and an easy-to-use -wire cascadable serial interface. The LTC68 output swings from V to V REF. The REF pin can be tied to V CC for rail-to-rail output swing. The LTC68 operates from a single.7v to.v supply. The typical power supply current is 7µA. The low power supply current makes the LTC68 ideal for battery-powered applications. The space saving MSOP provides the smallest -bit DAC system available., LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. TYPICAL APPLICATION µp.7v TO.V CS/LD D OT Functional Block Diagram: -Bit Rail-to-Rail DAC 6-BIT SHIFT REG AND DAC LATCH V CC 8 6 -BIT DAC REF + V OT 7 RAIL-TO-RAIL VOLTAGE OTPT DNL ERROR (LSB) Differential Nonlinearity vs Input Code TO OTHER DACS POWER-ON RESET GND 68 TA CODE TA

2 ABSOLTE MAXIMM RATINGS W W W V CC to GND....V to 7.V TTL Input Voltage....V to 7.V V REF....V to 7.V V OT....V to (V CC +.V) Junction Temperature... 6 C to C (Note ) Operating Temperature Range Commercial... C to 7 C Industrial... C to 8 C Storage Temperature Range... 6 C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR CS/LD D OT TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP 8 V CC 7 V OT 6 REF GND T JMAX = C, θ JA = C/W Consult factory for Military grade parts. W ATIO ORDER PART NMBER LTC68CMS8 LTC68IMS8 MS8 PART MARKING LTCW LTFW CS/LD D OT N8 PACKAGE 8-LEAD PDIP TOP VIEW 8 V CC 7 V OT 6 REF GND S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = C/W(N8) T JMAX = C, θ JA = C/W(S8) ORDER PART NMBER LTC68CN8 LTC68IN8 LTC68CS8 LTC68IS8 S8 PART MARKING 68 68I ELECTRICAL CHARACTERISTICS V CC =.7V to.v, V OT unloaded, REF V CC, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS DAC Resolution Bits Monotonicity Bits DNL Differential Nonlinearity V REF V CC.V (Note ) ±. LSB INL Integral Nonlinearity V REF V CC.V (Note ) ±8. LSB Zero Scale Error T A = C, N8 and S8 Package. mv T A = T MIN to T MAX, N8 and S8 Package. mv T A = T MIN to T MAX, MSOP Package 7. mv Offset Error T A = C, N8 and S8 Package, (Note 7) ±. mv T A = T MIN to T MAX, N8 and S8 Package, (Note 7) ±. mv T A = T MIN to T MAX, MSOP Package, (Note 7) ±7. mv V OS TC Offset Error Temperature ± µv/ C Coefficient Gain Error ± LSB Power Supply Gain Error Drift ±. ppm/ C V CC Positive Supply Voltage For Specified Performance.7. V I CC Supply Current.7V V CC.V (Note ) 7 µa Op Amp DC Performance Short-Circuit Current Low V OT Shorted to GND ma Short-Circuit Current High V OT Shorted to V CC ma

3 ELECTRICAL CHARACTERISTICS V CC =.7V to.v, V OT unloaded, REF V CC, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS AC Performance Reference Input Output Impedance to GND Input Code = 7 Ω Output Line Regulation Input Code = 68, V CC =.7V to.v, REF =.V. mv/v Voltage Output Slew Rate.. V/µs Voltage Output Settling Time (Note ) to ±.LSB µs Digital Feedthrough. nv s R IN REF Input Resistance 6 kω V REF REF Input Range (Notes, 6) V CC V Digital I/O V IH Digital Input High Voltage V CC = V. V V IL Digital Input Low Voltage V CC = V.8 V V OH Digital Output High Voltage V CC = V, I OT = ma, D OT Only V CC.7 V V OL Digital Output Low Voltage V CC = V, I OT = ma, D OT Only. V V IH Digital Input High Voltage V CC = V. V V IL Digital Input Low Voltage V CC = V.6 V V OH Digital Output High Voltage V CC = V, I OT = ma, D OT Only V CC.7 V V OL Digital Output Low Voltage V CC = V, I OT = ma, D OT Only. V I LEAK Digital Input Leakage V IN = GND to V CC ± µa C IN Digital Input Capacitance (Note 6) pf Switching (V CC =.V to.v) t Valid to Setup ns t Valid to Hold ns t High Time (Note 6) ns t Low Time (Note 6) ns t CS/LD Pulse Width (Note 6) ns t 6 LSB to CS/LD (Note 6) ns t 7 CS/LD Low to (Note 6) ns t 8 D OT Output Delay C LOAD = pf ns t 9 Low to CS/LD Low (Note 6) ns Switching (V CC =.7V to.v) t Valid to Setup 6 ns t Valid to Hold ns t High Time (Note 6) 6 ns t Low Time (Note 6) 6 ns t CS/LD Pulse Width (Note 6) 8 ns t 6 LSB to CS/LD (Note 6) 6 ns t 7 CS/LD Low to (Note 6) ns t 8 D OT Output Delay C LOAD = pf ns t 9 Low to CS/LD Low (Note 6) ns

4 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range. Note : Absolute Maximum Ratings are those values beyond which the life a device may be impaired. Note : Nonlinearity is defined from code to code 68 (full scale). See Applications Information. Note : DAC switched between code 68 and code. Note : Digital inputs at V or V CC. Note : V OT can only swing from (GND + V OS ) to (V CC V OS ) when output is unloaded. See Applications Information. Note 6: Guaranteed by design. Not subject to test. Note 7: Measured at code. TYPICAL PERFOR A CE CHARACTERISTICS W INL ERROR (LSB) Integral Nonlinearity (INL) vs Input Code CODE DNL ERROR (LSB) Differential Nonlinearity (DNL) vs Input Code CODE SPPLY CRRENT (ma) Supply Current vs Logic Input Voltage ALL DIGITAL INPTS TIED TOGETHER LOGIC INPT VOLTAGE (V) 68 G 68 G 68 G V CC V OT (V) Minimum Supply Headroom for Full Output Swing vs Load Current V OT < LSB CODE: ALL s V OT =.96V C C C LOAD CRRENT (ma) 68 G OTPT PLL-DOWN VOLTAGE (V) Minimum Output Voltage vs Output Sink Current..9 CODE: ALL ZEROS.8.7 C.6. C... C. OTPT SINK CRRENT (ma) 68 G OFFSET ERROR (LSB) Offset Error vs Temperature TEMPERATRE ( C) 68 G6

5 TYPICAL PERFOR A CE CHARACTERISTICS W GAIN ERROR (LSB) Gain Error vs Temperature 6 9 TEMPERATRE ( C) 68 G6 LSB/DIV Broadband Noise BW = Hz TO µs/div 68 G8 khz PIN FNCTIONS (Pin ): The TTL Level Input for the Serial Interface Clock. (Pin ): The TTL Level Input for the Serial Interface Data. Data on the pin is latched into the shift register on the rising edge of the serial clock and is loaded MSB first. The LTC68 requires a 6-bit word to be loaded in. The last two bits are don t cares. CS/LD (Pin ): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low the signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. D OT (Pin ): Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin ): Ground. REF (Pin 6): Reference Input. There is a gain of one from this pin to the output. When tied to V CC the output will swing from GND to V CC. The output can only swing to within it s offset specification of V CC (see Applicatons Information). V OT (Pin 7): Buffered Rail-to-Rail DAC Output. V CC (Pin 8): Positive Supply Input..7V V CC.V.

6 W W TI I G DIAGRA t t t t t 6 t 7 t 9 B MSB B B B LSB BX DMMY BX DMMY CS/LD t 8 t D OT B PREVIOS WORD B B BX BX B CRRENT WORD 68 TD DEFI ITIO S Differential Nonlinearity (DNL): The difference between the measured change and the ideal LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = ( V OT LSB)/LSB Where V OT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nv)(sec). Gain Error: Gain error is the difference between the output of a DAC from its ideal full-scale value after offset error has been adjusted. Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [V OT V OS (V FS V OS )(code/68)]/lsb Where V OT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = V REF /68 Resolution (n): Defines the number of DAC output states ( n ) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (V OS ): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. 6

7 OPERATIO LTC68 Serial Interface The data on the input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The input word must be 6 bits wide. The last two bits are don t cares. The buffered output of the 6-bit shift register is available on the D OT pin which swings from GND to V CC. Multiple LTC68s may be daisy-chained together by connecting the D OT pin to the pin of the next chip while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC68 rail-to-rail buffered output can source or sink ma over the entire operating temperature range while pulling to within mv of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of Ω, at V V CC, when driving a load to the rails. The output can drive pf without going into oscillation. The output swings from V to the voltage at the REF pin, i.e., there is a gain of from REF to V OT. Please note, if REF is tied to V CC the output can only swing to (V CC V OS ). See Applications Information. 7

8 APPLICATIONS INFORMATION W Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at V as shown in Figure b. Similarly, limiting can occur near full scale when the REF pin is tied to V CC. If V REF = V CC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at V CC as shown in Figure c. No full-scale limiting can occur if V REF is less than V CC FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. V REF = V CC POSITIVE FSE OTPT VOLTAGE INPT CODE (c) V REF = V CC OTPT VOLTAGE INPT CODE (a) OTPT VOLTAGE NEGATIVE OFFSET V INPT CODE (b) 68 F Figure. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V REF = V CC 8

9 TYPICAL APPLICATIO S An Optoisolated ma to ma Process Controller V LOOP.8V TO V LT -. IN OT + µf 7k % k FROM OPTO- ISOLATED INPTS V CC REF CS/LD LTC68 V OT 6.k % k.k % + LT77 k Q N R S Ω CS/LD OPTOISOLATORS Ω N8.V.6k CS/LD 68 TA I OT This circuit shows how to use an LTC68 to make an optoisolated digitally controlled ma to ma process controller. The controller circuitry, including the optoisolation, is powered by the loop voltage that can have a wide range of.8v to V. The.V output of the LT-. is used for the ma offset current and V OT is used for the digitally controlled ma to 6mA current. R S is a sense resistor and the op amp modulates the transistor Q to provide the ma to ma current through this resistor. The potentiometers allow for offset and full-scale adjustment. The control circuitry dissipates well under the ma budget at zero-scale. 9

10 TYPICAL APPLICATIO S A -Bit Analog Input/Output Channel for a PC V DIFFERENTIAL INPT D Ω Ω D Ω Ω A IN + A IN LTC7 6 V CC V SS µf D D V REF BSY µf µf V REFCOMP AGND CONVST RD 6 EXTIN SHDN 7 S DGND 8 OT D OT 9 LTC68 CS/LD 8 V CC 7 V OT 6 REF D OT GND µf / 7HC7 D PR Q CLR CK Q 6 V C 7µF 6 LT- C µf D6 D ANALOG OTPT k SELECT TX k RTS / 7HC7 9 D Q PR CLR V 8 CK Q k S D OT DTR CTS V C.µF 68 TA 68 TA

11 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # -8-66).8 ±.* (. ±.).7 (.8). ±.6 (. ±.) 6 TYP SEATING PLANE. ±.6 (. ±.). (.) REF.6 (.6) TYP. ±. (.86 ±.).6 ±. (. ±.) * DIMENSION DOES NOT INCLDE MOLD FLASH, PROTRSIONS OR GATE BRRS. MOLD FLASH, PROTRSIONS OR GATE BRRS SHALL NOT EXCEED.6" (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH OR PROTRSIONS. INTERLEAD FLASH OR PROTRSIONS SHALL NOT EXCEED.6" (.mm) PER SIDE.9 ±. (.88 ±.) ±.** (. ±.) MSOP (MS8) 97.. (7.6 8.)..6 (..6) N8 Package 8-Lead PDIP (Narrow.) (LTC DWG # -8-). ±. (. ±.7).* (.6) MAX (.9.8) ( ).6 (.6) TYP. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.7) MIN.8 ±. (.7 ±.76). (.8) MIN. ±.* (6.77 ±.8) N (..).. (..8) 8 TYP S8 Package 8-Lead Plastic Small Outline (Narrow.) (LTC DWG # -8-6)..69 (.6.7).. (..).89.97* (.8.) (..8) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE. (.7) TYP.8. ( ) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights...7** (.8.988) SO8 996

12 TYPICAL APPLICATION -Bit, V to V Single Supply, Voltage Output DAC.7V TO.V V CC REF.µF µp CS/LD D OT LTC68 V OT OTPT V TO REF GND TO NEXT DAC FOR DAISY-CHAINING 68 TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC7 Single -Bit V OT DAC, Full Scale:.8V, V CC :.7V to.7v, V to V Single Supply, Complete V OT DAC in Reference Can Be Overdriven p to V, i.e., FS MAX = V SO-8 Package LTC6/LTC6L Dual -Bit V OT DACs in SO-8 Package LTC6: V CC =.V to.v, V OT = V to.9v LTC6L: V CC =.7V to.v, V OT = V to.v LTC8 Dual -Bit V OT DAC, V CC :.7V to.v Output Swings from GND to REF. REF Input Can Be Tied to V CC LTC/LTCL Single -Bit V OT DACs with Parallel Interface LTC: V CC =.V to.v, V OT = V to.9v LTCL: V CC =.7V to.v, V OT = V to.v LTC Single Rail-to-Rail -Bit DAC, Full Scale:.9V, V CC :.V to.v, V, Low Power Complete V OT DAC in SO-8 Package Internal.8V Reference Brought Out to Pin LTC Single Rail-to-Rail -Bit V OT Multiplying DAC, V CC :.7V to.v Low Power, Multiplying V OT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC Single Rail-to-Rail -Bit V OT DAC, Full Scale:.V, V CC :.7V to.v V, Low Power, Complete V OT DAC in SO-8 Package LTC/LTCL Dual -Bit V OT DACs in SO-6 Package with Added Functionality LTC: V CC =.V to.v, V OT = V to.9v LTCL: V CC =.7V to.v, V OT = V to.v LTC6 Single Rail-to-Rail Output -Bit DAC with Clear Pin, Low Power, Complete V OT DAC in SO-8 Full Scale:.9V, V CC :.V to.v Package with Clear Pin LTC8/LTC8L Quad Bit Rail-to-Rail Output DACs with Added Functionality LTC8: V CC =.V to.v, V OT = V to.9v LTC8L: V CC =.7V to.v, V OT = V to.v LTC69 Single Rail-to-Rail -Bit V OT DAC in 8-Pin MSOP, V CC :.7V to.v Low Power, Multiplying V OT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to V CC. References LT9 Precision Voltage Reference ltralow Drift ppm/ C, Initial Accuracy:.% LT6 Micropower Precision Reference Low Drift ppm/ C, Initial Accuracy:.% Linear Technology Corporation 6 McCarthy Blvd., Milpitas, CA 9-77 (8)-9 FAX: (8) f LT/TP 99 K PRINTE SA LINEAR TECHNOLOGY CORPORATION 998