FEATURES APPLICATIO S. LTC1150 ±15V Zero-Drift Operational Amplifier with Internal Capacitors DESCRIPTIO TYPICAL APPLICATIO

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1 FEATRES High Voltage Operation: ±1V No External Components Required Maximum Offset Voltage: 1µV Maximum Offset Voltage Drift:.5µV/ C Low Noise 1.8µV P-P (.1Hz to 1Hz) Minimum Voltage Gain: 15dB Minimum PSRR: 1dB Minimum CMRR: 11dB Low Supply Current:.8mA Single Supply Operation:.5V to V Input Common Mode Range Includes Ground µa Supply Current with Pin 1 Grounded Typical Overload Recovery Time ms APPLICATIO S Strain Gauge Amplifiers Electronic Scales Medical Instrumentation Thermocouple Amplifiers High Resolution Data Acquisition LTC115 ±15V Zero-Drift Operational Amplifier with Internal Capacitors DESCRIPTIO The LTC 115 is a high-voltage, high-performance zero-drift operational amplifier. The two sample-and-hold capacitors usually required externally by other chopper amplifiers are integrated on-chip. Further, LTC s proprietary high-voltage CMOS structures allow the LTC115 to operate at up to V total supply voltage. The LTC115 has an offset voltage of.5µv, drift of.1µv/ C,.1Hz to 1Hz input noise voltage of 1.8µV P-P and a typical voltage gain of 18dB. The slew rate of V/µs and a gain bandwidth product of.5mhz are achieved with.8ma of supply current. Overload recovery times from positive and negative saturation conditions are ms and ms, respectively. For applications demanding low power consumption, Pin 1 can be used to program the supply current. Pin 5 is an optional AC-coupled clock input, useful for synchronization. The LTC115 is available in standard 8-lead, plastic dualin-line package, as well as an 8-lead SO package. The LTC115 can be a plug-in replacement for most standard bipolar op amps with significant improvement in DC performance., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIO 1M V IN Single Supply Instrumentation Amplifier 1k V LTC115 1k V IN 1M V LTC115 V OT GAIN = 1V/V OTPT OFFSET 5mV TOTAL SPPLY CRRENT DECREASES TO µa WHEN BOTH PIN 1s ARE GRONDED LTC115 TA1 VOLTAGE NOISE DENSITY (nv Hz) Noise Spectrum 1 1 1k 1k 1k FREQENCY (Hz) LTC115 TA 115fb 1

2 LTC115 ABSOLTE AXI RATI GS W W W Total Supply Voltage (V to V )... V Input Voltage (Note )... (V.V) to (V.V) Output Short Circuit Duration... Indefinite Burn-In Voltage... V W PACKAGE/ORDER I FOR ATIO (Note 1) Operating Temperature Range LTC115M (OBSOLETE)...55 C to 15 C LTC115C... C to 85 C Storage Temperature Range... 5 C to 15 C Lead Temperature (Soldering, 1 sec)... C I SPPLY IN IN V 1 TOP VIEW 8 5 N8 PACKAGE 8-LEAD PDIP T JMAX = 11 C, θ JA = 1 C/W J8 PACKAGE 8-LEAD CERDIP CLOCK OT V OT EXT CLOCK IN OBSOLETE PACKAGE Consider the N8 or S8 Package as an Alternate Source ORDER PART NMBER LTC115CN8 LTC115MJ8 LTC115CJ8 Consult LTC Marketing for parts specified with wider operating temperature ranges. I SPPLY 1 IN IN V TOP VIEW 8 5 S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 11 C, θ JA = C/W CLOCK OT V OT EXT CLOCK IN ORDER PART NMBER LTC115CS8 S8 PART MARKING 115 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at T A = 5 C. V S = ±15V, Pin 1 = Open, unless otherwise noted. LTC115M LTC115C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Input Offset Voltage (Note ) ±.5 ±1 ±.5 ±1 µv Average Input Offset Drift (Note ) ±.1 ±.5 ±.1 ±.5 µv/ C Long Term Offset Voltage Drift 5 5 nv/ mo Input Offset Current ± ± ± ± pa ±1.5 ±.5 na Input Bias Current ±1 ±5 ±1 ±1 pa ±.5 ±1. na Input Noise Voltage R S = 1Ω,.1Hz to 1Hz, TC µv P-P R S = 1Ω,.1Hz to 1Hz, TC.. Input Noise Current f = 1Hz (Note ) fa/ Hz Common Mode Rejection Ratio V CM = V to 1V db Power Supply Rejection Ratio V S = ±.5V to ±1V db Large-Signal Voltage Gain R L = 1kΩ, V OT = ±1V db Maximum Output Voltage Swing R L = 1kΩ ±1.5 ±1.5 ±1.5 ±1.5 V R L = 1kΩ 1.5/ 1.5/ R L = 1kΩ ±1.95 ± fb

3 ELECTRICAL CHARACTERISTICS LTC115 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 5 C. V S = ±15V, Pin 1 = Open, unless otherwise noted. LTC115M LTC115C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Slew Rate R L = 1kΩ, C L = 5pF V/µs Gain Bandwidth Product.5.5 MHz Supply Current No Load ma No Load, Pin 1 = V.. No Load Internal Sampling Frequency Hz The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 5 C. V S = 5V, Pin 1 = Open, unless otherwise noted. LTC115M LTC115C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Input Offset Voltage (Note ) ±.5 ±1 ±.5 ±1 µv Average Input Offset Drift (Note ) ±.1 ±.5 ±.1 ±.5 µv/ C Long Term Offset Voltage Drift 5 5 µv/ mo Input Offset Current ±1 ± ±1 ± pa Input Bias Current ±5 ± ±5 ± pa Input Noise Voltage R S = 1Ω,.1Hz to 1Hz, TC.. µv P-P R S = 1Ω,.1Hz to 1Hz, TC.. Input Noise Current f = 1Hz (Note ) fa/ Hz Common Mode Rejection Ratio V CM = V to.v db Power Supply Rejection Ratio V S = ±.5V to ±1V db Large-Signal Voltage Gain R L = 1kΩ, V OT =.V to.5v db Maximum Output Voltage Swing R L = 1kΩ.15 to to.85 V R L = 1kΩ. to.9. to.9 Slew Rate R L = 1kΩ, C L = 5pF V/µs Gain Bandwidth Product MHz Supply Current No Load ma Internal Sampling Frequency Hz Note 1: Absolute Maximum Ratings are those values beyond which life of the device may be impaired. Note : Connecting any terminal to voltages greater than V or less than V may cause destructive latch-up. It is recommended that no sources operating from external supplies be applied prior to power-up of the LTC115. Note : These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high-speed automatic test systems. V OS is measured to a limit determined by test equipment capability. Note : Current Noise is calculated from the formula: I N = (q I b ) where q = Coulomb. 115fb

4 LTC115 TEST CIRCITS Offset Voltage Test Circuit DC-1Hz Noise Test Circuit 1M 5k 1k V 1k.1µF LTC115 V R L OTPT 1Ω LTC k 1k.1µF 5k.1µF LT11 TO X-Y RECORDER LTC115 TC1 FOR 1Hz NOISE BW, INCREASE ALL THE CAPACITORS BY A FACTOR OF 1 LTC115 TC TYPICAL PERFOR A CE CHARACTERISTICS W Supply Current vs Supply Voltage Supply Current vs Temperature Gain/Phase vs Frequency SPPLY CRRENT (µa) T A = 5 C SPPLY CRRENT (µa) GAIN (db) C L = 1pF GAIN PHASE PHASE (DEGREES) TOTAL SPPLY VOLTAGE, V TO V (V) AMBIENT TEMPERATRE ( C) 1 1k 1k 1k 1M 1M FREQENCY (Hz) LTC115 TPC1 LTC115 TPC LTC115 TPC SHORT-CIRCIT OTPT CRRENT, I OT (ma) Output Short-Circuit Current vs Supply Voltage V OT = V I SORCE V OT = V I SINK PIN 1 = OPEN PIN 1 = V PIN 1 = V PIN 1 = OPEN T A = 5 C TOTAL SPPLY VOLTAGE, V TO V (V) LTC115 TPC SPPLY CRRENT (µa) k Supply Current vs R SET T A = 5 C 1k 1k 1M R SET, PIN 1 TO V (Ω) LTC115 TPC5 GAIN (db) Gain/Phase vs Frequency GAIN C L = 1pF PIN 1 = 15V PHASE 1 1k 1k 1k 1M 1M FREQENCY (Hz) LTC115 TPC PHASE (DEGREES) 115fb

5 LTC115 TYPICAL PERFOR A CE CHARACTERISTICS W INPT BIAS CRRENT (pa) Input Bias Current vs Supply Voltage T A = 5 C V CM = OV OTPT VOLTAGE (Vp-p) ndistorted Output Swing vs Frequency PIN 1 = V R L = 1k PIN 1 = FLOATING R L = 1k GAIN (db) Gain/Phase vs Frequency V S = ±.5V C L = 1pF GAIN PHASE PHASE (DEGREES) ± ± ± ± 8 ±1 ±1 ±1 ±1 SPPLY VOLTAGE (V) 1 1k 1k 1k 1M FREQENCY (Hz) 1 1k 1k 1k 1M 1M FREQENCY (Hz) LTC115 TPC LTC115 TPC8 LTC115 TPC9 INPT BIAS CRRENT (pa) 1 1 Input Bias Current vs Input Common Mode Voltage I B I B T A = 5 C INPT BIAS CRRENT (pa) Input Bias Current vs Temperature V CM = I B I B COMMON MODE RANGE (V) Common Mode Input Range vs Supply Voltage T A = 5 C INPT COMMON MODE VOLTAGE (V) LTC115 TPC TEMPERATRE ( C) LTC115 TPC11 15 ±.5 ±5 ±.5 ±1 ±1.5 ±15 SPPLY VOLTAGE (V) LTC115 TPC1 CMRR vs Frequency PSRR vs Frequency Offset Voltage vs Sampling Frequency CMRR (db) PSRR (db) POSITIVE SPPLY, PIN 1 = OPEN NEGATIVE SPPLY, PIN 1 = OPEN NEGATIVE SPPLY, PIN 1 = V POSITIVE SPPLY, PIN 1 = V OFFSET VOLTAGE (µv) 1 8 V A = ± 15V T A = 5 C PIN 1 = V PIN 1 = OPEN k 1k 1k FREQENCY (Hz) k 1k 1k FREQENCY (Hz) 1k k SAMPLING FREQENCY, f S (Hz) k LTC115 TPC1 LTC115 TPC1 LTC115 TPC15 115fb 5

6 LTC115 TYPICAL PERFOR A CE CHARACTERISTICS W OFFSET VOLTAGE DRIFT (nv/c ) Offset Voltage Drift vs Sampling Frequency PIN 1 = OPEN 1Hz PEAK-TO-PEAK NOISE (µv) 1 1Hz p-p Noise vs Sampling Frequency T A = 5 C SAMPLING FREQENCY (Hz) Sampling Frequency vs Temperature 1 1k SAMPLING FREQENCY, f S (Hz) 1k 1 1k SAMPLING FREQENCY, f S (Hz) 1k AMBIENT TEMPERATRE ( C) LTC115 TPC1 LTC115 TPC1 LTC115 TPC18 Large-Signal Transient Response Large-Signal Transient Response, Pin 1 = V Small-Signal Transient Response V S = ±15V, A V = 1, C L = 1pF, R L = 1kΩ V S = ±15V, A V = 1, C L = 1pF, PIN 1 = V V S = ±15V, A V = 1, C L = 1pF, R L = 1kΩ Small-Signal Transient Response, Pin 1 = V Overload Recovery from Negative Saturation Overload Recovery from Positive Saturation V S = ±15V, A V = 1, C L = 1pF, R L = 1kΩ, PIN 1 = V V S = ±15V, A V = 1, ms/div V S = ±15V, A V = 1, ms/div 115fb

7 LTC115 TYPICAL PERFOR A CE CHARACTERISTICS W.1Hz to 1Hz Noise, V = ±15V, T A = 5 C, Internal Clock.µV P-P 1µV 1s 1s LTC115 TPC5.1Hz to 1Hz Noise, V = ±15V, T A = 5 C, f S = 18Hz 1.µV P-P 1µV 1s 1s LTC115 TPC.1Hz to 1Hz Noise, V = ±15V, T A = 5 C, Internal Clock nv P-P 5nV 1s 1s LTC115 TPC 115fb

8 LTC115 TYPICAL PERFOR A CE CHARACTERISTICS W.1Hz to 1Hz Noise, V = ±15V, T A = 5 C, f S = 18Hz nv P-P 5nV 1s 1s LTC115 TPC8 PI DESCRIPTIO S 8-Pin Packages I SPPLY (Pin 1): Supply Current Programming. The supply current can be programmed through Pin 1. When Pin 1 is left open or tied to V, the supply current defaults to 8µA. Tying a resistor between Pin 1 and Pin, the negative supply pin, will reduce the supply current. The supply current, as a function of the resistor value, is shown in Typical Performance Characteristics. IN (Pin ): Inverting Input. IN (Pin ): Noninverting Input. V (Pin ): Negative Supply. EXT CLOCK IN (Pin 5): Optional External Clock Input. The LTC115 has an internal oscillator to control the circuit operation of the amplifier if Pin 5 is left open or biased at any DC voltage in the supply voltage range. When an external clock is desirable, it can be applied to Pin 5. The applied clock is AC-coupled to the internal circuitry to simplified interface requirements. The amplitude of the clock input signal needs to be greater than V and the voltage level has to be within the supply voltage range. Duty cycle is not critical. The internal chopping frequency is the external clock frequency divided by four. When frequency of the external clock falls below 1Hz (internal chopping at 5Hz), the internal oscillator takes over and the circuit chops at 55Hz. OT (Pin ): Output. V (Pin ): Positive Supply. CLOCK OT (Pin 8): Clock Output. The signal coming out of this pin is at the internal oscillator frequency of about.khz (four times the chopping frequency) and has voltage levels at V H = V S and V L = V S.. If the circuit is driven by an external clock, Pin 8 is pulled up to V S fb

9 LTC115 APPLICATIO S I FOR ATIO W ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE Picoamperes In order to realize the picoampere level of accuracy of the LTC115, proper care must be exercised. Leakage currents in circuitry external to the amplifier can significantly degrade performance. High quality insulation should be used (e.g., Teflon, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be necessaryparticularly for high temperature performance. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input connections with a guard ring operated at a potential close to that of the inputs: in inverting configurations the guard ring should be tied to ground; in noninverting connections to the inverting input. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends on the guard ring width. Microvolts Thermocouple effects must be considered if the LTC115 s ultralow drift is to be fully utilized. Any connection of dissimilar metals forms a thermoelectric junction producing an electric potential which varies with temperature (Seebeck effect). As temperature sensors, thermocouples exploit this phenomenon to produce useful information. In low drift amplifier circuits the effect is a primary source of error. Connectors, switches, relay contacts, sockets, resistors, solder, and even copper wire are all candidates for thermal EMF generation. Junctions of copper wire from different manufacturers can generate thermal EMFs of nv/ C four times the maximum drift specification of the LTC115. The copper/kovar junction, formed when wire or printed circuit traces contact a package lead, has a thermal EMF of approximately 5µV/ C times the maximum drift specification of the LTC115. Minimizing thermal EMF-induced errors is possible if judicious attention is given to circuit board layout and component selection. It is good practice to minimize the number of junctions in the amplifier s input signal path. Avoid connectors, sockets, switches, and relays where possible. In instances where this is not possible, attempt to balance the number and type of junctions so that differential cancellation occurs. Doing this may involve deliberately introducing junctions to offset unavoidable junctions. Figure 1 is an example of the introduction of an unnecessary resistor to promote differential thermal balance. Maintaining compensating junctions in close physical proximity will keep them at the same temperature and reduce thermal EMF errors. NOMINALLY NNECESSARY RESISTOR SED TO THERMALLY BALANCE OTHER INPT RESISTOR RESISTOR LEAD, SOLDER, COPPER TRACE JNCTION LEAD WIRE/SOLDER COPPER TRACE JNCTION LTC115 Figure 1. Extra Resistors Cancel Thermal EMF OTPT LTC115 AI1 When connectors, switches, relays and/or sockets are necessary, they should be selected for low thermal EMF activity. The same techniques of thermally-balancing and coupling the matching junctions are effective in reducing the thermal EMF errors of these components. Resistors are another source of thermal EMF errors. Table 1 shows the thermal EMF generated for different resistors. The temperature gradient across the resistor is important, not the ambient temperature. There are two junctions formed at each end of the resistor and if these junctions are at the same temperature, their thermal EMFs will cancel each other. The thermal EMF numbers are approximate and vary with resistor value. High values give higher thermal EMF. 115fb 9

10 LTC115 APPLICATIO S I FOR ATIO Table 1. Resistor Thermal EMF 1 RESISTOR TYPE Tin Oxide Carbon Composition Metal Film WireWound Evenohm Manganin W THERMAL EMF/ C GRADIENT ~mv/ C ~5µV/ C ~µv/ C ~µv/ C ~µv/ C PACKAGE-INDCED OFFSET VOLTAGE Package-induced thermal EMF effects are another important source of errors. It arises at the copper/kovar junctions formed when wire or printed circuit traces contact a package lead. Like all the previously mentioned thermal EMF effects, it is outside the LTC115 s offset nulling loop and cannot be cancelled. Metal can H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC115 is actually set by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from.5 to minutes, depending on package type. ALIASING Like all sampled data systems, the LTC115 exhibits aliasing behavior at input frequencies near the sampling frequency. The LTC115 includes a high-frequency correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications. For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC151/5 data sheet. SYNCHRONIZATION OF MLTIPLE LTC115O S When synchronization of several LTC115 s is required, one of the LTC115 s can be used to provide the master clock to control over 1 slave LTC115 s. The master clock, coming from Pin 8 of the master LTC115, can directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC115 s will be pulled up to V S. If all the LTC115 s are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC115 s. LEVEL SHIFTING THE CLOCK Level shifting is needed if the clock output of the LTC115 in ±15V operation must interface to regular 5V logic circuits. Figures and show some typical level shifting circuits. When operated from single 5V or ±5V supplies, the LTC115 clock output at Pin 8 can interface to TTL or CMOS inputs directly. LOW SPPLY OPERATION The minimum supply for proper operation of the LTC115 is typically below.v (±.V). In single supply applications, PSRR is guaranteed down to.v (±.5V) to ensure proper operation down to the minimum TTL specified voltage of.5v. 15V LTC115 15V 8 1k 1k 5V LOGIC CIRCIT LTC115 AI Figure. Output Level Shift (Option 1) 15V LTC115 15V 8 1pF GND 1k 5V 1k 5V LOGIC CIRCIT LTC115 AI Figure. Output Level Shift (Option ) 115fb

11 LTC115 TYPICAL APPLICATIO S Low Level Photodetector 15pF 1M 1Ω HP 58- V I P LTC115 1k OTPT = I P 1 9 Ω LTC115 TA Ground Force Reference 1k 15V 1pF 15V SINGLE POINT SENSE GROND LTC115 15V LT11 15V FORCED GROND APPLICATION: TO FORCE TWO GROND POINTS IN A SYSTEM WITHIN 5µV LTC115 TA 115fb 11

12 LTC115 TYPICAL APPLICATIO S Paralleling to Improve Noise CLK IN 1Ω 1k LTC115 1k 1k 1Ω LTC115 MEASRED NOISE V OS = 1.1µV CLK FREE RN CLK DRIVEN 18Hz 1Hz = nv P-P 1Hz = nv P-P V OS = 1µV 1Hz = nv P-P 1Hz = 1nV P-P 1k 5k 1k 1Ω LTC115 1k LTC115 V OT = 1k V IN IN 1k 1Ω LTC115 1k LTC115 TA5 Battery Discharge Monitor OPEN AT t = C R LTC115 IR1 V OT = t RC LOAD I R1 5µV ERROR pa IR1 I R R1 LTC115 TA 1 115fb

13 LTC115 PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow. Inch, Hermetic) (Reference LTC DWG # ).5.8 ( ) FLL LEAD OPTION. BSC (. BSC) CORNER LEADS OPTION ( PLCS)..5 ( ) HALF LEAD OPTION.5 (.1) MIN.5 (.5) RAD TYP.5 (1.8) MAX ( ). (5.8) MAX.15. ( ).8.18 (..5) 15 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.5.5 ( ).1. (..).1 (.5) BSC MIN J8 81 OBSOLETE PACKAGE 115fb 1

14 LTC115 PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow. Inch) (Reference LTC DWG # ).* (1.1) MAX ±.15* (. ±.81) 1..5 (. 8.55).5.5 ( ).1 ±.5 (. ±.1).8.15 (..81) ( ).5 (1.51) TYP.1 (.5) BSC NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.1 INCH (.5mm).1 (.8) MIN.18 ±. (.5 ±.). (.58) MIN N fb

15 LTC115 PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow.15 Inch) (Reference LTC DWG # ) N.5 BSC.5 ± (.81 5.) NOTE MIN 1 N/.1 ±.5.8. ( ) N N/ ( ) NOTE. ±.5 TYP RECOMMENDED SOLDER PAD LAYOT (..5).1. (.5.58) 5 8 TYP.5.9 (1. 1.5)..1 (.11.5) (. 1.) (.55.8) NOTE: INCHES TYP 1. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED." (.15mm).5 (1.) BSC SO8 5 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 115fb 15

16 LTC115 TYPICAL APPLICATIO DC Stabilized, Low Noise Amplifier 15V INPT LTC115 15V.1µF 15V 1k 1Ω 1 LT18 8 8Ω 15V OTPT 1k 15V (A = 1) 1Ω LTC115 TA 1 Linear Technology Corporation 1 McCarthy Blvd., Milpitas, CA (8) -19 FAX: (8) fb LW/TP 1 1K REV B PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 1991