Projet 5 - K3501 / Onduleur 12V DC - 220V AC.

Transcription

1 Thierry LEQUEU Septembre 26 [DATA76] Fichier : PROJETS-IUT1.DOC Projet 5 - K351 / Onduleur 12V DC - 22V AC. Projet : PROJETS-IUT1 Info : kit Velleman, [DATA12]. Révision : 24 janvier Liste des documents - Liste des composants. - Schéma électronique. - Implantation des composants. - Circuit imprimé coté cuivre. - Documentation des composants - Recherche des montages équivalents. Figure 5.1. Face avant (images-maquettes\onduleur2.jpg). 26

2 Réalisation de circuits imprimés IUT / Documentation des composants IRFP14 31A, 1V,.7 Ohm, N-Channel Power MOSFET, July HCF411B QUAD 2 INPUT HCC/HCF 411B. MC1413B Dual D-type flip-flop. HEF46B January 1995, MSI 14-stage ripple-carry binary counter/divider and oscillator. Figure 5.2. Câblage du montage (images-maquettes\onduleur1.jpg). 5.3 Recherche des montages équivalents [DATA11] [99ART98] K351, Convertisseur 12V ou 24V DC en 22V AC, Kit Velleman. R. RATEAU, Convertisseur 12V/22V 5 Hz - 22VA, Radio Plans - Electronique Loisirs N 423, pp [DATA21] G. ISABEL, Un convertisseur 12V/2V - 25VA, Electronique Pratique, no. 186, pp [DATA22] Réalisation flash, Convertisseur 12V/2V - 3 VA, Le haut-parleur hors série, pp [DATA68] [DATA14] [DATA16] G. LAVERGNE, J. ROULLET, Onduleur à point milieux 12V/22V, projet IUT GEII, mars E. AYMERIAL, N. MOUKHLISS, Onduleur de secours 12V --> 22V 5 Hz, projet IUT GEII TOURS, mars 2. M. CHI, R. CUZON, Onduleur de secours 12V --> 22V 5 Hz, projet IUT GEII TOURS, mars 2, 6 pages. 27

3 Thierry LEQUEU Septembre 26 [DATA76] Fichier : PROJETS-IUT1.DOC 5.4 Facture 26 Radioson Figure 5.3. Commande Radioson 26 (images-maquettes\k351-radioson-26.jpg). 28

4 IRFP14 Data Sheet July 1999 File Number A, 1V,.77 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA Ordering Information PART NUMBER PACKAGE BRAND IRFP14 TO-247 IRFP14 NOTE: When ordering, include the entire part number. Features 31A, 1V r DS(ON) =.77Ω Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol G D S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) 4-35 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. or Copyright Intersil Corporation 1999

5 IRFP14 Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified IRFP14 UNITS Drain to Source Voltage (Note 1) V DS 1 V Drain to Gate Voltage (R GS = 2kΩ) (Note 1) V DGR 1 V Continuous Drain Current I D 31 A T C = 1 o C I D 22 A Pulsed Drain Current (Note 3) I DM 12 A Gate to Source Voltage V GS ±2 V Maximum Power Dissipation P D 18 W Linear Derating Factor W/ o C Single Pulse Avalanche Energy Rating (Note 4) E AS 1 mj Operating and Storage Temperature T J, T STG -55 to 175 o C Maximum Temperature for Soldering Leads at.63in (1.6mm) from Case for 1s T L 3 Package Body for 1s, See Techbrief T pkg 26 o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation ofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 15 o C. Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS V GS = V, I D = 25µA (Figure 1) V Gate to Threshold Voltage V GS(TH) V GS = V DS, I D = 25µA V Zero Gate Voltage Drain Current I DSS V DS = Rated BV DSS, V GS = V µa V DS =.8 x Rated BV DSS, V GS = V, T J = 125 o C µa On-State Drain Current (Note 2) I D(ON) V DS > I D(ON) x r DS(ON)MAX, V GS = 1V A Gate to Source Leakage I GSS V GS = ±2V - - ±1 na Drain to Source On Resistance (Note 2) r DS(ON) V GS = 1V, I D = 19A (Figures 8, 9) Ω Forward Transconductance (Note 2) g fs V DS 5V, I D = 19A (Figure 12) S Turn-On Delay Time t d(on) V DD = 5V, I D 28A, R GS = 9.1Ω, R L = 1.7Ω, ns Rise Time t r V GS = 1V MOSFET Switching Times are Essentially ns Turn-Off Delay Time t d(off) Independent of Operating Temperature ns Fall Time t f ns Total Gate Charge (Gate to Source + Gate to Drain) Q g(tot) V GS = 1V, I D 27A, V DS =.8 x Rated BV DSS, I G(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature nc Gate to Source Charge Q gs nc Gate to Drain Miller Charge Q gd nc Input Capacitance C ISS V GS = V, V DS 25V, f = 1.MHz (Figure 11) pf Output Capacitance C OSS pf Reverse Transfer Capacitance C RSS pf Internal Drain Inductance L D Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Internal Source Inductance L S Measured from the Source Lead, 6mm (.25in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D G L D L S S nh nh Thermal Resistance Junction to Case R θjc Thermal Resistance Junction to Ambient R θja Free Air Operation o C/W o C/W 4-36

6 IRFP14 Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Source to Drain Current I SD Modified MOSFET A D Pulse Source to Drain Current (Note 3) I Symbol Showing the SDM A Integral Reverse P-N Junction Diode G S Source to Drain Diode Voltage (Note 2) V SD T J = 25 o C, I SD = 31A, V GS = V (Figure 13) V Reverse Recovery Time t rr T J = 25 o C, I SD = 28A, di SD /dt = 1A/µs ns Reverse Recovered Charge Q RR T J = 25 o C, I SD = 28A, di SD /dt = 1A/µs µc NOTES: 2. Pulse test: pulse width 3µs, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. V DD = 25V, starting T J = 25 o C, L = 16µH, R G = 5Ω, peak I AS = 31A. Typical Performance Curves Unless Otherwise Specified POWER DISSIPATION MULTIPLIER T C, CASE TEMPERATURE ( o C) T C, CASE TEMPERATURE ( o C) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, TRANSIENT THERMAL IMPEDANCE t t 2 t 2 SINGLE PULSE NOTES: DUTY FACTOR: D = t 1 /t 2 PEAK T J = P DM x Z θjc + T C t 1, RECTANGULAR PULSE DURATION (s) P DM FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-37

7 IRFP14 Typical Performance Curves Unless Otherwise Specified (Continued) OPERATION IN THIS REGION IS LIMITED BY r DS(ON) 1µs 1µs 1ms 1ms T C = 25 o C DC T J = MAX RATED SINGLE PULSE V DS, DRAIN TO SOURCE VOLTAGE (V) V GS = 1V V GS = 8V V GS = 7V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 6V V GS = 5V V GS = 4V V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 8V V GS = 1V V GS = 7.V V GS = 6V V GS = 5V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V DS 5V T J = 175 o C T J = 25 o C V GS = 4V V DS, DRAIN TO SOURCE VOLTAGE (V) V GS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 1V V GS = 2V NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE PULSE DURATION = 8µs DUTY CYCLE =.5% MAX I D = 19A, V GS = 1V T J, JUNCTION TEMPERATURE ( o C) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-38

8 IRFP14 Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE I D = 25µA C, CAPACITANCE (pf) V GS = V, f = 1MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GD C ISS C OSS C RSS T J, JUNCTION TEMPERATURE ( o C) V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE g fs, TRANSCONDUCTANCE (S) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V DS 5V T J = 25 o C T J = 175 o C I SD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T J = 175 o C T J = 25 o C V SD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) 2 I D = 34A 16 V DS = 2V 12 V DS = 5V V 8 DS = 8V Q g, GATE CHARGE (nc) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-39

9 IRFP14 Test Circuits and Waveforms V DS BV DSS L t P V DS VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G + V DD - I AS V DD DUT V t P I AS.1Ω t AV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS t ON t d(on) t OFF t d(off) t r t f R L V DS 9% 9% V GS R G DUT + V DD - V GS 1% 5% 1% PULSE WIDTH 9% 5% 1% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR V DS (ISOLATED SUPPLY) V DD 12V BATTERY.2µF 5kΩ.3µF SAME TYPE AS DUT Q gs Q gd Q g(tot) V GS D V DS G DUT I G(REF) I G CURRENT SAMPLING RESISTOR S V DS I D CURRENT SAMPLING RESISTOR I G(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 2. GATE CHARGE WAVEFORMS 4-31

10 HCC411B/12B/23B HCF411B/12B/23B NAND GATES QUAD 2 INPUT HCC/HCF 411B DUAL 4 INPUT HCC/HCF 412B TRIPLE 3 INPUT HCC/HCF 423B PROPAGATION DELAY TIME = 6ns (typ.) AT. CL = 5pF, VDD = 1V BUFFERED INPUTS AND OUTPUTS QUIESCENT CURRENT SPECIFIED TO 2V FOR HCC DEVICE INPUT CURRENT OF 1nA AT 18V AND 25 C FOR HCC DEVICE. 1% TESTED FOR QUIESCENT CURRENT 5V, 1V AND 15V PARAMETRIC RATINGS MEETS ALL REQUIREMENTS OF JEDEC TEN- TATIVE STANDARD N o. 13A, STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES EY (Plastic Package) M1 (Micro Package) F (Ceramic Frit Seal Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC4XXBF HCF4XXBM1 HCF4XXBEY HCF4XXBC1 DESCRIPTION The HCC411B, HCC412B and HCC423B (extended temperature range) and HCF411B, HCF412B and HCF423B (intermediate temperature range) are monolithic, integrated circuit, available in 14-lead dual in-line plastic or ceramic package and plastic micropackage. The HCC/HCF411B, HCC/HCF412B and HCC/HCF423B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of COS/MOS gates. All inputs and outputs are buffered. PIN CONNECTIONS 411B 412B 423B June /12

11 SEMICONDUCTOR TECHNICAL DATA The MC1413B dual type D flip flop is constructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each flip flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip flops for counter and toggle applications. Static Operation Diode Protection on All Inputs Supply Voltage Range = 3. Vdc to 18 Vdc Logic Edge Clocked Flip Flop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse Capable of Driving Two Low power TTL Loads or One Low power Schottky TTL Load Over the Rated Temperature Range Pin for Pin Replacement for CD413B Î Î Î MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit Î VDD DC Supply Voltage.5 to ÎÎÎ ÎÎ ÎÎÎ V Vin, Vout Input or Output Voltage (DC or Transient).5 to VDD +.5 ÎÎÎ ÎÎ ÎÎÎ V lin, lout Input or Output Current (DC or Transient), ± 1 ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ per Pin ÎÎ ÎÎÎ ma PD Power Dissipation, per Package 5 ÎÎÎ ÎÎ ÎÎÎ mw Tstg Storage Temperature 65 to + 15 ÎÎÎ ÎÎ ÎÎÎ C TL Lead Temperature (8 Second Soldering) 26 ÎÎ C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic P and D/DW Packages: 7. mw/ C From 65 C To 125 C Ceramic L Packages: 12 mw/ C From 1 C To 125 C Inputs TRUTH TABLE Outputs Clock Data Reset Set Q Q X Q Q X X 1 1 X X 1 1 X X X = Don t Care = Level Change No Change L SUFFIX CERAMIC CASE 632 ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = 55 to 125 C for all packages BLOCK DIAGRAM D C D C S R S R Q Q Q Q VDD = PIN 14 VSS = PIN 7 P SUFFIX PLASTIC CASE 646 D SUFFIX SOIC CASE 751A REV 3 1/94 MOTOROLA Motorola, Inc CMOS LOGIC DATA MC1413B 45

12 Philips Semiconductors 14-stage ripple-carry binary counter/divider and oscillator Product specification HEF46B MSI DESCRIPTION The HEF46B is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, R TC and C TC ), ten buffered outputs (O 3 to O 9 and O 11 to O 13 ) and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (O 3 to O 9 and O 11 to O 13 = LOW), independent of other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. PINNING MR RS R TC C TC O 3 to O 9 O 11 to O 13 master reset clock input/oscillator pin oscillator pin external capacitor connection counter outputs Fig.2 Pinning diagram. HEF46BP(N): 16-lead DIL; plastic (SOT38-1) HEF46BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF46BT(D): 16-lead SO; plastic (SOT19-1) ( ): Package Designator North America FAMILY DATA, I DD LIMITS category MSI See Family Specifications January

13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be... January Fig.3 Logic diagram. 14-stage ripple-carry binary counter/divider and oscillator HEF46B MSI Philips Semiconductors Product specification