Millimeter wave. Dr. Kwang-Jin Koh MICS Group ECE Dept. Virginia Tech. MICS RFIC Group

Transcription

1 Millimeter wave Dr. Kwang-Jin Koh Group ECE Dept. Virginia Tech RFIC Group 1

2 Outline Tutorial-1 (1.5 hr) Millimeter wave overview: Applications, Challenges (25 min) LNA and Mixer design (25min) VCO design (20min) PA design (20 min) Tutorial-2 (1.5 hr) Introduction to Phased Array (10 min) Phased array metric and architectural study (30 min) Phase shifter/phased Array IC designs (50 min) RFIC Group 2

3 Millimeter wave overview Definition Millimeter wave bands for different applications Wireless Comm (Multi-Gbps data links) Challenges Example designs Automotive Radars Example designs Imaging systems Example designs RFIC Group 3

4 Millimeter wave definition IEEE bands: Ka band: GHz (Radar) V band: GHz (Radar/Sat. Comm) W band: GHz (Radar/Imaging/Fixed Point Wireless Comm) G band : GHz (> 10 s Gbps Wireless Comm./ Imaging) RFIC Group [ref1] 4

5 Millimeter wave bands 380 GHz 60 GHz 183 GHz 325 GHz 120 GHz 240 GHz GHz GHz GHz RFIC Group [ref2] [T. Rappaport, Proceeding of IEEE 2011 ] Channels For long/short range Links 5

6 mm-wave frequency band Applications Data Communication bands(based on FCC frequency allocation): GHz, GHz, GHz, GHz, Fixed and mobile communication, Fixed and mobile satellite communication Radar systems: 24.05~24.25GHz : Police radar 33.4 ~ 36.0 GHz: Short range surveillance 76~81 GHz: Automotive Radars 92 ~ 100 GHz: Automotive Radars, Airborne wire detection Imaging systems GHz: Passive and Active Imaging for Security gates and Medical Imaging applications RFIC Group 6

8 Demand for Gbps Links High data rate link for transferring large amount of data: Replacing paper/magnetic storage media at office, High quality multimedia (HDTV) at home, [T. Rappaport, Proceeding of IEEE 2011 ] RFIC Group 8

9 Demand for mm-wave Gbps Links Multi-Gbps wireless networks: 6 GHz bandwidth of unlicensed bands at 60 GHz, 71 GHz, and 81 GHz RFIC Group 9

10 Available standards for 60GHz IEEE ad IEEE ad VHT (very high throughput) Wireless display Distribution of HDTV Rapid upload/download Backhaul Outdoor Campus/Auditorium IEEE aj Portable device applications IEEE c Wireless display Distribution of HDTV RFIC Group 10

11 mm-wave band under investigation High data link applications for fixed communication: GHz, and GHz, and GHz bands IEEE Standard has not been set yet. RFIC Group 11

12 mm-wave Circuit design RFIC Group 12

13 Transceiver architecture Direct Conversion + No image rejection required, + Simple structure and low chip area, - More sensitive to Self-mixing, - Difficulty of generation of low phase noise LO, -Difficulties of distribution high frequency LO, Heterodyne + Relaxed LO and IF design, + LO distribution at lower frequency, - Difficulty of Image rejection, - Larger chip area, RFIC Group 13

14 mm-wave Circuit design Challenges No accurate (maybe reliable) model for active and passive devices Transistors have Lower current gain at frequencies near f T ( b =f T /f) Circuits are more sensitive to parasitics Parasitic caps should be resonated out by inductors or T-lines: need larger area Due to self-resonance requirements, load Inductors (in LNA, Mixer, ) can not have more than 2 turns: need larger area Larger area: More loss in signal path and LO distribution network and lower phase noise Quality factor of passives reduces at mm-wave frequencies More loss, more phase noise, poor filters RFIC Group 14

15 Which technology to use? Active device speed and gain f max /f T III-V devices have much higher f T f T of Si-based devices get high enough in recent scaled technologies System integration and yield Si-based RF front-ends can achieve high level of integration with analog/digital baseband circuits Mask levels and Fabrication cost III-V devices are expensive Si-based devices are cheap RFIC Group [T. Rappaport, Proceeding of IEEE 2011 ] 15

16 Multi-Gbps III-V 60GHz Transceiver 60GHz transceiver designs started with III-V processes, The possibility of multi-gb/s links is Confirmed, This transceiver achieved highest data rate: Direct conversion ASK/OOK modulation MMICs based on AlGaAs/InGaAs HJFET technologies Data rate : 3.5 Gbps link over 3m 20mm [ref5] K. Ohata, ISSCC mm TX RX RFIC Group 16

17 0.4 mm CMOS 60GHz RF Front-End 0.3 mm B Razavi, JSSCC In 2006, the First CMOS 60-GHz receiver circuits was reported, A quadrature down-converter was reported in 130-nm CMOS It incorporated an LNA and active mixers in 0.3 mm 0.4 mm, Gp = 28dB, NF = 12.5 db, RF=58~64 GHz, IF = 100 MHz, DC Power: 9 mw. RFIC Group 17

18 Multi-Gbps CMOS 60GHz Transceiver V Sorin, JSSCC The potential of 60-GHz links to achieve data rates as high as 6 Gb/s over distances of up to 2 m, RF: 55~64 GHz, Zero IF, Receiver consumes 101 mw and Transmiter consumes 131 mw from 1V supply, Transceiver Area: 0.81mm x mm RFIC Group 18

19 1.6 mm 1.72 mm SiGe Heterodyne Transceiver 9 GHz 17.5 GHz 500 MHz 3.4 mm 130-nm SiGe 630-Mbps link over 10 m 5.4Gbps with 16-element Array RX: 500-mW, TX: 800-mW Represented a very high level of integration on a 3.4 mm 1.7 mm chip. Incorporated Antenna in Package RFIC Group 3.4 mm RF : GHz LO : GHz IF : GHz B Floyd, JSSCC S. K. Reynolds, JSSCC A. Natarajan, JSSCC

20 Automotive Radar [ref10] LRR : long range radar 1-150m, 24 GHz, 77GHz, MRR : Medium range radar m, 24GHz, 77GHz, SRR : Short range radar 0.2-5m, 77GHz, RFIC Group Christian C. Enzet al., Springer,

22 Automotive Radars RFIC Group Christian C. Enzet al., Springer,

23 1.9 mm SiGe 24/79 GHz Automotive Radar 3.9 mm V. Jain, JSSCC mm SiGe, Transceiver dissipates 510mW/615mW for K/W band, Meets FFC power emission regulations, Demonstrates low-power single-chip implementation of dual-band radars for long/short range, RFIC Group 23

25 mm-wave Imaging T rx = T obj +T back +T atmos +T sky T obj = ϵ T atmos + ρ T surrounding ϵ : emissivity, ρ : reflectivity (ρ = 1-ϵ) Different object in the scene radiate different power Variations in radiated the power is used to generate scene images. RFIC Group 25

26 Active and Passive Imaging V Sorin, JSSCC 2009 T obj = ϵ T atmos + ρ T surrounding Active imagers work based on reflectivity of the objects in the scene while Passive imagers work based on emissivity RFIC Group 26

27 mm-wave Imaging applications Concealed weapons detection in security gate Visible Images RFIC Group mm-wave Images V Sorin, JSSCC 2009 [ref14] 27

28 mm-wave Imaging Aircraft navigation, landing, and Refueling in clouds, fogs, and dust. applications Visible Image in clear air Visible Image in dust [ref14] mm-wave Image in dust mm-wave image with 94-GHz Passive Ima V Sorin, JSSCC RFIC Group 28

29 mm-wave Imaging Receiver (Radiometer ) KTB R V out RFIC Group 29

30 mm-wave Imaging Receiver (Radiometer ) KTB PD V out KTB PD G PD, R B LF G PD, B PD B PD R B LF V out G PD and B PD are gain and bandwidth of pre-detector stages V out,detector = G PD R P in where G PD R is the Responsivity (W/V) of the receiver. Temperature resolution: T = B LF T 2 B PD + T 2 G PD G PD 2 + BLF NEP 2 K G PD B PD 1 2 RFIC Group 30

31 0.425 mm W-band SiGe Radiometer 0. 5 mm J. W. May, JSSCC mm SiGe BiCMOS Bandwidth: GHz Front-end Responsivity: 4MV/W Temperature resolution: 0.83 K DC power: 35mW RFIC Group 31

32 W-band SiGe Radiometers Integration demonstration 0.18 mm SiGe BiCMOS Bandwidth: GHz Front-end Responsivity: 285MV/W Temperature resolution: 0.48 K DC power: 787 mw (for 4 array) Z. Chen, JSSCC 2012 RFIC Group 32

33 Summary Applications with tens of GHz bandwith in mmw bands: Multi-Gbps wireless data communication Automotive radars Passive and Active Imagers Challenges: Near ft operation of transistors Low quality factor of passive components Sensitivity to parasitics RFIC Group 33

34 More Details for building blocks will be provided in the next talks. RFIC Group 34

35 LNA and Mixer Design in Millimeter wave 1

36 Outline MM-wave Passive design LNA design General LNA topology Design example of W-band LNA Challenges of mm-wave Mixer design Homodyne and Heterodyne Mixer Subharmonic Mixer Mm-wave Passive Mixer Layout Methodology 2

37 MM-wave Passive Design Wavelength is few millimeters. λ= C f ε eff so when signal traverse components with appreciable size of wavelength, their true nature is like wave.so distributed effect must be considered as a part of design process. Transmission lines provide better model accuracy than inductors due to well define ground planes. Ground shielded Coplanar waveguide (G-CPW) is widely used for matching of interconnection. Use of T-lines results noticeable increase in chip-area, alternatively Slow wave CPW are used. CPW (IBM SIGe BiCMOS process) SW-CPW 3

38 Passive components Folded Microstrip lines can also be used for inductor. Transformer based balun is widely used to make single ended to differential. Usually Baluns are routed with top two thick metal layers. Folded Microstrip line (90nm CMOS Tech.) Octagonal Transformer (center tapped) Square Transformer (SONNET Layout) Metal-insulator-metal (MIM) capacitor terminations must be considered as T-lines and modeled consequently. 3pF MIM Capacitor and its equivalent Model (0.13um SiGe BiCMOS process) 4

39 LNA Design in mm-wave Z s Z 0 = Z s Z sopt Z sopt Simultaneous conjugate matching and noise matching at LNA input. Multistage LNA: Inter-stage matching and stability. When Transistors operate close to their f T,lower gain and higher NF is observed.so devices should have high -current gain, cutoff frequency and breakdown voltage. 5

40 LNA topology Common gate topology: Two Serious Issues Matching and Gain degrades because of parasitic inductance between C G and its connections to gate and to ground. Needs very low impedance return path to ground Gain of CG stage is much lower at mmwave frequency. Reference: Bezad Razavi,Fellow,IEEE, Design of millimeter-wave CMOS Radios:A tutorial,ieee transactions on circuits and systems,regular papers,vol 56, No.1 Jan

41 LNA topology (cont.) Inductively degenerated cascode topology: Input matching depends on package parasitic. Exhibits a P All inductors must be integrated on chip. GND return path for L 1 and L 2 should display very low inductance. So careful layout consideration is needed. The pole (in the order of f T /2) adversely impact the gain and noise figure. 7

42 LNA topology (cont.) L s can be used as Series resonance, acts as inter-stage matching. Transformer feedback LNA Cascading three stage.. Wide Band impedance & noise matching Reference: Bezad Razavi,Fellow,IEEE, Design of millimeter-wave CMOS Radios:A tutorial,ieee transactions on circuits and systems,regular papers,vol 56, No.1 Jan

43 W-band LNA Four stage LNA, Gain=25 db, NF=8.3 db, 0.18um SiGe BiCMOS technology. Capacitance of GSG pad is absorbed by input matching network. To minimize parasitic inductance and ensure stability, C 2 is put as close as possible to the V b3 Q 2 base of Q 2. C 3 C 4, R 2 Local decoupling network for Q 1 Next stage power supply. To reduce footprint,lumped inductors are used instead of T-lines, as well as inter-stage matching. Reference: Zhiming cheng,chun-cheng wang,hsin-cheng yao,payam heydari, A BiCMOS W-band 2 2 focal-plane Array with On-chip Antenna, IEEE journal of Solid State Circuits,Vot.47,No.10,Octobar

44 Common base topology for BJT 245 GHz LNA, Gain=12 db, NF= 9.4 db, BW=26 GHz, Power consumption=28 mw Negative Resistance seen from emitter due to L p, Z E = (jω ω T)L p 2 (1) Common base can achieve higher gain, wider bandwidth and higher isolation than CE stage. Parasitic inductance at base introduces negative resistance at emitter. For stability, collector current is reduced (V be is reduced) to reduce ω T. Parasitic inductance L p can increase gain and lower NF. C byp, R byp form a low pass filter improve isolation between CB stages. Reference: Yanfei Mao,K. schmalz,j. Borngraber,J.C scheytt, A 245GHz CB LNA in SiGe,Proceedings of 6 th European Microwave Integrated circuits Conference 10

45 Challenges in Mixer Design in mm-wave Homodyne Mixer : High performance silicon base oscillator Mixer IF amplifier is very challenging in mm-wave frequency. so for direct conversion, LO is generated at a fraction of RF frequency and then use a multiplier prior to the frequency translation. Heterodyne Mixer: Double conversion mixer is used to relax oscillator and frequency divider requirement in mm-wave application. IQ Mixer: Generation of I Q phases of LO at mm-wave frequency and its balanced distribution is problematic. Quadrature operation typically degrades phase noise in mmwave frequency. n LO n N frequency multiplier Homodyne mixer 11

46 Challenges in Mixer Design (Cont.) LO distribution is difficult because of significant loss and mismatch in interconnects at high frequency. AT mm-wave frequencies, it is difficult to get large LO signal, so conversion gain is low with weak LO signal. Parasitic and layout consideration is an important issue for port to port isolation and stability. 12

47 Conversion Gain or Loss Conversion gain or loss is the ratio of the desired IF output (voltage or power) to the RF input signal value ( voltage or power). Voltage Conversion Gain r.m.s. voltage of r.m.s. voltage of the IF signal the RF signal CG= 2 π g m3r 1 g m1 C p 2 ω 2 +g m1 2 To increase Gain: Transmission line is used to reduce the parasitic at the common node of switches. Optimize Transconductor bias current for high gain. LO Improve Gain C p 13

48 Homodyne Mixer in Millimeter wave RC low-pass improves LO-IF Isolation Balun Balun Small Signal Equivalent Circuit RF=76 GHZ, CG=15 db, SSB NF=11.2 db, IIP3=8.5 dbm, Supply=5.5 V, SiGe:C technology. Reference: Saverio trotta,bernhard Dehlink,herbert Knapp,Klaus Aufinger, Thomas F. Meister,Josef Bock, Werne Simburger and Arpad L. Scholtz, Design considerations for low noise, Highly Linear Millimeter-wave Mixer in SiGe Bipolar Technology 14

49 Homodyne Mixer (Cont.) ω RF ω RF ) 2ω RF 2ω RF ) ω RF L 1 - C cs Filters 2ω LO Improve stability Nonlinearity of B-E junction creates harmonics. High C bc, L3-C1 represents very low impedance path for 2ω RF components generated by T1. The feedthrough 2ω LO to T1 can increase IM3,both 2ω RF, 2ω LO is highly attenuated by Low pass filter consisting of Ccs-L1,as RF and LO frequency are quite close. The effect of parasitic capacitance at node A is lowered by L1 which also improves NF. L2 and R1 improves stability. 15

50 Folded structure Distributed T-Lines For improved matching, Gain, NF RF=76.5 GHz, LO=38.25 GHz, CG with IF amplifier = 18 db, Supply 3.3 V, 200 GHz f T SiGe BiCMOS technology. RF Current in the input RF-pair can be optimized to improve NF and linearity. So Transistors are biased to get highest stable gain. LO switch quad are biased in low current to reduce noise injected by these transistors. RF pair is separated from Switching quad Voltage headroom available at the IF output help to avoid the clipping of mixer core. Reference: S.trotta,B.Dehlink,R. Reuter,Y.Yin,J.John,J.Kirchgessner,D.Morgan,P.welch,J.J.Lin,B.Knappenberger,I.To and M.Huang, A multi-channel Rx for 76.5GHz Automotive Radar Applications with 55dB IF Channel-to-Channel Isolation, 4 th European Micorwave Integrated Circuits Conference,

51 Heterodyne Mixer Two step down conversion scheme with RF =76-81 GHz, IF= GHz. CG=5 db,bw=10 GHz, NF=11 26 GHz Second quadrature LO is generated by dividing first LO by 2. Single frequency synthesizer can be used as first and second LO generation. 52 GHz Shielded T-lines are used for matching circuits because required reactance is small, also These lines has high isolation, reduced coupling to adjacent circuits. Second Mixer achieves 6dB conversion gain and BW=8 GHz in base 26 GHz Reference: Aydin babakhani,xiang Guan,Abbas komijani,arun Natarajan,Ali hajimiri, A &&GHz phased array transceiver with on chip antennas in Silicon:receiver and Antennas,IEEE journal of Solid State Circuit,vol.41,no.12,December

52 Subharmonic Mixer Second or Fourth Harmonic of LO is used Allow lower LO frequency, avoids multiple mixers, separate multiplier and associated circuitry Lower power consumption and Low Active area To increase the gain, desired harmonic mixing product should be maximized 18

53 Subharmonic Mixer :Topology 1 Ring oscillator RF= 50 GHz,LO=24 GHz, peak CG=9dB,NF=11.8 db from 3.3V supply, 0.12um SiGe BiCMOS process. Second Harmonic of LO is used. Completely Doubled Balanced Gilbert cell. This topology uses just two level of transistors hence lower supply voltage. Differential Two stage ring oscillator is used to generate quadrature phase. The some of the collector current of all switching pair has 2ω LO component indicating frequency doubling. Reference: R.M. kodkani and L.E. larson, An integrated 50GHz SiGe Subharmonic Mixer/downconverter with a quadrature ring VCO,IEEE

54 Subharmonic mixer: Topology 2 RF =122 GHz,LO=60 GHz,CG=23 db with +3 dbm LO power,ssb NF=12 db, SiGe:C HBT Technology. Second Harmonic of LO is used. Quadrature signal is applied to the stacked LO stages yields the product of twice the LO switching cycle. Reduced size 90 degree Hybrid coupler is used l = λ 8 60 GHZ = 315um to generate quadrature LO signal. C=90fF This topology Requires High supply voltage, Supply 6.6V,power consumption 150mW. 90 degree Hybrid Reference: A.M uller,m.thiel,h.irion,and H.-O.Ruoß, A 122 GHz SiGe Active Subharmonic Mixer. 20

55 Subharmonic Mixer: Topology 3 RF=245 GHz, LO=60 GHz, Conversion gain 0.7dB, NF=23 db, P 1 =-9.1 dbm. SiGe:C BiCMOS Technology, f T =300 GHz. Fourth Harmonic of LO is used. Transconductance mixing topology : Switching core may not work as a switch at frequency near f T. Reference: Yanfei Mao,Klaus schmalz,johannes Borgraber and john christoph scheytt, 245GHz LNA, Mixer and Subharmonic receiver in SiGe technology, IEEE transactions On Microwave theory and Technique,vol 60,no.12,december

56 Passive Mixer At very high frequency, Active mixers is complicated. No Conversion Gain, Sensitivity of Receiver can be Reduced Low Power consumption Better Linearity 22

57 Passive Mixer Single balanced Mixer. Doubled balanced Mixer. Balun RC low pass filter Matching circuit Matching circuit 65nm CMOS process. 67~75 GHz RF. 45nm CMOS IBM12SOI process. Wide band RF 130GHz-180 GHz. Conversion loss 12-13dB with 3dBm LO power. Reference: (1)16.9-mW 33.7-dB Gain mmwave Receiver Front-End in 65 nm CMOS, hun-hsing Li and Chien-Nan Kuo, 2012 IEEE (2)Double-Balanced GHz Passive and Balanced GHz Active Mixers in 45 nm CMOS, Ozgur Inac, Andy Fung2 and Gabriel M. Rebeiz, 2011 IEEE 23

58 Layout Methodology : Isolation LO-RF Isolation RF frequency=77ghz,lo Frequency=80GHz,130nm BiCMOS Technology. For X junction, reducing the width of path at crossing point allows minimizing the coupling effect. Reference:Low Power and High Gain Double-Balanced Mixer dedicated to 77 GHz Automotive Radar Applications, A. Mariano, T. Taris, B. Leite, C. Majek, Y. Deval, D. Belot, 2010 IEEE 24

59 Layout Methodology (cont.) Bias signals from large signal circuits (like the VCO and PA) must not be shared with sensitive circuit LNA. When bias lines of different blocks must be crossed, local ground plane should be placed between them to minimize their capacitive coupling. LNA should be placed as far as possible from frequency divider, PA. Capacitance of the metal planes contribute on-chip decoupling which prevents the propagation of high frequency noise between adjacent blocks.so power bias and ground planes are interlaced to increase their capacitance. Local GND plane used for isolation V DD V DD Circuit blocks should be surrounded by n-well and p-well isolation ring to prevent noise coupling between different blocks.. Metal planes for bias and Power distribution (SiGe Tech.) 25

60 Summary Different passive components are described in mm-wave range. All passive components and transistor interconnections should be verified by EM simulation at this high frequency. A number of techniques have been described to design LNA and mixer that ameliorate the challenges in mm-wave design. Homodyne mixer is difficult to implement in mm-wave because of High LO frequency. Heterodyne mixer needs multiple mixers. Subharmonic Mixer offers lower LO frequency but with lower gain. Systematic methodologies in layout, coupling among building blocks through the power lines and substrate are critical tasks that must be addressed. 26

61 Thank you 27

62 Back up 28

63 29

64 Passive mixer 1:power consumtion 16.9mW from 1 V supply IF is 8MHz is measured with LO power -2dBm,the highest gain is 33dB with Three stage LNA front end,nf of the front end is 12.2dB,IIP3 is -19dBm(overall) As Rd isncreases gain is also increasedused rd is 2k,but linearity degraed with high Rd,so it has a good trade off between gain and linearity. 30

65 Passive 2:CMOS SOI has ft 220GHz,balun loss 2dB,W/L=400um=16*1um/40nm,turn on R=16ohm,Vg=.3V=vth,for measurement Ghz gunn oscillator has been used with a multiplier 2.IF measurement is done by 26.5GHz spectrum analyzer.rf power has been swept upto 16dBm and no compression has been seen.square shaped balun is used for LO 31

66 Subharmonic mixer topology 1:.25um SGC25 IHP HBT,Ft is 200GHz,LO is 60Ghz,6.6V supply, Gain 23dB,NF=12dB, LO power=3dbm The quadrature signal that is applied to the stacked LO stages yields the product LO(I-Q) which is twice the LO switching cycle. 32

67 Subharmonic mixer topology 2: in run 2.13um BiCmos (SG13S) technology is used.ft and fmax is 250 and 300G.in run 3 (SG13G2) SiGe.13 um bicmos tech is used.fourth harmonic signal is function of conduction cycle. Q1 Q2 are biased at the edge of turn on voltage so that linarity is maximizedm. Measured result: IF 1GHz,conversion gain <5Db,NF 39dB 1dB compression point -9dBm. 33

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69 IQ Mixer IQ mixer:low power is the goal so transformers are used,telescopic cascode structures are avoided.the input is amplified by three stage LNA.Q5 Q6 acts as power active power splitter from LNA.G5 G6 are biased at peak Ft current. Conversion gain 5db,1db compression is -10dbm,DSB NF is 18.5dB including the unity gain buffer. ~56mW power consumption 35

70 Double balanced over single balanced Increased linearilty Better suppression of spurious products High intercept point Good supply rejection Better IF isolation from LO and RF 36

71 Inductively degenerated cascode topology: Input matching depends on package parasitic. Magnetic coupling between L G and L 1 can alter Input matching so careful layout consideration is needed. A pole(in the order of f T /2) is introduced at node P, thereby adversely impact the gain and noise figure in mm-wave. 37

72 Voltage Controlled Oscillators for mm-wave Application

73 Outline Design of LC cross-coupled VCO Phase Noise of LC-VCO Methods to create quadrature signals Cases of Quadrature VCOs for mm-wave application Conclusion 2

74 Criteria for Oscillation X + + H(jw) Y Closed loop transfer function Self-sustaining oscillation at frequency ω 0 if Barkhausen s criteria for oscillation at ω 0 1. Gain =1 2. Total phase = N 2π 3

75 Resonator-Based Oscillator Cancel out loss in tank with negative resistance element 4

76 LC- Voltage Controlled Oscillator Vcont Variable capacitor (varactor) controls oscillation frequency by adjusting Vcont. Parasitic capacitance cannot be removed. This capacitance lowers frequency tuning range. 5

77 MOS Varactor Consists of a reverse biased diode junction Variable capacitor formed by depletion capacitance Capacitance drops as roughly the square root of the bias voltage Easily integrated in CMOS Q is relatively low in the transition region. low tuning range (< +/-10%) 6

78 Improved Varactor Can achieve high Q + wide tuning range High Q metal caps for coarse tuning Low Q MOS varactor for fine tuning 7

79 Phase Noise Leeson s equation Flicker noise White noise Device noise Phase noise can be reduced by: 1) Increasing the Q of the LC tank. 2) Increasing the output voltage swing. 3) Reducing the effect of the bias transistor 1/f noise upconversion. 4) Reducing transistor noise. 8

80 Phase Noise due to Varactor Q of varactor at different frequencies 15GHz 60GHz As operation frequency increases, total quality factor of LC tank decreases. 1 = Q Total Q L Q C That is, phase noise becomes worse. 9

81 Typical LC-VCO in Triode Region M1: triode M2: off M1: off M2: triode The tank Q falls twice each period. Active device noise factor > γ cf.) F min = 1+γ at boundary b/w current limited and voltage limited regimes Lower current conversion efficiency 10

82 Tail Current Noise Filter Vs [Hegazi, JSSC 2001] Vs is twice oscillation frequency. Choose value of L T to resonate with C T and parasitic capacitance at 2ω 0. The filter prevents the switching FET in triode region from loading the resonator and lowering its Q. The switching FET pair will not upconvert its flicker noise into phase noise. 11

83 Class-C Oscillator [Mazzanti, ISSCC 2008] Class-C to avoid triode region Q preserved Better current conversion efficiency Minimized noise factor 12

84 Quadrature Signal Generation-(1) 2f GHz OSC Divider f GHz Frequency Division Simple architecture Poor phase noise (PN of 2f GHz OSC) Frequency limitation poor I/Q mismatch Cross-coupled QVCO Simple architecture (small area) Good I/Q accuracy Poor phase noise (in general, -85dBc/Hz@1MHz offset, 60GHz) Frequency limitation 13

85 Quadrature Signal Generation-(2) VCO w/ PPF or HC Low power consumption Poor phase noise I/Q mismatch f/n GHz OSC f GHz OSC Nth-harmonic Injection Locked QVCO Good phase noise PN@f/N GHz OSC + 20logN worse I/Q mismatch Narrow locking range 14

86 Cross-Coupled QVCO Prior Art-(1) Parallel QVCO Simple Good I/Q mismatch (in general, < w/o LC mismach) Poor phase noise (in general, -85dBc/Hz@1MHz offset, 60GHz) Two stable modes Bottom-Series QVCO Simple Good I/Q mismatch (similar to parallel QVCO) Limited voltage headroom Limited tuning range in mm-wave frequency 15

87 Cross-Coupled QVCO Prior Art-(2) Superharmonic Coupling QVCO Good phase noise Poor phase mismatch Need extra transformer Ex) PN= offset, 5GHz Phase error= [S. Gierkink, JSSC 2003] Magnetically-Coupled QVCO Good phase noise Need careful design(coupling coefficient K) Ex) PN= offset, 60GHz [U. Decanis, JSSC 2011] 16

88 Case of VCO w/ PPF or HC Hybrid Coupler LO signal generation using push-push VCO To improve phase noise 60GHz PN= 30GHz PN + 6dB Good phase noise (-95dBc/Hz@10MHz offset, 62GHz) Single ended output of VCO I/Q mismatch (5 phase error@58-65ghz) 60GHz 30GHz 30GHz [C. Marcu, ISSCC 2009] 17

89 3 rd -harmonic Injection Locked QVCO-(1) [W. Chan, JSSC 2008] Quadrature injection locking tripler Locking range: 56~65GHz I/Q polyphase filter for multiphase injection Good phase noise Phase + 9.5dB 1MHz offset, 60GHz 18

90 3 rd -harmonic Injection Locked QVCO-(2) [A. Musa, JSSC 2011] Quadrature injection locking tripler Single injection locking type narrow locking range Dual injection of tripler to improve injection locking range (58~65.4GHz) Good phase noise Phase (106dBc/Hz) + 9.5dB -95dBc/Hz@1MHz 19

91 Summary Reduce phase noise of VCO. High Q of varactor: coarse & fine controls Low noise factor: tail noise filter, class-c VCO Create quadrature signals for mm-wave applications. Good phase noise: 3 rd -harmonic injection locked QVCO, magnetically-coupled QVCO, push-push VCO with I/Q filter Considerations: phase noise, locking range and I/Q phase mismatch, power consumption 20

92 Phased Array History, Benefits and Architectures /RF Group 1

93 Outline Phased Array History, Benefits and Architectures Phased array metric and architectural study Mm-Wave Phase Shifter and Phased Array IC Design /RF Group 2

94 Outline What is a phased array? Why an array??? Case Study: A 60 GHz WPAN link budget Phased array versus timed array /RF Group 3

95 What is a phased array? A phased array electronically modifies the direction of transmission or reception of the electromagnetic beam. By introducing a variable time delay Time delay equal to dsinθ in /C. /RF Group 4

96 What is a phased array? Additional power gain of N 2. AF is lower for other angles of incidence, Spatial Selectivity. /RF Group 5

97 Why an Array??? A 60 GHz WPAN Link Budget: Antenna G : 5 db Path loss for a 10 m link is 88 db at 60 GHz Antenna G : 5 db Transmitter OFDM (BW:325 MHz) Receiver NF= 10 db 60 GHz CMOS PAs P 1-dB : 6 dbm (6 dbm back off) Transmitted power is around 0 dbm. P noise = log (325)+ NF= -79 dbm P RX = =-93 dbm. This CMOS-based WPAN link budget is deep in the negative SNR regime by 14 db!!! 6

98 Phased array techniques can come to the rescue 8-channel phased array on the transmitter side, gain enhances by 18 db. A 4-channel receiver phased array enhances SNR by 6 db. The SNR is boosted to a positive 10 db /RF Group 7

99 Why an Array??? Application Typical Range Array Size Conventional (>50 years) Military Radar Radio Astronomy Long Range (> 1km) Large ( ) Why an Array? Focused, High-Power Beam Multiple, Simultaneous Beams Spatial Interference Cancellation SNR Improvement in RX Driver Performance Size Cost Emerging ( 5 years) Wireless Comm. Automotive Radar Short Range (< 100m) Small (4-64) SNR Improvement in RX Relaxed PA Requirement Link Reliability (Comm.) Spatial Selectivity (Radar) Cost Size Power Consumption Realization Technology Module-based III-V Single Chip Silicon /RF Group 8

100 Why an Array??? Phased Array Provides: SNR Improvement Relaxed PA Requirement Focused, High-Power Beam What We Need Link Reliability Spatial Selectivity /RF Group

101 Phased Arrays versus Timed Arrays A phased array modifies the direction of transmission/reception of the electromagnetic beam by introducing a variable time delay. Integrated variable time delay blocks are difficult to implement in practice, particularly on silicon. In narrowband systems, the required variable time delay is often approximated with a variable phase shift, and the variable delay elements are replaced with phase shifters. /RF Group 10

102 Phased Arrays versus Timed Arrays The validity of the delay-phase approximation in phased arrays naturally depends on the instantaneous bandwidth!!! Array-induced Inter-Symbol Interference is a direct result of this approximation. Another reason to go to mmwave frequencies 5GHz of ISI-free bandwidth can easily be achieved in a 60GHz phased array, but would require a true-time-delay implementation if deployed in the 3-10GHz frequency range. /RF Group 11

103 Summary Phased array provides: SNR improvement. Spatial selectivity. Focused high power beam. For narrowband signals, the required variable time delay is often approximated with a variable phase shift. The phase-shifters can be incorporated in different parts of the transmitter/receiver chain. This results in three distinct phased array architectures. RF Phase-shifting, LO Phase-shifting, Digital Arrays 12

104 13

105 Conventional phase array architectures The phase-shifters required to achieve phased-array functionality can be incorporated in different parts of the transmitter/receiver chain. This results in three distinct phased array architectures RF Phase-shifting LO Phase-shifting Digital Arrays /RF Group 14

106 1) RF Phase-shifting Signals in the various channel are phase-shifted and combined in the RF domain. After combiner the receiver path can be configured as conventional receivers (heterodyne, homodyne or other image rejection architectures). /RF Group 15

107 1) RF Phase-shifting The most widespread phased-array architecture because of insulating a larger portion of the receiver chain from strong, in-band from undesired direction interferers. The main advantage: The dynamic range requirements on the mixer and the blocks that follow it are alleviated. The main challenge: Is the implementation of RF phase-shifters in silicon. (Passive- active) /RF Group 16

108 2) LO Phase-shifting /RF Group 17

109 2) LO Phase-shifting The advantage The nonlinearity, loss and the noise performance of the phase-shifters no longer have a direct impact on the system performance. Performance requirements on LO-path phase shifters are more relaxed consume less area/power. Disadvantage: Mixers must have sufficient dynamic range to withstand the interferers. Routing of strong LO in different paths. /RF Group 18

110 3) Digital Arrays /RF Group 19

111 3) Digital Arrays In this architecture each channel is digitized using an (ADC) and the bits of all channels are then processed using a Digital Signal Processing unit (DSP), where the spatial filtering is performed. The main advantage: Is its versatility and flexibility. Such phased arrays are extensively used in the cellular-phone industry. Disadvantage : RF mixer and ADC of each channel and the DSP unit must have sufficient dynamic range to handle the interferers. The entire RF chain is replicated for each channel which results in a rather powerhungry design. /RF Group 20

112 Comparative View of the Conventional Architectures /RF Group 21

113 Conclusion Using phase array architectures provides SNR improvement, spatial selectivity, and relaxes PA requirements. In RF phase shifting the dynamic range requirements on the mixer and the blocks that follow it are alleviated. In LO phase shifting the nonlinearity, loss and the noise performance of the phase-shifters no longer have a direct impact on the system performance. Different DSP algorithem can be used to perform spatial filtering. /RF Group 22

114 /RF Group 23

115 Phased Arrays versus Timed Arrays /RF Group 24

116 Phased Array Metric & Architectural Study Hedieh Elyasi Dr Kwang Jin Koh Group ECE Dept. Virginia Tech 1

117 OUTLINE Characterization of phased array Phased array architectures Linearity Comparison of different architectures Conclusion 2

118 Characterization of phased array Why phased array characterization is important for us? It makes design of complicated structures easy. P in G 1, NF 1, TOI 1 P out,1 Allowing fast characterization of the BFN. To have better understanding of P in G 2, NF 2, TOI 2 P out,2 system performance, P out specifications of the whole antenna can be evaluated. Gain P in G m, NF m, TOI m P out,m NF Linearity SNR 3

119 Gain P in G 1 P in G 1 P in ( M G m gain for each branch 2same ) P in LNA Phase shifter VGA G 2 P in G 2 + m=1 = P in M 2 G Power Combiner P in G m P in G m Total Power Gain G total = MG G total in db = G in db +10log 10 M 4

120 Noise Figure S in N in Input referred noise S in N in G 1, F 1 G 2, F 2 M ( G m S in m=1 + M S m F m ) 2 F total = (S N ) in M ( S N ) out Considering all branches has same gain (G) and noise factor (F) m=1 ( S N ) in S in N in G m, F m S m = S in G m N m = S mf m (S/N) in + F total = M2 GF M 2 G = F NF total = NF 5

121 Signal to Noise ratio S in G 1 N in S in G 1 N in G 1 Considering same signal and noise at output of each branch; M S in N in G 2 S in G 2 N in G 2 S in ( m=1 M G m ) 2 ( S N ) out= (M S m) 2 MN m = M ( S N ) m N m m=1 S in G m Output SNR ( S N ) out= M ( S N ) m N in S in G m N in G m ( S N ) out in db = ( S N ) in in db +10log 10 M 6

122 Linearity TOI m = 2 +P in db P 1 When we add all branches together, will not change because both P 1 and P IM3 are increased by a same number in db. P IM3 db So difference will be constant. 2ω 1 ω 2 ω 1 ω 2 2ω 2 ω 1 But! We have M branches with P in input power. TOI total = 2 + P in db +10 log 10 M TOI total =TOI+10 log 10 M 7

124 Phased Arrays Architectures 1. Phased Arrays based on feed network design parallel-fed Arrays Series-fed Arrays mm-wave PHASED ARRAY TRANSMITTER MICROWAVE PHASED ARRAY RECEIVER 2. Phased Array based on phase shifter stage PHASE SHIFTER RF Phase Shifting S LO Phase shifting Digital Phased Arrays 9

125 RF Phase Shifting Signals at the antenna elements are phase shifted and combined in RF domain. The combined signal is then down-converted to baseband using heterodyne or homodyne mixing. 10

126 RF Phase Shifting Advantages only one mixer is needed No need of LO signal distribution Mixer sees high directivity pattern Most compact architecture among RF RF phase shifter RF combiner other phase array designs (lower power, high linearity). LNA IF Insulation of a larger portion of the receiver chain from interference. Dynamic range of mixer can be more relaxed. RF RF without Interferer RF LO Widely used (since 1950) 11

127 RF Phase Shifting RF-scanning array is favored by industry: LM, Boeing, Teledyne, IBM, MTK, Intel, Disadvantages Implementing high performance phase-shifters at RF frequencies. Excessively lossy property of passive phase shifters. Low dynamic range property of active phase shifters at high frequencies. 12

128 LO Phase Shifting Tuning the phase of LO signals would translate into changing the phase of RF signals. 13

129 LO Phase Shifting Advantages: The loss, nonlinearity, bandwidth, and the noise performance of the phase-shifters would not have a direct impact on the overall system performance. RF IF phase shifter IF combiner RF LNA IF Disadvantages: Requiring a large number of mixers RF with Interferer LO IF + Mixer Intermod. (RF+interferer) Overall complexity and power consumption could be higher than RF-scanning phased array. *LO-phase shifting is equivalent to IF-phase shifting 14

130 Digital Phased Arrays The signal is digitized using an ADC and the digital signal are then processed using a DSP. Disadvantages: Interference emanating from undesired directions is not canceled out after signal processing All the elements must have sufficient dynamic range Power consumption is relatively high in this architecture. 15

131 Digital Phased Arrays Advantages: Multifunction capability such as creating many beams. An extensive variety of complex, signal-processing algorithms can be implemented using DSP units. Multi-beam Multiple-input-multiple-output (MIMO) Capability of distinguishing among desired signals, multipath and interfering signals, as well as demonstrating their directions of arrival. Can adaptively update their beam patterns, so as to track the desired signal with the beam s main lobe and track the interferers by placing nulls in their directions. 16

133 Antenna Array factor Array factor: useful method for predicting the spatial pattern of antenna array independent of the details of the element pattern. Assumption: Element pattern is Omni-directional allows greatest steering range. N 1 AF ψ = e jmkd(sinψ sinψ RF) n=0 k = 2π/λ, d is spacing between elements 18

134 Linearity in Single RF Channel Conventional case: IM3 = ( 3 4 )G 3V RF 3 If we have two tones of RF and JM with same frequency; 1,n = 2 RF,n JM,n LO,n We will have two answers for IM3 2,n = 2 JM,n RF,n LO,n we should consider maximum (worst case). Assumptions: Same LO, RF, JM frequency and phase of RF signal and LO signal considered zero. 19

135 AF-IM3 LO-Scanned Arrays M AF IM3,1 ψ RF, ψ JM = e j(2 RF,n JM,n LO,n ) m=1 M = e jnπsin(θ JM) m=1 AF IM3,2 ψ RF, ψ JM = e j(2 JM,n RF,n LO,n ) = m=m m=1 M e j2nπsin(θ JM) 2 LO-scanning (N=2) 1.5 IM3,1 IM3,2 1 X: Y: G 1 = H 1 M 1 G 3 = H 1 3 M 3 + 2H 1 H 2 M 2 +H 3 M Jammer Angle (degree) 20 A. K. Gupta and J. F. Buckwalter, Spur free dynamic range prediction for phased array receiver, IEEE Tran. Antennas and propagation, vol. 60, no. 4, April

136 LO-Scanned Arrays TOI ψ RF, ψ JM = 4G 1 AF(ψ RF ) 3G 3 max (AF IM3,m (ψ RF,ψ JM )) =TOI G AF(ψ RF ) max ( AF IM3,m (ψ RF,ψ JM ) ) For a coincident jammer, the TOI of the LO-scanned array reduces to TOIG. where no or little IM3 rejection occurs where the intermodulation array factor effectively nulls the IM3 terms 21 A. K. Gupta and J. F. Buckwalter, Spur free dynamic range prediction for phased array receiver, IEEE Tran. Antennas and propagation, vol. 60, no. 4, April

137 RF scanned Arrays The beam formed in the RF path & IM3 terms are generated through two paths. TOI G 2 = TOI H 2 + N 2 H 1 2. TOI M 2 IM3 1 ψ RF, ψ JM = 3 4 V RF 3 [H 3 M 1 AF IM3,1 ψ RF, ψ JM + H 1 3 AF ψ RF 2 AF(ψ JM ) M 3 ] IM3 2 ψ RF, ψ JM = 3 4 V RF 3 [H 3 M 1 AF IM3,2 ψ RF, ψ JM + H 1 3 AF ψ JM 2 AF(ψRF ) M 3 ] When the mixer is perfectly linear and the LNA introduces all of nonlinearity in the receiver chain, it behaves as LO-scanned Array. A. K. Gupta and J. F. Buckwalter, Spur free dynamic range prediction for phased array receiver, IEEE Tran. Antennas and propagation, vol. 60, no. 4, April

138 RF scanned Arrays TOI 1 2 ψ RF, ψ JM = TOI G 2 1 N 2 AF(ψ RF)AF(ψ JM ) + TOI H 2 ( AF IM3,1(ψ RF, ψ JM ) AF(ψ RF ) 1 N 2 AF(ψ RF)AF(ψ JM )) TOI 2 2 ψ RF, ψ JM = TOI G 2 1 N 2 AF(ψ JM) 2 + TOI H 2 ( AF IM3,2(ψ RF, ψ JM ) AF(ψ RF ) 1 N 2 AF(ψ JM) 2 ) As the beam steered to 40, the TOI of the RFscanned array becomes slightly more sensitive at around -75 jammer angle. 23 A. K. Gupta and J. F. Buckwalter, Spur free dynamic range prediction for phased array receiver, IEEE Tran. Antennas and propagation, vol. 60, no. 4, April

139 Spurious Free Dynamic Range While the SFDR of an array is limited to the SFDR for a single channel, the LO-scanned and the RF-scanned arrays have different SFDR limits since the single channel of the RF-scanned array introduces an additional phase shifter. SFDR = 2 3 (TOI MDS in) MDS = N i F SNR min = KT f F SNR min F is noise factor for the receiver, k is Boltzman s constant, T is room temperature f is the receiver bandwidth. Gain [db] Noise Figure [db] TOI [dbm] LNA Phase Shifter Mixer Receive Chain (without phase shifter) Receive Chain (without phase shifter)

140 IIP3 in LO Scanning Array desired signal jamming interference desired signal jamming Output of each branch Intermodulation Distortion 0 90 Phase Phase M AF IM3,1 ψ RF, ψ JM = 0 TOI tot Final Output For even M (number of arrays) AF IM3,2 ψ RF, ψ JM = M TOI tot = TOI G AF ψ RF = M M Phase Note: For odd number of M, only AF IM3,1 ψ RF, ψ JM will change to -1. So the result will not change. 25 TOI or Third Order Intercept Point or IIP3 25

141 IIP3 in RF Scanning Array desired signal jamming interference desired signal jamming Output of phase shifter 0 90 Phase Phase For even M (number of arrays) AF IM3,1 ψ RF, ψ JM = 0 TOI tot = M AF IM3,2 ψ RF, ψ JM = M TOI tot = Final Output H AF ψ RF = M M 0 AF ψ JM = 0 Phase Note: For odd number of M, only AF IM3,1 ψ RF, ψ JM will change to -1. So the result will not change. 26

142 SFDR (db) Normalized SFDR Normalized Mixer-based LO-scanning Array N=2 N=8 N=64 N= Jamming Angle (degree) 27 27

143 TOI Envelope trend with increasing of N 28 28

144 TOI (dbm) TOI (dbm) TOI comparison Mixer-based (N=64) LO-scanning RF-scanning Mixer-based (N=128) LO-scanning RF-scanning Jamming Angle (degree) Jamming Angle (degree) While LO scanning offers no rejection to jammers, RF scanning offers superior SFDR across a broader range of jammer angle

145 Digitizing Array Nonlinearities in the analogue-to-digital conversion degrade the overall SFDR of the digitization process. All ADC possess nonlinearities due to the nonideal sample, hold operation and amplifier nonlinearities. Ʌ x t = x t + γx(t)[m x(t) ) M is the maximum modulus of x(t), γ measure of the departure from linearity, x(t) is the derivative of x t SFDR = 20 log 10 (2πfγδ 1 A 2 ) L. B. White, F. Rice, and A. Massie, Spurious Free Dynamic Range for a Digitizing Array, IEEE Tran. Sig. Proc., Vol. 51, No. 12. Dec

146 Conclusion In phased array system with consuming more power, complexity and, cost compared to single channel we have; Higher Gain Same Noise Figure Better Linearity SNR improvement While LO scanning offers no rejection to jammers, RF scanning offers superior SFDR across a broader range of jammer angle. 31

147 Thanks for your attention! 32

148 Mm-Wave Phase Shifter and Phase Array IC Design /RF Group 1

149 Outline Introduction- mm-wave phase shifter design Passive phase shifters Switched transmission line phase shifter The high-pass/low-pass phase shifter Reflection type phase shifter Active Phase shifters Conclusion Vector-Summing Phase Shifter Quadrature all-pass filters 90 hybrid coupler /RF Group 2

150 Outline PHASED ARRAY IC DESIGN PHASED ARRAY 12 GHZ IC-design, chip & board level verification PHASED ARRAY 44 GHZ IC-design & chip level verification MM-WAVE PHASED ARRAY TRANSMITTER MICROWAVE PHASED ARRAY RECEIVER PHASE SHIFTER CONCLUSIONS S 3

151 Introduction RF-SCANNED PHASED ARRAY IF (LO)-SCANNED PHASED ARRAY RF RF phase shifter RF combiner RF IF phase shifter IF combiner RF LNA IF RF LNA IF LO RF without Interferer RF RF with Interferer LO IF + Mixer Intermod. (RF+interferer) *LO-phase shifting is equivalent to IF-phase shifting Need 1 mixer (simple) Mixer sees high directivity pattern Widely used (since 1950) Need # N mixers (complex) Mixer sees low directivity pattern Limited applications For on-chip integration, RF phase shifting is much better (lower power, high linearity) RF phase shifting architecture meets backward compatibility with existing systems /RF Group 4

152 Passive Phase Shifters Switched transmission line phase shifter Multiple, quasi-distributed, transmission-line Π-sections, combined with MOSFET switches. This phase shifter has: Good linearity performance. The main challenge is: The loss associated with the MOSFET switches. Performance: 4 bit phase-shifter implemented in a 0.13μm SiGe BiCMOS technology. The insertion loss is 13dB from 30-38GHz. Phase error is less than 7. /RF Group Ref: B.W. Min, et al, Ka-Band BiCMOS 4-Bit Phase Shiftrer with Integrated LNA for Phased Array T/R Modules, IEEE/MTT-S, June,

153 Passive Phase Shifters The high-pass/low-pass phase shifter Phase Shift: Difference between the phase response of a high-pass path and a low-pass path. Each individual bit is designed for different phase differences. Good Linearity Performance The challenges: Losses in the passive elements and the switches. Performance: 5 bit phase-shifter implemented in a 200GHz SiGe BiCMOS technology, the insertion loss is 18dB from 8-12GHz. Absolute rms phase error is less than 8 M. Morton, et al Sources of Phase Error and Design Considerations for Silicon-Based Monolithic High Pass/Low-Pass Microwave Phase Shifters," IEEE Transactions on Microwave Theory and Techniques, Dec /RF Group 6

154 Passive Phase Shifters Reflection-Type Phase Shifter (RTPS) Includes: 4-port directional coupler and purely reflective (imaginary) loads. jx Phase of the output varies by varying the imaginary termination. The total phase shift: π/2 2tan 1 (Zo/X), Zo is the impedance to which the ports are matched. Zo C. T. Charles, et al A 2-GHz Integrated CMOS Reflective-type Phase Shifter with 675 Control Range," IEEE International Symposium on Circuits and Systems, May For a total phase variation of 180, the termination capacitance must vary from 0 to, cannot be realized with varactor. To maximize the achievable phase shift range, higher order terminations are employed, such as series LC networks. /RF Group 7

155 Passive Phase Shifters Reflection-Type Phase Shifter (RTPS) Good linearity performance. The main challenge is Loss Associated by Switch and TLs. Varactor Single resonated load (SRL) Transformed single resonated load (TSRL), Performance: 2GHz phase-shifter implemented in a 0.18 um CMOS process, phase change 343º. The insertion loss is -10dB, and noise figure is 19 db, for 0-1.8V operation. /RF Group 8

156 Active Phase Shifters Vector-Summing Phase Shifter Quadrature generation block. Variable-gain amplifiers Combiner. Phase of the output is tan 1 (A2/A1) The quadrature generation block can be implemented in a number of ways. Quadrature all-pass filters (QAF). 90 hybrid coupler. /RF Group 9

157 Vector-Summing Phase Shifter (Quadrature all-pass filters) Passive signal interpolation for quadrature vector synthesis! 1. Single-ended quadrature generation 2. Differential configuration Vin VOQ iin + VC - + VR - Vin+ L iin VL VOI VOI + VR=V in VL - + VR - VC VOQ Phasor Phasor diagram Q=1 C 2R VOI+ VOQ+ VOQ+ R C VOI+ VOQ+ VOI+ Vin+ Vin+ B A L Vin- VOI- VOQ- VOI- VOQ- Vin- Vin- VOI- VOQ- NOTE Step-1: 3-dB resonance Step-3: bandwidth extension (by removing L-C energy storage pair, de-q) All-pass filter with 3dB NF V V OI OQ TRANSFER FUNCTION V in 2 2ωo 2 s s - ωo Q 2 2ωo 2 s s ωo Q I-path Q-path 2 2ωo 2 s - s - ωo Q 2 2ωo 2 s s ωo Q ωol where, Q, ω R o 1 LC 4. Differential Quadrature All-pass Filter (QAF) 3. Elimination by series resonance Ref: K.-J. Koh etal, 0.13-mm CMOS phase shifters for X-, Ku-, and K-Band Phased Arrays, IEEE JSSC, Nov /RF Group 10

158 Vector-Summing Phase Shifter (Quadrature all-pass filters) Output Output- Output+ bias A Qin+ v, out II IQ Out 8xIref 2 Gilbert-cells 20xIref I/Q 28xIref VGA Active inductor save area -1 IQ tan Keep I Q +I I =constant II constant gain versus phase change Input Iin- L C 2R Qin+ II IQ Iin+ Qin- Qin+ Iin- Iin+ Qin- II IQ RF input I/Q Network (Quadrature All-pass Filter) Sb S D + - D1 D2 D3 D DI1 DI2 DI3 DI4 I - + Gain control (VGA) Q DAC S RF output Sb CAL Qin- SIM. X-BAND 0.18-mm CMOS Gain = 0 GHz IIP3 = 15 GHz I I +I Q =2.5 ma, Vdd=3.3 V Sign control 1:1 1:1 Control logic Control bits /RF Group 11

159 ACTIVE PHASE SHIFTER 4/5-BIT RELATIVE PHASES 4-bit relative phases (deg) Frequency (GHz) 5-bit relative phases (deg) Frequency (GHz) After DAC calibration (Relative phases referenced to 0 o -bit phase, RMS phase error < 5.6 GHz) NOTE Phase interpolation is an independent process of frequency Operational BW is limited by the I/Q network, i.e. the accuracy of I/Q network Phase can be easily calibrated using a high resolution DAC (not easy in passive design) First realization of integrated 5-bit active phase shifter in silicon achieving 6-18 GHz coverage (3:1 BW) /RF Group 12

160 Vector-Summing Phase Shifter (90 hybrid coupler) 90 o Hybrid Rat-Race 90 o Hybrid + + : LNA Compensates for the loss of phase shifter. &: Switch Amplifier (functioning as an active switch) These switches are used to select the appropriate quadrant that the two orthogonallyphased inputs create the desired phase. : VGA varies the amplitudes of two orthogonally-phased input signals to get the desired phase within the selected quadrant. /RF Group 13

161 Phase(S21) in degree 1-94 GHz Phased Array Front End S21,NF (db) S21 NF=8-9 GHz Frequency(GHz) Frequency(GHz) Continuous 360 o phase control (shown only 3-bit control here) S21: GHz These gain variation can be offset by adjusting VGA (not shown here) NF: 8-9 GHz /RF Group 14

162 2-120 GHz Phased Array Front End Phase(S21) in Degree S21,NF (db) S21 NF (11-12 GHz) Frequency(GHz) Frequency(GHz) Continuous 360 o phase control (shown only 3-bit control here) S21: GHz These gain variation can be offset by adjusting VGA (not shown here) NF: /RF Group 15

163 94 GHz Phased Array Front End: Layout Gnd VCC Vc1 1592μm Vc2 Vc3 Vc4 Vc5 Vc6 Vc7 Gnd VGA Gnd RFin Switch Amplifier Switch Amplifier Gnd RFout 600μm Gnd Gnd VGA 90º Hybrid Rat-Race Supply 2.5 V, Total current 44mA /RF Group 16

164 GHz Phased Array Front End: Layout 1592μm Gnd VCC Vc1 Vc2 Vc3 Vc4 Vc5 Vc6 Vc7 Gnd Gnd RFin Switch Amplifier VGA Gnd Switch RFout Amplifier 600μm Gnd VGA Gnd 90º Hybrid Rat-Race Supply 2.5V,Total Current 37mA 17

165 Conclusion Passive phase shifters have good linearity performance, but the main challenge is the loss associated with the passive elements and switches. Their physical sizes make them impractical for integration with multiple arrays in a commercial IC process, especially below K band frequencies (< 30 GHz). Active phase shifters can achieve a high integration level with decent gain and accuracy along with a fine digital phase control under a constrained power budget. The most challenging part of realizing active phase shifters is the quadrature generation block which can be implemented by quadrature all-pass filters (at lower frequencies) and a 90 hybrid coupler (at higher frequencies). /RF Group 18

166 PHASE ARRAY IC DESIGN PHASED ARRAY 12 GHZ IC-design, chip & board level verification PHASED ARRAY 44 GHZ IC-design & chip level verification MM-WAVE PHASED ARRAY TRANSMITTER MICROWAVE PHASED ARRAY RECEIVER PHASE SHIFTER CONCLUSIONS S 19

167 8-ELEMENT PHASED-ARRAY (12 GHZ, SCALABLE ARRAY) GaAs LNA Optional: depending on Freq, BW & NF Low-cost packaging solution Scalable board-level design 8-ELEMENT Si BEAMFORMER MIXER FILTER ADC 2-D MxN silicon phased array MODEM DSP DIGITAL DATA DIGITAL PHASE CONTROL Scalable to MxN system (SiGe BiCMOS) Utilize existing baseband processor (CMOS) (backward compatibility) 20

168 8 ELEMENT SI BEAMFORMER: PHASE SHIFTER RF input Input Active Balun I/Q Network (Quadrature All-pass Filter) Q I PHASE SHIFTER CORE Gain control (VGA) Sign control I Q DAC Output Active Balun Control logic CAL RF output OPERATION Balun provides differential signal I/Q network splits signal into I & Q vector signals VGA controls gain for I & Q path I/Q signals are added in V-domain (phase interpolation) DAC provides 4-bit phase control CAL calibrates DAC to get 5-bit phase resolution OUTPUT PHASE =tan -1 (Q / I) Control bits * The in/out balun stages will not be necessary for fully integrated differential systems Mostly active circuits DAC control Small chip area & Gain Fine accurate phase control & calibration 21

169 ACTIVE PHASE SHIFTER - SCHEMATIC 8xIref 20xIref 28xIref Output bias Qin+ Input L C 2R Iin+ Qin- Qin+ Iin- Qin- II IQ Sb S D1 D2 D3 D S Sb 4xII 4xIQ D 1:1 1:1 Ref: K.-J. Koh etal, 0.13-mm CMOS phase shifters for X-, Ku-, and K-Band Phased Arrays, IEEE JSSC, Nov

170 ACTIVE BALUN QAF ACTIVE PHASE SHIFTER CHIP PHOTO 0.18-mm SiGe BiCMOS process (Phase shifter: 0.18-mm CMOS) Chip size: 1.2 x 0.7 mm 2 (Phase shifter: 0.4 x 0.3 mm 2 ) ADDER (I/Q VGA) ACTIVE BALUN CALIBRATION (FOR 5-BIT) ACTIVE PHASE SHIFTER INPUT DAC / LOGICS OUTPUT Total current: 18.7 ma (V DD =3.3 V) 13% 1% Bias: 0.2 ma 4-BIT PHASE CONTROL 16% Input balun: 13 ma 70% Supported by DARPA SMART project ( ) Presented at the DARPA meeting & MTT-s 2010 Lockheed Martin bought the designs (schematic & layout), 2009 All pads are ESD protected (HBM rating: 3kV, 2A) 23

171 ACTIVE PHASE SHIFTER TEMPERATURE MEASUREMENTS RF input I/Q Network (Quadrature All-pass Filter) Gain control (VGA) Sign control I Q DAC RF output CAL Control logic Control bits RMS Phase Error (deg) C 50 C 75 C 100 C 5 4 < 1 o Frequency (GHz) RMS Gain Error (db) I & Q paths are biased with a reference PTAT circuit Output phase depends on I:Q gain ratio (not absolute gain) I & Q amplifiers track each other vs. PVT, resulting in low sensitivity to PVT RMS phase error < C 24

172 8-ELEMENT PHASED-ARRAY (12 GHZ, ARCHITECTURE) VCC (3.3 V) ADDRESS (3-b) CK (ENABLE) DATA (4-b) Integrate 8-CHs in SiGe ESD BANDGAP 3:8 ADDRESS DECODER 4-b REGISTER ARRAY DECODER DIGITAL CONTROL Integrate RF + DIGITAL 4-bit active phase shifter 2-step signal combining (active adders) RF CH-4 RF CH-5 ESD protection (3kV, 2A) RF CH-3 4-CH S 2-CH S 4-CH S RF CH-6 RF CH-2 RF CH-7 RF CH-1 RF CH-8 LNAB (LNA+BALUN) PHASE SHIFTER DIFFERENTIAL-TO- SINGLE (DTS) RF OUTPUT 25

173 QAF ADDER 8-ELEMENT PHASED-ARRAY (12 GHZ, CHIP PHOTO) CH-4 BANDGAP DAC & ENCODER ARRAY DECODER 4-CH S CH-5 METALLIC BARRIER 0.18-mm SiGe BiCMOS (Jazz SiGe120, 1P6M, f T =150 GHz) Area = 2.2 x 2.4 mm 2 Near perfect corporate-feed layout (E-length btw any input to output is identical) Metallic barrier: max CH-CH isolation V CC =3.3 V, I total =170 ma (561 mw, Active-S < 10%) CH-3 CH-6 Bias 2-CH S DTS CH-2 CH-7 LNAB PHASE SHIFTER 4-CH S CH-1 CH-8 Single channel: 17.6 ma (x8) SINGLE CHANNEL (ADDRESS: 000) OUTPUT (PORT-9) 26

174 8-ELEMENT PHASED-ARRAY (12 GHZ, GAIN, NF, MATCHING) Input/Output Return Loss (db) S99 simulation (SPECTRE) Frequency (GHz) 0 S11 <-10 GHz <-13 GHz Power Gain (db) GHz Average gain simulation (SPECTRE) NF Frequency (GHz) NF (db) < 5 GHz (Min. 3.9 GHz) Isolation (db) Isolation < -60 GHz output-to-input RMS Gain Error (db) RMS gain error < 0.9 GHz Frequency (GHz) Frequency (GHz) 27

175 8-ELEMENT PHASED-ARRAY (12 GHZ, PHASE, GROUP DELAY) 4-bit Phase Responses (deg) o -bit 0 o -bit (reference) Frequency (GHz) Group Delay (ps) Group delay = 175 GHz Variations < 25 GHz Frequency (GHz) 4-bit Relative Phases (deg) Near ideal constant phase GHz Frequency (GHz) RMS Phase Error (deg) RMS phase error: < 3 GHz < 5.7 GHz Accuracy ~ GHz Frequency (GHz) 28

176 8-ELEMENT PHASED-ARRAY (12 GHZ, CH-TO-CH VARIATION) CH-3 CH-2 CH-1 Measured S-parameters for 8 different channels for every 4-bit (16 phases) states!!! 4-CH S CH-4 CH-5 2-CH S OUTPUT (PORT-9) Comparison of 128 S-Parameters = 8 (channels) x 16 (4-bit phases) Excellent matching between array elements Major benefit in the on-chip integration CH-6 CH-7 CH-8 Phase Mismatch (deg) Gain Mismatch (db) RMS gain mismatch < 0.5 db RMS phase mismatch < 3 o Frequency (GHz) 29

177 6 cm (2.4 in) 8-ELEMENT PHASED-ARRAY (12 GHZ, CHIP-ON-BOARD, ANGLED-DIPOLE) 10 cm (3.9 in) l/4 ESD stub GND plane edge at the bottom 0.5l o (1.25 GHz) 50W T-line W=0.8 mm dummy antenna with 50W load ANGLED-DIPOLE SINGLE ELEMENT E-PATTERN dummy Bias & Digital Control Output HPBW:102 o 0.5l Rogers RT5880 Teflon substrate (e r =2.2, h=10 mils) ANGLED-DIPOLE ANTENNA: Wider beam width, Lower mutual coupling, Wideband S11 HPBW: 102 o, S11<-10 GHz, S21<-17 db Scan angle: +/- 60 o w/ 4dB drop in element factor dummy Ref: Y. A. Atesal, B. Cetinoneri, K.-J. Koh, G. M. Rebeiz, X/Ku-Band 8-Element Phased Arrays Based on Single Silicon Chips, 2010 IMS, May

178 6 cm (2.4 in) 8-ELEMENT PHASED-ARRAY (12 GHZ, CHIP-ON-BOARD, CHIP MOUNTING) 10 cm (3.9 in) ESD stub GND plane edge at the bottom 0.5l o (1.25 GHz) 50W T-line W=0.8 mm dummy antenna with 50W load SILICON PHASED ARRAY CHIP (2.2 X 2.4 mm 2 ) Coupling (db) BONDWIRE & COUPLING SIMULATION WITH HFSS Bias & Digital Control A4-A3 A4-A2 A4-A1 Output Rogers RT5880 Si Chip Teflon substrate (e r =2.2 h=10 mils) Duroid System GND VCC bias & digital control Digital control VCC Freq (GHz) Worst-case coupling < -17 db, bondwire inductance: 0.5 nh VCC Output port GND pedestal Ref: Y. A. Atesal, B. Cetinoneri, K.-J. Koh, G. M. Rebeiz, X/Ku-Band 8-Element Phased Arrays Based on Single Silicon Chips, 2010 IMS, May

179 8-ELEMENT PHASED-ARRAY (12 GHZ, BOARD MEASUREMENT SETUP) ANECHOIC ANTENNA CHAMBER GPIB CONTROL DUT GAIN & PHASE CONTROL 2.1m HORN ANT POWER METER DUT 2.1 m STANDARD GAIN HORN ANTENNA -5 dbm (125 mv) Friis TRANSMISSION EQUATION P P R T G T Horn ANT gain = 20 db Free space pathloss = db R: 2.1 m l: 2.5 GHz 2 l 4πR G R Phased array gain = 41 db Channel gain (20 db) Array factor (18 db) Antenna gain (3 db) dbm (13 mv) G R dbm (118 mv) FREE SPACE LOSS G T -25 GHz (12.5 mv) 32

180 15 o 19 o 26 o 8-ELEMENT PHASED-ARRAY RX (12 GHZ, BOARD MEASUREMENT) MEASURED GHZ MEASURED GHZ Scanned from -60 o to 60 o Element factor causes 3-4 db drop at 60 o HPBW: 15 o -scan, 19 o -scan, 26 o -scan Excellent agreement with simulations No-true-time delay on each element Slight beam 60 o - scan angle Instantaneous BW limited to GHz (D=1.2 GHz, 10%) First system-level (w/ antenna) demo of an X-band array based on a single silicon chip! 33

181 AREA COMPARISON: SINGLE VS 8-ARRAY LNA SINGLE ELEMENT 3.5 mm 8 ELEMENTS + DIGITAL 2.4 mm PHASE SHIFTER 3.8 mm Ref: Comeau etal (Georgia Tech), A SiGe Receiver for X-Band T/R Radar Modules, IEEE JSSC, Sept Integration (A=13.3 mm 2 ): LNA + Phase shifter + bias c.k.t. (single element: analog) COMPARE (8-element array is 40% size of the passive single-element) 2.2 mm Ref: K.-J. Koh etal, An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-mm SiGe BiCMOS Technology, IEEE JSSC, June 2008 Integration (A=5.3 mm 2 ): 8 LNAs + 8 Phase shifters + bandgap (8 elements: analog) + Array decoder (digital control) 34

182 PHASE ARRAY IC DESIGN PHASED ARRAY 6-18 GHZ IC-design, chip & board level verification mm-wave PHASED ARRAY TRANSMITTER PHASED ARRAY 44 GHZ IC-design & chip level verification CONCLUSION MICROWAVE PHASED ARRAY RECEIVER PHASE SHIFTER S 35

183 16-ELEMENT mm-wave PHASED-ARRAY TX (LARGE ARRAY, 3-D INTEGRATION) PROJECT: DARPA SCALABLE MILLIMETER-WAVE ARRAY TECHNOLOGY (SMART, ) 16 X PATCH ANTENNAS SUPER-TILE (20x20=400 elements) ONE TILE (SUB-ARRAY) (4x4 elements) Q-Band satellite Q-band satellite comm. (43-45 GHz, l/2=3.4 mm) Large array: 20x20 elements Microstrip antenna size = 3.4x3.4 mm 2 ANTENNA FEEDS & FILTERS 4X PA InP Power amplifier: 1.5W, 30% PAE Heat sink POWER AMPLIFIERS (16 X InP HBT) w/ heat spreading chamber (MEMS) RF DISTRIBUTION LAYER (microstrip T-lines) SIGE BICMOS 16-ELEMENT BEAMFORMER (THIS WORK) Integrate 1 sub-array (4x4) in a single package (Area < 3x3 cm 2 ) Multi-layered integration in a single package TILE-BASED 2-D LARGE ARRAY (20X20) CONSTRUCTION ONE TILE (SUB-ARRAY): 4X4 ELEMENT, ONE SUPER-TILE: 5X5 TILES 36

184 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, ARCHITECTURE) ADDRESS (4-B) DATA (4-B) ARRAY DECODER CK (ENABLE) 44 GHz satellite comm. application DIGITAL PHASE CONTROL Integrate 16 elements (4x4) PA (III-V) (INP) AND and ANTENNA Antenna ARRAY array (external) (EXTERNAL) RF INPUT PA (III-V) (INP) AND and ANTENNA Antenna ARRAY array (external) (EXTERNAL) 50-W DRIVER ACTIVE BALUN PHASE SHIFTER 1:2 1:8 1:8 LOSS COMPENSATION AMPLIFIER (LCA) BIAS PTAT DIFFERENTIAL T-LINE (70 W) T-LINE (50 W) PA (INP) AND ANTENNA PA (III-V) and Antenna array (external) PA (INP) AND ANTENNA ARRAY (EXTERNAL) PA (III-V) and Antenna array (external) ARRAY (EXTERNAL) Corporate feed architecture - Active balun, 1:2 active, 1:8 passive Single channel elements - LCA: compensate 1:8 division loss - 4-bit active phase shifter - 50-W driver drives external PA Array decoder - control each channel independently Ref: K.-J. Koh etal, A Millimeter-wave (40-45 GHz) 16- Element Phased-Array Transmitter in 0.18-mm SiGe BiCMOS Technology, IEEE JSSC, May 2009 SIGE Q-BAND TRANSMIT BEAMFORMER 37

185 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, CHIP PHOTO) CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER ACTIVE BALUN ARRAY DECODER LCA 1:2 ACTIVE PTAT METALLIC BARRIER 1:8 PASSIVE T- JUNCTION CH-9 CH-10 CH-11 CH mm SiGe BiCMOS technology - 1P6M, f T =150 GHz Size: 2.6 x 3.2 mm 2 (overall) Near perfect corporate-feed layout - E-length is identical for all channels Metallic barrier - Grounded via stacks from M1-M6 - Decrease ch-to-ch coupling Current consumption: 724 ma (5 V, 3.6 W) RF INPUT Active Balun=5 ma 1:2 Active =15 ma CH-4 CH-13 CH-3 CH-14 CH-2 CH-1 1:8 PASSIVE T-JUNCTION CH-15 CH ma x 16 CH =704 ma - LCA: 22 ma - Phase shifter: 8 ma - 50-W dirver: 14 ma 38

186 LCA (loss compensation amplifier) 12.5 um 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, 1:8 T-JUNCTION) CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER ARRAY DECODER LCA ACTIVE BALUN 1:2 ACTIVE 1:8 PASSIVE T- JUNCTION (0.15X1.15 mm 2 ) = 2% PTAT SIGE METAL STACKS oxide M3 M1 CH-9 CH-11 CH-12 M6 M5 M4 M2 M3 M1 CH-10 Si-sub CH W-cm SHIELDED BROADSIDE-COUPLED DIFF-T-LINE Al (M6) Top metal + Vias 2 um - M5 + + M4 M3 1.6 um 1.9 um GND (M1) Perfectly shielded (no coupling btw T-lines) Allow compact integration of many diff T-lines 1:8 TEE-JUNCTION DIVIDER - RF INPUT CH-4 CH-3 CH-13 CH-14 1:2 50 W 12.5 W 25 W 50 W CH-2 1:8 PASSIVE T-JUNCTION CH-15 CH-1 CH-16 Quarter path Division loss: 18 db + parasitic loss (~ 3 db) 39

187 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, COAXIAL T-LINE) ARRAY DECODER SHIELDED BROADSIDE-COUPLED DIFF-T-LINE Al (M6) Top metal CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER RF INPUT ACTIVE BALUN LCA 1:2 ACTIVE PTAT 1:8 PASSIVE T-JUNCTION (0.15X1.15 mm 2 ) = 2% CH-9 CH-10 CH-11 CH-12 M + + Vias mm 2 um M M 1.9 mm 3 GND (M1) Perfectly shielded (no coupling btw T-lines) Allow compact integration of many diff T-lines ODD-MODE E-FIELDS EVEN-MODE E-FIELDS CH-4 CH-13 CH-3 CH-2 1:8 PASSIVE T-JUNCTION CH-14 CH-15 W=3 mm: odd-mode impedance=50 W (HFSS sim) Most fields (> 95%) are confined btw diff-t lines Measured loss: 3 db / 0.5 GHz CH-1 CH-16 40

188 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, MEASUREMENT) PARAMETER Technology Supply voltage Current consumption Frequency band Phase resolution Input return loss Output return loss Power gain (ave) Maximum output power Phase error (RMS) Gain error (RMS) Output P 1dB Phase mismatch (RMS) Amp. mismatch (RMS) Isolation (CH-to-CH) Array factor directivity Chip area RESULTS 0.18-mm SiGe BiCMOS (Jazz SiGe120, 1P6M) 5 V (analog), 3.3 V (digital) I bias =720 ma (44 ma per channel) Q-band (3-dB BW: GHz) 4-bit (accuracy > 5-bit) < GHz < GHz GHz GHz < GHz < GHz GHz < GHz (between all channels) < GHz (between all channels) < GHz 12 db (16-element) 2.6 x3.2 mm 2 BEAM PATTERN BASED ON MEASURED S-PARAMETERS (16 S-PARA X 16 CHANNELS= 256 S-PARA) Scan angle (deg) Broadside scan Dot: Ideal Red: Measured S-para 45 o -scan ASSUMPTION Isotropic radiator, uniform array spacing, d=l/2 Ideal 45 o -scan: o (= 360 o x d/l x sin45 o ) 41

189 CONCLUSIONS Provide a low-cost phased array solution for RF and mm-wave defense & commercial applications First implementation of All-RF (RF-scanning) Si phased array IC including system-level demonstration Phase shifter Si on-chip array Antenna board verification Successful technology transfers to DoD industries (Boeing, Lockheed Martin, Raytheon, Teledyne, NG) Phase shifter Lockheed Martin (JSSC 2007) X-band, 8-element Rx Q-band, 16-element Tx Lockheed Martin Raytheon, Boeing Northrop Grumman (JSSC 2008) Teledyne (Rockwell) (JSSC 2009) Q-band, 4-element Rx Lockheed Martin Boeing (T-MTT 2008) Designs can be extended for high data-rate wireless systems at mm-wave frequencies (60 GHz wireless comm., > 100 GHz high data rate mm-wave comm. ) SiBeam, IBM, MTK, Intel all use now the All-RF based phased array architecture. First 16-element integration in silicon First mm-wave (>30 GHz) on-chip silicon array Inspire industries (DoD & Commercial) The Most Significant Achievement in 2008 DARPA Special WAR REPORT to Pentagon Team of The Year Award in 2010 from Teledyne Scientific Corp (Rockwell) 42

190 BACK-UP SLIDES 43

191 8-ELEMENT PHASED-ARRAY (12 GHZ, SCHEMATICS) RF INPUT 2-CH S 4-CH S (COMBINER) CH S ACTIVE PHASE SHIFTER SINGLE CHANNEL: LNAB (LNA + BALUN) + PHASE SHIFTER 2-CH S Emitter-coupled diff-pair Single-to-differential conversion L-C input matching 2 nd stage diff amp: CMRR Signal -S in current domain Binary fashion signal -S Wideband signal-s NMOS-based push-pull 2-CH S (COMBINER) DTS (PUSH- PULL) RF OUTPUT CH #1 CH #2 CH #3 CH #4 4-CH #1 4-CH #

192 8-ELEMENT PHASED-ARRAY (12 GHZ, CH-TO-CH COUPLING) Leakage signal undergoes different phase delay causing signal errors!!! 4-CH S CH-4 CH-5 SIGNAL ERROR DUE TO COUPLING (@ 12 GHZ, GAIN=20 db) CH-3 CH-6 2-CH S COUPLED LEAKAGE CH-2 2 CH-7 CH-1 1 CH-8 LNA OUTPUT (PORT-9) GROUNDED METAL BARRIER Amplitude Error (db, RMS) Mag. error < 0.4 db Phase error < 4 o Frequency (GHz) Phase Error (deg, RMS) Coupling causes amplitude & phase errors which could be serious in silicon Measured errors are negligible due to high isolation layout, e.g. metallic barrier 27 45

193 4-ELEMENT mm-wave PHASED-ARRAY RX (44 GHZ, ARCH & CHIP PHOTO) PHASED-ARRAY RX BLOCK DIAGRAM CHIP PHOTOGRAPH ADDRESS (2-b) DATA (4-b) CK (ENABLE) CH-1 CH-2 CH-3 PTAT LNA BIAS ARRAY DECODER DIGITAL PHASE CONTROL WILKINSON COMBINER (2-STAGE) DRIVER l/4 l/4 l/4 l/4 RF OUTPUT CH-4 CH-3 CH-2 LNA PTAT PHASE SHIFTER ARRAY DECODER DRIVER CH-4 PHASE SHIFTER l/4=1.045 GHz FOR HIGH LINEARITY CH-1 2-STAGE WILKINSON SiGe BiCMOS (f T =150 GHz), Area=1.4x1.7 mm

194 4-ELEMENT mm-wave PHASED-ARRAY RX (44 GHZ, WILKINSON COUPLER) Isolation (db) Loss (db) Return loss (db) WILKINSON COUPLER MEASUREMENTS -10 Wilkinson I -20 S11 Wilkinson II -30 S22 (or S33) Simulation (ADS) Wilkinson I & II Wilkinson I -25 Simulation (ADS) -30 Wilkinson II Frequency (GHz) CHIP PHOTOGRAPH 100 W Port-2 Port-3 l=l/4=1.045 mm Port-1 Loss: GHz Isolation < -20 GHz Excellent matching with EM-sim Area Wilkinson I: 0.15 x 0.5 mm 2 (3.15 %) Wilkinson II: 0.08 x 1 mm 2 (3.36 %) First on-chip Wilkinson coupler in phased arrays 2-STAGE WILKINSON SiGe BiCMOS (f T =150 GHz), Area=1.4x1.7 mm

195 4-ELEMENT mm-wave PHASED-ARRAY RX (44 GHZ, MEASUREMENT) PARAMETER RESULTS Technology 0.18-mm SiGe BiCMOS (Jazz SiGe120, 1P6M) Supply voltage Current consumption Frequency band 5 V (analog), 3.3 V (digital) I bias =118 ma (29 ma per channel) Q-band (3-dB BW: GHz) PTAT ARRAY DECODER Phase resolution 4-bit (accuracy > 5-bit) CH-4 Input return loss Output return loss Power gain (ave) < GHz < GHz GHz CH-3 DRIVER NF Phase error (RMS) Gain error (RMS) GHz < GHz < GHz CH-2 LNA PHASE SHIFTER IIP GHz Phase mismatch (RMS) < GHz (between all channels) CH-1 Amp. mismatch (RMS) Isolation (CH-to-CH) Array factor directivity Chip area < GHz (between all channels) < GHz 6 db (4-element) 1.4 x1.7 mm 2 2-STAGE WILKINSON Ref: K.-J. Koh etal, A Q-Band Four-Element Phased-Array Front-End Receiver with Integrated Wilkinson Power Combiners in in 0.18-mm SiGe BiCMOS Technology, IEEE Trans. On MTT, Sept

196 ACTIVE PHASE SHIFTER - I/Q NETWORK (LOSSLESS) Output FOR X- & KU-BAND (6-18 GHZ) 2R=50 W L=324 ph C=543 ff bias f o =12 GHz 8xIref 20xIref 28xIref Optimization of R, L & C Qin+ Input Iin- C L Qin- 2R Qin+ Qin- I/Q phase error (deg) xII Allow acceptable error around fii o to increase bandwidth Measurements Simulation 4xIQ Iin+ Qin- Qin+ Iin- Iin Frequency (GHz) Under 70 ff loading capacitance, I/Q phase error < 3 GHz I/Q amplitude mismatch < 1.8 GHz IQ RF input I/Q Network (Quadrature All-pass Filter) Sb S D + - D1 D2 D3 D DI1 DI2 DI3 DI4 I - + Gain control (VGA) Sign control 1:1 1:1 Q DAC S RF output Sb Control logic Control bits CAL 12 49

197 SOME REMARKS ON I/Q NETWORK I/Q network is an indispensable block for comm. system, but rarely used at RF signal path due to loss Lossless I/Q network, QAF (3dB gain, 3dB NF, All-Pass), enables many new system configurations IMAGE REJECTION QUADRATURE ALL-PASS DOHERTY POWER AMPLIFIER 90 o FILTER RF 90 o -Hybrid 90 o (l/4) T-line RF 90 o S IF RF RF 90 o 90 o RF RF 90 o 90 o S IF ANTENNA POLARIZATION CONTROL 90 o l/2 EV 90 o RHCP (EH=EV - 90 o ) RF 90 o S IF EV EH EH S LHCP (EH=EV + 90 o ) Versatile and promising building block for future RF & mm-wave phased arrays and comm. systems 50

198 0.13-mm CMOS ACTIVE PHASE SHIFTERS X-BAND (6-18 GHZ) DESIGN KU-BAND (15-26 GHZ) DESIGN Input Quadrature all-pass filter DAC & Control logic Adder Output matching Output Input Quadrature all-pass filter DAC & Control logic Adder Output matching Output CMOS implementations with same active phase shifter architectures Phase shifter core size: 0.3 x 0.4 mm 2 (smallest one published) Ref: K.-J. Koh etal, 0.13-mm CMOS phase shifters for X-, Ku-, and K-Band Phased Arrays, IEEE JSSC, Nov First realization of CMOS active phase shifters (4-bit resolution) Supported by Intel UC Discovery Project ( ) Presented at Intel project review meeting & RFIC

199 ACTIVE PHASE SHIFTER MEASUREMENTS NF & power gain (db) Gain error (db, RMS) sim Gain NF sim Frequency (GHz) Gain: GHz Gain error: 1.1 db GHz NF: GHz 5-bit phase response (deg) Phase error (deg, RMS) o -bit (reference, 00000) o -bit (11111) Frequency (GHz) Phase error: < 5.6 o GHz S11 < -10 GHz S22 < -10 GHz The active phase shifter achieves 6-bit accuracy at 6-18 GHz (D=360 o /2 6 =5.625 o ) 52

200 ACTIVE PHASE SHIFTER TEMPERATURE MEASUREMENTS RF input I/Q Network (Quadrature All-pass Filter) Gain control (VGA) Sign control I Q DAC RF output CAL Control logic Control bits RMS Phase Error (deg) C 50 C 75 C 100 C < 1 o < 0.2 db Frequency (GHz) RMS Gain Error (db) I & Q paths are biased with a reference PTAT circuit RMS phase error < C RMS gain error < C I & Q amplifiers track each other vs. PVT, resulting in low sensitivity to PVT 53

201 ANGLED-DIPOLE ANTENNA GHZ MEASUREMENT S 11 < GHz 102 HPBW 3 db antenna gain Coupling < -17 db Can be used +/- 60 o scan with 4dB drop in element factor Ref: Y. A. Atesal, B. Cetinoneri, K.-J. Koh, G. M. Rebeiz, X/Ku-Band 8-Element Phased Arrays Based on Single Silicon Chips, 2010 IMS, May

202 50 W 8-ELEMENT PHASED-ARRAY (6-18 GHZ, Z-MATCHING) DIGITAL CONTROL L-C matching SILICON PHASED ARRAY CHIP (2.2 X 2.4 mm 2 ) 5 mm R-C VCC DECOUPLNG (100 nf) OUTPUT PORT VCC bias & digital control Digital control VCC VCC Output port GND pedestal S 11 < GHZ S 22 < GHZ 55

203 8-ELEMENT PHASED-ARRAY (6-18 GHZ, BOARD MEASUREMENT) S11 < GHZ S22 < GHZ 56

204 3-D PACKAGE SIMULATION (1) Si Chip Duroid 200 μm System gnd Modeled using HFSS Coupling between adjacent ports < -17 db 57

205 3-D PACKAGE SIMULATION (2) Coupling between adjacent ports is reduced to < -25 db 58

206 ACTIVE COMBINER V.S. PASSIVE COMBINER Vcc ACTIVE COMBINER PASSIVE COMBINER db channel gain 18 db array gain (α N 2 ) ~ 3 db antenna gain 0.7 db loss due to connector ~40 db overall measured gain 59

207 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, SCHEMATIC) ARRAY DECODER ACTIVE BALUN CH-8 CH-7 CH-6 PHASE SHIFTER 50W DRIVER LCA 1:8 PASSIVE T- JUNCTION (0.15X1.15 mm 2 ) = 2% CH-9 CH-10 CH-11 include parasitic L (EM sim) Emitter-coupling Stub-matching: 50W 6dB gain, 5 ma 1:2 CH-5 RF INPUT CH-4 ACTIVE BALUN 1:2 ACTIVE PTAT CH-12 CH-13 Current mode 1:2 CMRR 12dB gain, 15 ma 1:8 1:2 ACTIVE DIVIDER 1:8 CH-3 CH-14 CH-2 1:8 PASSIVE T-JUNCTION CH-15 Active Balun CH-1 CH-16 60

208 LCA (loss compensation amplifier) 12.5 um 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, 1:8 T-JUNCTION) CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER ACTIVE BALUN ARRAY DECODER LCA 1:8 PASSIVE T- JUNCTION (0.15X1.15 mm 2 ) = 2% 1:2 ACTIVE PTAT SIGE METAL STACKS oxide M3 M1 SHIELDED BROADSIDE-COUPLED DIFF-T-LINE Al (M6) Top metal M6 M5 M CH Vias um M4 M3 2 um M M2 M M 1.9 um CH-10 Si-sub CH W-cm GND (M1) CH-11 Perfectly shielded (no coupling btw T-lines) Allow compact integration of many diff T-lines CH-12 1:8 TEE-JUNCTION DIVIDER RF INPUT 12.5 W 25 W 50 W CH-4 CH-3 CH-13 CH-14 1:2 50 W CH-2 1:8 PASSIVE T-JUNCTION CH-15 CH-1 CH-16 Quarter path Division loss: 18 db + parasitic loss (~ 3 db) 61

209 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, COAXIAL T-LINE) ARRAY DECODER SHIELDED BROADSIDE-COUPLED DIFF-T-LINE Al (M6) Top metal CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER ACTIVE BALUN LCA 1:8 PASSIVE T- JUNCTION (0.15X1.15 mm 2 ) = 2% 1:2 ACTIVE PTAT CH-9 CH-10 CH-11 CH-12 M + + Vias mm 2 um M M 1.9 mm 3 GND (M1) Perfectly shielded (no coupling btw T-lines) Allow compact integration of many diff T-lines ODD-MODE E-FIELDS EVEN-MODE E-FIELDS RF INPUT CH-4 CH-13 CH-3 CH-14 CH-2 CH-1 1:8 PASSIVE T-JUNCTION CH-15 CH-16 W=3 mm: odd-mode impedance=50 W (HFSS sim) Most fields (> 95%) are confined btw diff-t lines Measured loss: 3 db / 0.5 GHz 62

210 Phase shifter 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, SCHEMATIC) ARRAY DECODER LOSS COMPENSATION AMP (LCA) CH-8 CH-7 CH-6 CH-5 PHASE SHIFTER 50W DRIVER ACTIVE BALUN LCA 1:8 PASSIVE T- JUNCTION (0.15X1.15 mm 2 ) = 2% 1:2 ACTIVE PTAT CH-9 CH-10 CH-11 CH-12 1:8 CE + CB + Push-pull = 22 ma 12 db gain RF INPUT CH-4 CH-3 CH-13 CH-14 50W DRIVER ACTIVE PHASE SHIFTER LCA + - PA CH-2 CH-1 1:8 PASSIVE T-JUNCTION CH-15 CH-16 Diff-amp: 11 ma NMOS push-pull: 3 ma Wideband 1/gm matching (S11< -10dB, GHz) 63

211 16-ELEMENT mm-wave PHASED-ARRAY TX (44 GHZ, MEASUREMENT) S-Parameters (db) Power gain (db) Frequency (GHz) Gain Average gain Simulation (SPECTRE) Output return loss Input return loss Output power (average) Power pain (average) Input power (dbm) bit relative phases (deg) Output power (dbm) Frequency (GHz) Power gain: 12.5 GHz RMS gain variation < 1.3 GHz 3-dB BW: GHz S11 < -10 GHz S22 < -10 GHz RMS phase error < 8.8 GHz P sat : dbm (for all phase GHz OP 1dB : GHz 64

212 16-ELEMENT mm-wave PHASED-ARRAY TX (CHIP-SET TREND) EVOLUTION OF PHASED ARRAY CHIP-SET AREA, COST, WEIGHT L-Band T/R module, early 90 s Lincoln Lab Journal, 2000 T/R MMICs & ASIC on board A < 1 inch 2 T/R MMICs & ASIC in single package (2-D integration), A < 1 cm 2 T/R MMIC (III-V), A=15 mm Ref: 2007 Multi-function phased-array RADAR Conference CERAMIC BOARD (packaged transistors, switches, phase shifters & AMP) CERAMIC BOARD (T/R MMICs & signal processor) CURRENT TECH SINGLE PACKAGE (2-D integration) 65

213 16-ELEMENT mm-wave PHASED-ARRAY TX (LARGE ARRAY, 3-D INTEGRATION) EVOLUTION OF PHASED ARRAY CHIP-SET MULTI-LAYER 3-D INTEGRATION AREA, COST, WEIGHT L-Band T/R module, early 90 s Lincoln Lab Journal, 2000 T/R MMIC (III-V), A=15 mm 2 T/R MMICs & ASIC on board A < 1 inch 2 T/R MMICs & ASIC in single package (2-D integration), A < 1 cm 2 3-D integration in single package Q-Band satellite Ref: 2007 Multi-function phased-array RADAR Conference CERAMIC BOARD (packaged transistors, switches, phase shifters & AMP) CERAMIC BOARD (T/R MMICs & signal processor) CURRENT TECH SINGLE PACKAGE (2-D integration) SINGLE PACKAGE (3-D integration) FUTURE TECH 66

214 TYPICAL PASSIVE PHASE SHIFTERS (TOPOLOGIES) T-LINE APPROACHES 1 Switched T-lines 1 LUMPED PASSIVE APPROACHES 1 Lumped synthetic T-lines L L Input C C C C Output Input Output o branch-line hybrid coupler 2 Lumped hybrid coupler Output Input Input C D L D l=l/4 ex: GHz l=l/4 3 Periodic loaded line C L Variable impdeance Output Output Input C1 C1 C2 3 LPF / HPF approach Input L L C C L C L L Variable impdeance Output ISSUES: Chip area, Loss, Nonlinear control 67

215 TIME-DOMAIN y t Wave front (eqi-phase in space-time domain) Y = A sin(kx-wt) x SAMPLE & HOLD (ADC) Time-domain sampling T s < Nyquist rate Aliasing Need hold time, T H, to quantize SAMPLED-DATA SYSTEM (TIME DOMAIN) t T S: SAMPLING PERIOD Ts T/2 Ts PERIOD: T=1/f T-DOMAIN SIGNAL f S =1/T S QUANTIZER DIGITAL OUT HOLD TH TH TH TH TH FREQ QUANTIZER f B W f S 2f S nf S DIGITAL 68

216 SPACE-DOMAIN t y t Wave front (eqi-phase in space-time domain) SAMPLED-DATA SYSTEM (TIME DOMAIN) T S: SAMPLING PERIOD Ts T/2 Ts PERIOD: T=1/f Y = A sin(kx-wt) x SAMPLED-DATA SYSTEM (SPATIAL DOMAIN) x d: SAMPLING DISTANCE d l/2 d WAVELENGTH: l=c/f C: LIGHT SPEED SAMPLE & HOLD (ADC) Time-domain sampling T s < Nyquist rate Aliasing Need hold time, T H, to quantize PHASED-ARRAY (MULTI-ANTENNA) Space-domain sampling d < Nyquist distance Aliasing ( Grating lobe ) Need t to in-phase ( Select ) or to out-of-phase ( Reject ) HOLD TH TH TH TH TH QUANTIZER DIGITAL DELAY t 1 t 2 t 3 t 4 t 5 COMBINER RF TIME ω 2 T SPACE k 2 l 69

217 2-ANTENNA ARRAY (2-POINT SAMPLING, INTUITIVE) WAVE FRONT t 30 o B A 2 1 PHASE DOMAIN x FOR THE SAME WAVE-FRONT (incident angle: 30 o ), A arrives first to ANT 1 B travels X d more to arrive ANT 2 PHASE DIFFERENCE BTW 1 & Arriv altime difference 2 l o 1 d sin30 2f 2 c Distance (X d sin30 l ) 4 o 90 o 2 2 Xd l/ LNA PHASE OUTPUT SHIFTER + + *Amplitude (db) o delay = = -90 o delay *Conceptually drawn SELECTING SIGNAL REJECTING SIGNAL 1-2 Filtering signal at SPACE-domain (PHASED ARRAY = SPATIAL FILTER) 70

218 PHASED ARRAY V.S. MIMO (1) PHASED ARRAY MIMO 71

219 PHASED ARRAY V.S. MIMO (2) 72