ENABLING LOW-TEMPERATURE BONDING IN ADVANCED PACKAGING USING ELECTRODEPOSITED INDIUM

Transcription

1 ENABLING LOW-TEMPERATURE BONDING IN ADVANCED PACKAGING USING ELECTRODEPOSITED INDIUM Yi Qin, K. Flajslik, B. Sherzer, E. Banelis, I. Lee, R. Cho, L. Grippo, M. Imanari, M. Lefebvre, L. Wei, W. Tachikawa, J. Dong, J. Calvert Dow Electronic Materials 455 Forest Street, Marlborough, MA, USA, Dow.com

2 Potential Applications in Packaging Chip package design concept courtesy of IMEC ETNA 3D chip stack with DRAM and Logic integration 3D IC Flexible Electronics Potential low-t solder application Melting Point (ºC) Unique physical and thermal properties of dium Low melting point ( low assembly temp.) Soft, flexible metal Electrical Resistivity (20ºC, nω m) High thermal conductivity Thermal Conductivity (W/m K -1 ) Potential to alloy with other solder metals CTE (25ºC, µm/m K -1 ) Sn New material requirements with fast evolution of packaging 3D IC Challenging thermal management dium for thermal interface materials Flexible electronics sensitive to assembly temperature dium for low temperature bonding IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

3 Potential Applications in Packaging Case 1: C4 bumps Case 2: multi(thin)-layer bonding terconnect Electrodeposited indium bumps (as-plated) 1 Reflowed indium bump array (40 µm diameter, 100 µm pitch) 2 -including multilayer composite design for low-t bonding 3 Materials & UBM (Ti/Pt/Au) Materials /Sn/Au multilayer composite Process Electroplating and Sputtering Process Evaporation (e-beam and thermal) Application FC interconnection of FPAs (focal plane arrays) and ROICs (read-out integrated circuits) Application Photonic and fiber optic device packaging Properties Enabled Low temp. bonding; ductility at cryogenic conditions; high reliability Properties Enabled 140ºC bonding temp.; low stress, fluxless bonding 1 Tian et al, Journal of Electronic Materials, Huang et al, Journal of Semiconductors, Lee et al, Materials Science and Engineering A, 2002 IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

4 Results & Discussion Technical Approach dium capping on micro copper pillar dium capping on standard copper pillar PR 25 µm 8µm 18µm (INDOTHERM ) Cu (INTERVIA 8540) 10µm 30µm PR 50 µm 20 µm 50 µm Feature Test wafer 1 Test wafer 2 Via diameter 20 µm 50 µm Photoresist type Dry film Dry film Photoresist height 25 µm 50 µm Pitch 2:1~5:1 2:1~5:1 Open area 13% 9% IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

5 Results & Discussion -Ni equilibrium phase diagram* terfacial property investigation FIB Pt (Protection Layer) Ni/Cu Si wafer TEM -Ni IMC Void-free performance at the -Ni interface. *H. Okamoto et al, Binary Alloy Phase Diagrams (ASM ternational, Metals Park, OH, 1990) IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

6 Results & Discussion dium capping on copper pillar Sparse 50 µm 10µm 30µm 50 µm (INDOTHERM ) Cu (INTERVIA 8540) 8µm 18µm 20 µm 25 µm Co-planarity Height (µm) WID% DENSE SPARSE DENSE SPARSE Standard pillars (INDOTHERM ) Micro pillars Cu (INTERVIA 8540) hmax h WID(%) 2 h avg min 100% Excellent co-planarity (WID) performance on the test wafer of multiple pitches. Demonstration of dium capping on both micro and standard Copper pillars IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

7 Heat flow Results & Discussion dium capping on copper pillar DSC Analysis 50 µm 10µm 30µm (INDOTHERM ) Cu (INTERVIA 8540) 8µm 18µm 25 µm 50 µm 20 µm C (INDOTHERM ) Cu (INTERVIA 8540) Temperature (ºC) Demonstration of dium capping on both micro and standard Copper pillars DSC (differential scanning calorimetry) analysis showed a melting point of dium at ~157ºC. IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

8 Results & Discussion dium capping on copper pillar Reflow Trials (INDOTHERM ) Cu (INTERVIA 8540) Reflow Zone Temperature ( C) Reflow Profile Time (Seconds) Cooling 60 Preliminary trials reflowed dium caps at a peak temperature as low as ~165ºC. Void-free in X-ray IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

9 Results & Discussion -Sn equilibrium phase diagram* Other low-t solder candidates Solder Composition Melting temperature ( o C) 160ºC 120ºC 52 48Sn Sn Bi 42Sn Sn >110ºC 60Sn 40Bi Sn 3.5Ag Sn 232 Wide range of -Sn solder composition of low melting points -Sn alloys, with a wide range of composition window, could enable lower melting point than pure dium. *H. Okamoto et al, Binary Alloy Phase Diagrams (ASM ternational, Metals Park, OH, 1990) IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

10 Results & Discussion vestigation Strategy Strategy A: stacking of and Sn Strategy B: electrodeposition of -Sn alloy Sn IN UBM Reflow UBM -Sn As-plated Alloy UBM Reflow UBM Current trials with INDOTHERM dium plating chemistry Future work of next generation product development IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

11 Results & Discussion SEM images of bump morphologies Nickel Ni PR residue Nickel/dium Ni Nickel/dium/Tin Sn Ni Co-planarity Step Avg. Height (um) Range of height (Max Min) um WID % (Range)/(2*Avg. height) Nickel Nickel/dium Nickel/dium/Tin dium/tin stacks on Nickel were prepared to form -Sn alloys. IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

12 Heat flow Results & Discussion Reflow of -Sn Stacks DSC Analysis Sn Ni As-plated Post reflow 25 µm 20 µm Sn: 3µm : 3µm Ni: 3 µm DSC (differential scanning calorimetry) analysis showed a melting point of -Sn alloy at ~119ºC. IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

13 Development of Next-Gen dium Chemistry Optical images of Nickel and Nickel/dium deposit on internal test wafer 72µm 75µm Ni 72µm 75µm Ni 72µm 75µm Ni 25µm Ni = NIKAL BP chemistry (1 ASD, 55C, 60s) Smooth Ni deposit = new electrolyte only, no additive, 4ASD, 25C, 11s Rough dium deposit = next generation chemistry, 4ASD, 25C, 11s Smooth dium deposit Smooth nucleation of dium on Ni IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

14 Development of Next-Gen dium Chemistry Characterization of Ni deposit Optical Image SEM Image AFM Image 20000X Ni only (NIKAL BP, 1 ASD, 55C, 60s); Area of AFM scan = 10µm X 10µm; Ra = ~ 4nm Characterization of Ni/ deposit 20000X Ni (NIKAL BP, 1 ASD, 55C, 60s) / (next generation chemistry, 4ASD, 25C, 11s) Area of AFM scan = 5µm X 5µm; Ra = ~ 13nm IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

15 Summary INDOTHERM demonstrated capability of indium metallization for low-temperature solder in advanced packaging applications. Development of next-gen dium chemistry is in progress to further improvement. SOLDERON BP TS6000 SnAg Cap SnAg T melt = ~221ºC Reflow Temp. T melt = ~157ºC INDOTHERM Cap 20 µm Cu INTERVIA 8540 Cu Cu 20 µm IEEE 66 th ECTC Las Vegas, NV, May 31 ~ June 3,

16 Thank You Acknowledgement Dow Core R&D Analytical Science Trademark of The Dow Chemical Company ("Dow") or an affiliated company of Dow