ADM206E/ADM207E/ADM208E/ADM211E/ADM213E

Transcription

1 EMI/EMC-Compliant, ± kv ESD Protected, RS- Line Drivers/Receivers ADM6E/ADM7E/ADM8E/ADME/ADME FEATURES Complies with 89/6/EEC EMC directive ESD protection to IEC (80-) Contact discharge: ±8 kv Air-gap discharge: ± kv Human body model: ± kv EFT/burst immunity (IEC ) Low EMI emissions (EN 0) Eliminates need for TransZorb suppressors kbps data rate guaranteed Single V power supply Shutdown mode μw Plug-in upgrade for MAXxxE Space saving TSSOP package available APPLICATIONS Laptop computers Notebook computers Printers Peripherals Modems GENERAL DESCRIPTION The ADMxxE is a family of robust RS- and V.8 interface devices that operate from a single V power supply. These products are suitable for operation in harsh electrical environments and are compliant with the EU directive on electromagnetic compatibility (EMC) (89/6/EEC). The level of emissions and immunity are both in compliance. EM immunity includes ESD protection in excess of ± kv on all I/O lines (IEC ), fast transient burst protection (IEC ), and radiated immunity (IEC ). EM emissions include radiated and conducted emissions as required by Information Technology Equipment EN 0, CISPR. All devices fully conform to the EIA--E and CCITT V.8 specifications and operate at data rates up to kbps. Shutdown and enable control pins are provided on some of the products (see Table ). The shutdown function on the ADME disables the charge pump and all transmitters and receivers. On the ADME the INPUTS 0V 0V T IN T IN T IN T4 IN R OUT R OUT R OUT R4 OUT R OUT EN (ADME) EN (ADME) CONNECTION DIAGRAM C 4 C C 6 C V TO0V DOUBLER 0V TO 0V INVERTER 0 T T T T4 R R R R4 R ADME/ ADME V CC V V 7 V INPUT 6.V 0V T OUT T OUT T OUT T4 OUT R IN R IN R IN R4 IN R IN RS- RS- INPUTS SHDN (ADME) SHDN (ADME) INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. Figure. charge pump, all transmitters, and three of the five receivers are disabled. The remaining two receivers remain active, thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral device begins communication. The active receivers can alert the processor, which can then take the ADME out of the shutdown mode. Operating from a single V supply, four external 0. μf capacitors are required. The ADM7E and ADM8E are available in 4-lead PDIP, SSOP, available in 8-lead SSOP, TSSOP, and SOIC_W packages. All products are backward compatible with earlier ADMxx products, facilitating easy upgrading of older designs. Table. Selection Table Model Supply Voltage Drivers Receivers ESD Protection Shutdown Enable Packages ADM6E V 4 ± kv Yes Yes RW-4 ADM7E V ± kv No No N-4-, RW-4, RS-4, RU-4 ADM8E V 4 4 ± kv No No N-4-, RW-4, RS-4, RU-4 ADME V 4 ± kv Yes Yes RW-8, RS-8, RU-8 ADME V 4 ± kv Yes (SHDN) Yes (EN) RW-8, RS-8, RU-8 Two receivers active Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADM6E/ADM7E/ADM8E/ADME/ADME TABLE OF CONTENTS Features... Applications... General Description... Connection Diagram... Revision History... Specifications... Absolute Maximum Ratings... 4 ESD Caution... 4 Pin Configurations and Function Descriptions... Typical Performance Characteristics... 8 Theory of Operation... 0 Circuit Description... 0 REVISION HISTORY 9/06 Rev. D to Rev. E Updated Format...Universal Changes to Figure and Table... Changes to Table... Changes to Figure, Figure, and Figure... Changes to Figure 7 and Figure Changes to Figure... 7 Changes to Figure Updated Outline Dimensions... 6 Changes to Ordering Guide /0 Rev. C to Rev. D Changes to Specifications Section... Changes to Ordering Guide... 4 Updated Outline Dimensions... 6 Enable and Shutdown... 0 High Baud Rate... ESD/EFT Transient Protection Scheme... ESD Testing (IEC )... EFT/Burst Testing (IEC )... IEC Radiated Immunity... Emissions/Interference... 4 Conducted Emissions... 4 Radiated Emissions... 4 Outline Dimensions... 6 Ordering Guide... 9 /0 Rev. B to Rev. C Changes to Features Section... Changes to Specifications Table... Changes to Absolute Maximum Ratings... Changes to Figure 6... Changes to Typical Performance Characteristics Section... 7, 8 Changes to Table V... Rev. E Page of

3 SPECIFICATIONS VCC =.0 V ± 0%, C to C4 = 0. μf. All specifications TMIN to TMAX, unless otherwise noted. ADM6E/ADM7E/ADM8E/ADME/ADME Table. Parameter Min Typ Max Unit Test Conditions/Comments DC CHARACTERISTICS Operating Voltage Range V VCC Power Supply Current. ma No load SHUTDOWN SUPPLY CURRENT 0. 0 μa LOGIC Input Pull-Up Current 0 μa TIN = Input Logic Threshold Low, VINL 0.8 V TIN, EN, EN, SHDN, SHDN Input Logic Threshold High, VINH.0 V TIN Input Logic Threshold High, VINH.0 V EN, EN, SHDN, SHDN Output Voltage Low, VOL 0.4 V IOUT =.6 ma Output Voltage High, VOH. V IOUT = 40 μa Output Leakage Current 0.0 ±0 μa EN = VCC, EN =, 0 V ROUT VCC RS- RECEIVER Input Voltage Range 0 0 V Input Threshold Low 0.8. V Input Threshold High.0.4 V Input Hysteresis 0.6 V Input Resistance 7 kω TA = 0 C to 8 C RS- TRANSMITTER Output Voltage Swing ±.0 ±9.0 V All transmitter outputs loaded with kω to ground Output Resistance 00 Ω VCC = 0 V, VOUT = ± V Output Short-Circuit Current ±6 ± ±60 ma TIMING CHARACTERISTICS Maximum Data Rate kbps RL = kω to 7 kω, CL = 0 pf to 0 pf Receiver Propagation Delay, TPHL, TPLH 0.4 μs CL = 0 pf Receiver Output Enable Time, ter ns Receiver Output Disable Time, tdr ns Transmitter Propagation Delay, TPHL, TPLH μs RL = kω, CL = 0 pf Transition Region Slew Rate 8 V/μs RL = kω, CL = 0 pf to 0 pf, measured from V to V or V to V EM IMMUNITY ESD Protection (I/O Pins) ± kv Human body model ± kv IEC air-gap discharge ±8 kv IEC contact discharge Radiated Immunity 0 V/m IEC Guaranteed by design. Table. ADME Truth Table SHDN EN Status TOUT :4 ROUT : 0 0 Normal operation Enabled Enabled 0 Normal operation Enabled Disabled X Shutdown Disabled Disabled X = don t care. Table 4. ADME Truth Table SHDN EN Status TOUT :4 ROUT : ROUT 4: 0 0 Shutdown Disabled Disabled Disabled 0 Shutdown Disabled Disabled Enabled 0 Normal operation Enabled Disabled Disabled Normal operation Enabled Enabled Enabled Rev. E Page of

4 ADM6E/ADM7E/ADM8E/ADME/ADME ABSOLUTE MAXIMUM RATINGS TA = C, unless otherwise noted. Table. Parameter Rating VCC 0. V to 6 V V (VCC 0. V) to 4 V V 0. V to 4 V Input Voltages TIN 0. V to (V 0. V) RIN ±0 V Output Voltages TOUT ± V ROUT 0. V to (VCC 0. V) Short-Circuit Duration TOUT Continuous Power Dissipation N-4- PDIP (Derate. mw/ C above 70 C) 000 mw RW-4 SOIC_W (Derate mw/ C above 70 C) 900 mw RS-4 SSOP (Derate mw/ C above 70 C) 80 mw RU-4 TSSOP (Derate mw/ C above 70 C) 900 mw RW-8 SOIC_W (Derate mw/ C above 70 C) 900 mw RS-8 SSOP (Derate 0 mw/ C above 70 C) 900 mw RU-8 TSSOP (Derate mw/ C above 70 C) 900 mw Operating Temperature Range 40 C to 8 C Storage Temperature Range 6 C to 0 C Lead Temperature, Soldering (0 sec) 00 C ESD Rating MIL-STD-88B (I/O Pins) ± kv IEC Air-Gap (I/O Pins) ± kv IEC Contact (I/O Pins) ±8 kv Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. E Page 4 of

5 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADM6E/ADM7E/ADM8E/ADME/ADME T OUT 4 T4 OUT T OUT 4 T4 OUT T OUT R IN T OUT R IN T OUT R OUT T OUT R OUT R IN 4 SHDN R IN 4 T IN R OUT T IN T IN ADM6E EN 6 TOP VIEW 9 T4 IN 7 (Not to Scale) 8 T IN R OUT T IN T IN ADM7E T OUT 6 TOP VIEW 9 T4 IN 7 (Not to Scale) 8 T IN 8 7 R OUT 8 7 R OUT V CC 9 6 R IN V CC 9 6 R IN C 0 V V 4 C C C Figure. ADM6E Pin Configuration C 0 V V 4 C C C Figure 4. ADM7E Pin Configuration V INPUT 6.V 6V 0 C C C 4 C V TO 0V DOUBLER 0V TO 0V INVERTER V CC 9 V V V INPUT 6.V 6V 0V 0V 0 C C C 4 C V TO 0V DOUBLER 0V TO 0V INVERTER V CC 9 V V 6.V 0V T IN 7 T T OUT T IN 7 T T OUT T IN 6 T T OUT INPUTS T IN T IN 6 8 T T T OUT T OUT RS- INPUTS T IN 8 T T OUT RS- T4 IN 9 T4 4 T4 OUT T4 IN 9 T4 4 T4 OUT T IN T T OUT R OUT R 4 R IN R OUT R OUT R 7 R 6 R IN R IN RS- INPUTS R OUT R OUT R R 4 R IN R IN RS- INPUTS R OUT 7 R 6 R IN EN 8 ADM6E SHDN 8 ADM7E INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. Figure. ADM6E Typical Operating Circuit INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. Figure. ADM7E Typical Operating Circuit Rev. E Page of

6 ADM6E/ADM7E/ADM8E/ADME/ADME T OUT 8 T4 OUT T OUT T OUT R IN R OUT 4 4 T OUT R IN R OUT T4 IN T IN ADM8E T4 OUT R OUT 6 TOP VIEW 9 T IN R IN V CC C V C (Not to Scale) 8 T IN 7 R4 OUT 6 R4 IN V 4 C C Figure 6. ADM8E Pin Configuration T OUT 7 R IN T OUT 6 R OUT R IN 4 SHDN R OUT 4 EN T IN 6 ADME R4 IN T IN 7 TOP VIEW R4 OUT R OUT 8 (Not to Scale) T4 IN R IN 9 T IN 0 9 R OUT V CC 8 R IN C 7 V V 6 C C 4 C Figure 8. ADME Pin Configuration V INPUT 0V 0V 0 C C C 4 C V TO0V DOUBLER 0V TO 0V INVERTER V CC 9 V V V INPUT 6.V 0V 0V 0V T IN C 4 C C 6 C 7 V TO 0V DOUBLER 0V TO 0V INVERTER T V CC V V 7 6.V 0V T OUT INPUTS T IN T IN T IN 8 9 T T T 4 T OUT T OUT T OUT RS- INPUTS T IN T IN T4 IN 6 T T T4 8 T OUT T OUT T4 OUT RS- T4 IN T4 T4 OUT R OUT 8 R 9 R IN R OUT 6 R 7 R IN R OUT R 4 R IN R OUT R OUT 4 R R R IN R IN RS- INPUTS R OUT R4 OUT 6 R R4 7 R IN R4 IN RS- INPUTS R4 OUT 7 R4 6 R4 IN R OUT 9 R 8 R IN 8 ADM8E EN 4 0 ADME SHDN INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. Figure 7. ADM8E Typical Operating Circuit INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. Figure 9. ADME Typical Operating Circuit Rev. E Page 6 of

7 ADM6E/ADM7E/ADM8E/ADME/ADME V INPUT T OUT T OUT T OUT T4 OUT R IN R OUT 6V C 4 C V TO0V DOUBLER V CC V 6.V R IN 4 R OUT 4 T IN 6 ADME T IN 7 TOP VIEW R OUT 8 (Not to Scale) R IN V CC 8 SHDN EN R4 IN R4 OUT T4 IN T IN R OUT R IN INPUTS 6V T IN T IN T IN C 6 C 7 6 0V TO 0V INVERTER T T T V 7 6V T OUT T OUT T OUT RS- C 7 V T4 IN T4 8 T4 OUT V C 4 6 C C ACTIVE IN SHUTDOWN R OUT R OUT 8 R R 9 4 R IN R IN Figure 0. ADME Pin Configuration R OUT 6 R 7 R IN RS- INPUTS R4 OUT R4 R4 IN R OUT 9 R 8 R IN EN 4 ADME SHDN 0 INTERNAL 400kΩ PULL-UP RESISTOR ON EACH INPUT. INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT. ACTIVE IN SHUTDOWN. Figure. ADME Typical Operating Circuit Table 6. Pin Function Descriptions Mnemonic Function VCC Power Supply Input ( V ± 0%). V Internally Generated Positive Supply (9 V nominal). V Internally Generated Negative Supply ( 9 V nominal). Ground Pin. Must be connected to 0 V. C, C External Capacitor is connected between these pins. A 0. μf capacitor is recommended, but larger capacitors (up to 47 μf) can be used. C, C External Capacitor is connected between these pins. A 0. μf capacitor is recommended, but larger capacitors (up to 47 μf) can be used. TIN Transmitter (Driver) Inputs. These inputs accept levels. An internal 400 kω pull-up resistor to VCC is connected on each input. TOUT Transmitter (Driver) Outputs. These are RS- signal levels (typically ±9 V). RIN Receiver Inputs. These inputs accept RS- signal levels. An internal kω pull-down resistor to is connected on each input. ROUT Receiver Outputs. These are output logic levels. EN/EN Receiver Enable (active high on ADME, active low on ADME). This input is used to enable/disable the receiver outputs. With EN = low for the ADME (EN = high for the ADME), the receiver outputs are enabled. With EN = high for the ADME (EN = low for the ADME), the receiver outputs are placed in a high impedance state. (See Table and Table 4.) SHDN/SHDN Shutdown Control (active low on ADME, active high on ADME). When the ADME is in shutdown, the charge pump is disabled, the transmitter outputs are turned off, and all receiver outputs are placed in a high impedance state. When the ADME is in shutdown, the charge pump is disabled, the transmitter outputs are turned off, and Receiver R to Receiver R are placed in a high impedance state; Receiver R4 and Receiver R on the ADME continue to operate normally during shutdown. (See Table and Table 4.) Power consumption for all parts reduces to μw in shutdown. Rev. E Page 7 of

8 ADM6E/ADM7E/ADM8E/ADME/ADME TYPICAL PERFORMANCE CHARACTERISTICS LIMIT 60 (dbµv) (dbµv) LIMIT LOG FREQUENCY (MHz) Figure. EMC Conducted Emissions START 0.0MHz STOP 0.0MHz Figure. EMC Radiated Emissions Tx O/P (V) 9 7 Tx O/P HI Tx O/P LO LOAD CAPACITANCE (pf) Figure. Transmitter Output Voltage High/Low vs. Load Capacitance ( kbps) Tx O/P (V) 9 Tx O/P HI LOADED 7 7 Tx O/P LO LOADED V CC (V) Figure 6. Transmitter Output Voltage vs. Power Supply Voltage T SHDN Tx O/P HI T V Tx O/P (V) 0 Tx O/P LO T LOAD CURRENT (ma) Figure 4. Transmitter Output Voltage vs. Load Current CH.00V CH.00V M 0.0µs CH.V CH.00V V, V EXITING SHDN Figure 7. Charge Pump V, V Exiting Shutdown V Rev. E Page 8 of

9 ADM6E/ADM7E/ADM8E/ADME/ADME 0 00 V 0 V IMPEDANCE (Ω) V V/V (V) 0 V V CC (V) LOAD CURRENT (ma) Figure 8. Charge Pump Impedance vs. Power Supply Voltage Figure 9. Charge Pump V, V vs. Load Current Rev. E Page 9 of

10 ADM6E/ADM7E/ADM8E/ADME/ADME THEORY OF OPERATION The ADM6E/ADM7E/ADM8E/ADME/ADME are ruggedized RS- line drivers/receivers that operate from a single V supply. Step-up voltage converters coupled with level shifting transmitters and receivers allow RS- levels to be developed while operating from a single V supply. Features include low power consumption, high transmission rates, and compliance with the EU directive on EMC, which includes protection against radiated and conducted interfereence, including high levels of electrostatic discharge. All RS- inputs and outputs contain protection against electrostatic discharges up to ± kv and electrical fast transients up to ± kv. This ensures compliance to IEC and IEC requirements. The devices are ideally suited for operation in electrically harsh environments or where RS- cables are plugged/unplugged frequently. They are also immune to high RF field strengths without special shielding precautions. Emissions are also controlled to within very strict limits. technology is used to keep the power dissipation to an absolute minimum, allowing maximum battery life in portable applications. The ADMxxE is a modification, enhancement, and improvement to the ADMxx family and its derivatives. It is essentially plug-in compatible and does not have materially different applications. CIRCUIT DESCRIPTION The internal circuitry consists of four main sections: A charge pump voltage converter. V logic to EIA- transmitters. EIA- to V logic receivers. Transient protection circuit on all I/O lines. Charge Pump DC-to-DC Voltage Converter The charge pump voltage converter consists of a 0 khz oscillator and a switching matrix. The converter generates a ±0 V supply from the input V level. This is done in two stages using a switched capacitor technique as illustrated in Figure and Figure. First, the V input supply is doubled to 0 V using Capacitor C as the charge storage element. The 0 V level is then inverted to generate 0 V using C as the storage element. Capacitor C and Capacitor C4 are used to reduce the output ripple. If desired, larger capacitors (up to 47 μf) can be used for Capacitor C to Capacitor C4. This facilitates direct substitution with older generation charge pump RS- transceivers. The V and V supplies can also be used to power external circuitry, if the current requirements are small (see the Typical Performance Characteristics section). V CC INTERNAL OSCILLATOR V FROM DOUBLER S S INTERNAL OSCILLATOR C S C S4 Figure. Charge Pump Voltage Doubler S S C S C4 S4 Figure. Charge Pump Voltage Inverter Transmitter (Driver) Section V = V CC V CC V = (V) The drivers convert V logic input levels into EIA- output levels. With VCC = V and driving an EIA- load, the output voltage swing is typically ±9 V. Unused inputs can be left unconnected, as an internal 400 kω pull-up resistor pulls them high, forcing the outputs into a low state. The input pull-up resistors typically source 8 μa when grounded, so unused inputs should either be connected to VCC or left unconnected in order to minimize power consumption. Receiver Section The receivers are inverting level shifters that accept EIA- input levels and translate them into V logic output levels. The inputs have internal kω pull-down resistors to ground and are protected against overvoltages of up to ± V. The guaranteed switching thresholds are 0.4 V minimum and.4 V maximum. Unconnected inputs are pulled to 0 V by the internal kω pulldown resistor. This, therefore, results in a Logic output level for unconnected inputs or for inputs connected to. The receivers have Schmitt trigger inputs with a hysteresis level of 0.6 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times. ENABLE AND SHUTDOWN Table and Table 4 are truth tables for the enable and shutdown control signals. The enable function is intended to facilitate data bus connections where it is desirable to tristate the receiver outputs. In the disabled mode, all receiver outputs are placed in a high impedance state. The shutdown function is intended to shut down the device, thereby minimizing the quiescent current. In shutdown, all transmitters are disabled and all receivers on the ADME are tristated Rev. E Page 0 of

11 ADM6E/ADM7E/ADM8E/ADME/ADME On the ADME, Receiver R4 and Receiver R remain enabled in shutdown. Note that the transmitters are disabled but are not tristated in shutdown; it is not permitted to connect multiple (RS-) driver outputs together. The shutdown feature is very useful in battery-operated systems since it reduces the power consumption to μw. During shutdown, the charge pump is also disabled. The shutdown control input is active high on the ADME, and it is active low on the ADME. When exiting shutdown, the charge pump is restarted, and it takes approximately 00 μs for it to reach its steady state operating condition. HIGH BAUD RATE The ADMxxE feature high slew rates, permitting data transmission rates well in excess of the EIA--E specifications. RS- levels are maintained at data rates up to kbps, even under worst-case loading conditions. This allows for high speed data links between two terminals, making it suitable for the new generation modem standards that require data rates of 0 kbps. The slew rate is controlled internally to less than 0 V/μs to minimize EMI interference. V EN INPUT 0V VOH t DR VOH 0.V protection structure is shown in Figure 4 and Figure. Each input and output contains two back-to-back high speed clamping diodes. During normal operation, with maximum RS signal levels, the diodes have no effect because one or the other is reverse biased, depending on the polarity of the signal. If, however, the voltage exceeds about ±0 V, reverse breakdown occurs, and the voltage is clamped at this level. The diodes are large p-n junctions designed to handle the instantaneous current surges that can exceed several amperes. The transmitter outputs and receiver inputs have a similar protection structure. The receiver inputs can also dissipate some of the energy through the internal kω resistor to as well as through the protection diodes. The protection structure achieves ESD protection up to ± kv and EFT protection up to ± kv on all RS- I/O lines. The methods used to test the protection scheme are discussed in the ESD Testing (IEC ) and EFT/Burst Testing (IEC ) sections. RECEIVER INPUT R R IN D D RX Figure 4. Receiver Input Protection Scheme RECEIVER OUTPUT V EN INPUT VOL VOL 0.V NOTES. EN IS THE COMPLEMENT OF EN FOR THE ADME. Figure. Receiver Disable Timing 0V RECEIVER OUTPUT t ER.V 0.8V NOTES. EN IS THE COMPLEMENT OF EN FOR THE ADME. Figure. Receiver Enable Timing ESD/EFT TRANSIENT PROTECTION SCHEME The ADMxxE use protective clamping structures on all inputs and outputs that clamp the voltage to a safe level and dissipate the energy present in ESD (electrostatic) and EFT (electrical fast transient) discharges. A simplified schematic of the RX D D T OUT TRANSMITTER OUTPUT Figure. Transmitter Output Protection Scheme ESD TESTING (IEC ) IEC (previously IEC 80-) specifies compliance testing using two coupling methods, contact discharge and airgap discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses a higher test voltage but does not make direct contact with the unit under test. With air-gap discharge, the discharge gun is moved toward the unit under test, developing an arc across the air gap. This method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. The contact discharge method, while less realistic, is more repeatable and is gaining acceptance in preference to the air-gap method. Although very little energy is contained within an ESD pulse, the extremely fast rise time, coupled with high voltages, can cause failures in unprotected semiconductors. Catastrophic Rev. E Page of

12 ADM6E/ADM7E/ADM8E/ADME/ADME destruction can occur immediately because of arcing or heating. Even if catastrophic failure does not occur immediately, the device can suffer from parametric degradation that can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. I/O lines are particularly vulnerable to ESD damage. Simply touching or plugging in an I/O cable can result in a static discharge that can damage or destroy the interface product connected to the I/O port. Traditional ESD test methods, such as the MIL-STD-88B method 0.7, do not fully test product susceptibility to this type of discharge. This test was intended to test product susceptibility to ESD damage during handling. Each pin is tested with respect to all other pins. There are some important differences between the traditional test and the IEC test: The IEC test is much more stringent in terms of discharge energy. The peak current injected is over four times greater. The current rise time is significantly faster in the IEC test. The IEC test is carried out while power is applied to the device. It is possible that the ESD discharge could induce latch-up in the device being tested. This test, therefore, is more representtative of a real-world I/O discharge, where the equipment is operating normally with power applied. However, both tests should be performed to ensure maximum protection both during handling and later during field service. HIGH GENERATOR R C R ESD TEST METHOD R C H. BODY MIL-STD-88B.kΩ 00pF IEC Ω 0pF Figure 6. ESD Test Standards DEVICE UNDER TEST I PEAK (%) ns TO ns 0ns 60ns Figure 8. IEC ESD Current Waveform TIME t ADMxxE products are tested using both of the previously mentioned test methods. Pins are tested with respect to all other pins as per the MIL-STD-88B specification. In addition, all I/O pins are tested per the IEC test specification. The products are tested under the following conditions: Power on (normal operation). Power on (shutdown mode). Power off. There are four levels of compliance defined by IEC ADMxxE products meet the most stringent compliance level both for contact and for air-gap discharge. This means that the products are able to withstand contact discharges in excess of 8 kv and air-gap discharges in excess of kv. Table 7. IEC Compliance Levels Level Contact Discharge (kv) Air-Gap Discharge (kv) Table 8. ADMxxE ESD Test Results ESD Test Method I/O Pin (kv) MIL-STD-88B ± IEC Contact ±8 Air-Gap ± I PEAK (%) t RL t DL TIME t Figure 7. Human Body Model ESD Current Waveform EFT/BURST TESTING (IEC ) IEC (previously IEC 80-4) covers EFT/burst immunity. Electrical fast transients occur because of arcing contacts in switches and relays. The tests simulate the interference generated when, for example, a power relay disconnects an inductive load. A spark is generated due to the well-known back EMF effect. In fact, the spark consists of a Rev. E Page of

13 ADM6E/ADM7E/ADM8E/ADME/ADME burst of sparks as the relay contacts separate. The voltage appearing on the line, therefore, consists of a burst of extremely fast transient impulses. A similar effect occurs when switching on fluorescent lights. The fast transient burst test defined in IEC simulates this arcing; its waveform is illustrated in Figure 9. It consists of a burst of. khz to khz transients repeating at 00 ms intervals. It is specified for both power and data lines. V Classification : Temporary degradation or loss of function or performance that requires operator intervention or system reset. Classification 4: Degradation or loss of function that is not recoverable due to damage. ADMxxE products meet Classification and have been tested under worst-case conditions using unshielded cables. Data transmission during the transient condition is corrupted, but it can resume immediately following the EFT event without user intervention. 00ms ms t HIGH SOURCE R C C C L Z S R M C D 0Ω OUTPUT V ns Figure 0. IEC Fast Transient Generator Table 9. Level 0ns 0.ms/0.4ms Figure 9. IEC Fast Transient Waveform V Peak (kv) PSU V Peak (kv) I/O A simplified circuit diagram of the actual EFT generator is illustrated in Figure 0. The transients are coupled onto the signal lines using an EFT coupling clamp. The clamp is m long and surrounds the cable completely, providing maximum coupling capacitance (0 pf to 0 pf typical) between the clamp and the cable. High energy transients are capacitively coupled onto the signal lines. Fast rise times ( ns), as specified by the standard, result in very effective coupling. Because high voltages are coupled onto the signal lines, this test is very severe. The repetitive transients can often cause problems where single pulses do not. Destructive latch-up can be induced due to the high energy content of the transients. Note that this stress is applied while the interface products are powered up and are transmitting data. The EFT test applies hundreds of pulses with higher energy than ESD. Worst-case transient current on an I/O line can be as high as 40 A. Test results are classified according to the following: Classification : Normal performance within specification limits. Classification : Temporary degradation or loss of performance that is self recoverable. t IEC RADIATED IMMUNITY IEC (previously IEC 80-) describes the measurement method and defines the levels of immunity to radiated electromagnetic fields. It was originally intended to simulate the electromagnetic fields generated by portable radio transceivers or any other devices that generate continuous wave-radiated EM energy. Its scope has since been broadened to include spurious EM energy that can be radiated from fluorescent lights, thyristor drives, inductive loads, and other sources. Testing for immunity involves irradiating the device with an EM field. There are various methods of achieving this, including use of anechoic chamber, stripline cell, TEM cell, and GTEM cell. A stripline cell consists of two parallel plates with an electric field developed between them. The device under test is placed within the cell and exposed to the electric field. There are three severity levels having field strengths ranging from V/m to 0 V/m. Results are classified in a similar fashion to those for IEC Classification : Normal operation. Classification : Temporary degradation or loss of function that is self recoverable when the interfering signal is removed. Classification : Temporary degradation or loss of function that requires operator intervention or system reset when the interfering signal is removed. Classification 4: Degradation or loss of function that is not recoverable due to damage. The ADMxxE family of products easily meets Classification at the most stringent requirement (Level ). In fact, field strengths up to 0 V/m showed no performance degradation, and errorfree data transmission continued even during irradiation. Rev. E Page of

14 ADM6E/ADM7E/ADM8E/ADME/ADME Table 0. Test Severity Levels (IEC ) Level Field Strength (V/m) 0 EMISSIONS/INTERFERENCE EN 0, CISPR defines the permitted limits of radiated and conducted interference from information technology (IT) equipment. The objective of the standard is to minimize the level of emissions, both conducted and radiated. For ease of measurement and analysis, conducted emissions are assumed to predominate below 0 MHz, and radiated emissions are assumed to predominate above 0 MHz. CONDUCTED EMISSIONS This is a measure of noise that is conducted onto the line power supply. Switching transients from the charge pump that are V in magnitude and that contain significant energy can lead to conducted emissions. Another source of conducted emissions is the overlap in switch-on times in the charge pump voltage converter. In the voltage doubler shown in Figure, if S has not fully turned off before S4 turns on, a transient current glitch occurs between VCC and that results in conducted emissions. Therefore, it is important that the switches in the charge pump guarantee break-before-make switching under all conditions so instantaneous short-circuit conditions do not occur. The ADMxxE have been designed to minimize the switching transients and ensure break-before-make switching, thereby minimizing conducted emissions. This results in emission levels well below specified limits. Other than the recommended 0. μf capacitor, no additional filtering/decoupling is required. Conducted emissions are measured by monitoring the line power supply. The equipment used consists of a line impedance stabilizing network (LISN) that essentially presents a fixed impedance at RF and a spectrum analyzer. The spectrum analyzer scans for emissions up to 0 MHz. A plot for the ADME is shown in Figure. V CC INTERNAL OSCILLATOR S S C S C S4 Figure. Charge Pump Voltage Doubler V = V CC V CC (dbµv) ø ø SWITCHING GLITCHES Figure. Switching Glitches LOG FREQUENCY (MHz) RADIATED EMISSIONS Figure. Conducted Emissions Plot LIMIT Radiated emissions are measured at frequencies in excess of 0 MHz. RS- outputs designed for operation at high baud rates while driving cables can radiate high frequency EM energy. The previously described causes of conducted emissions can also cause radiated emissions. Fast RS- output transitions can radiate interference, especially when lightly loaded and driving unshielded cables. Charge pump devices are also prone to radiating noise due to the high frequency oscillator and the high voltages being switched by the charge pump. The move toward smaller capacitors in order to conserve board space has resulted in higher frequency oscillators being employed in the charge pump design, resulting in higher levels of conducted and radiated emissions. The RS- outputs on the ADMxxE products feature a controlled slew rate in order to minimize the level of radiated emissions, yet they are fast enough to support data rates of up to kbps Rev. E Page 4 of

15 ADM6E/ADM7E/ADM8E/ADME/ADME RADIATED NOISE DUT TURNTABLE ADJUSTABLE ANTENNA TO RECEIVER 60 0 Figure 4. Radiated Emissions Test Setup Figure shows a plot of radiated emissions vs. frequency. The levels of emissions are well within specifications, without the need for any additional shielding or filtering components. The ADMxxE were operated at maximum baud rates and configured like a typical RS- interface (dbµv) START 0.0MHz STOP 0.0MHz Figure. Radiated Emissions LIMIT Testing for radiated emissions was carried out in a shielded anechoic chamber. Rev. E Page of

16 ADM6E/ADM7E/ADM8E/ADME/ADME OUTLINE DIMENSIONS.80 (.). (.7). (.4) PIN 0. (.) MAX 0.0 (.8) 0.0 (.0) 0. (.9) 0.0 (0.6) 0.08 (0.46) 0.04 (0.6) (.4) BSC (.78) (.) 0.04 (.4) 0.80 (7.) 0. (6.) 0.40 (6.0) 0.0 (0.8) MIN SEATING PLANE 0.00 (0.) MIN (.) MAX 0.0 (0.8) GAUGE PLANE 0. (8.6) 0.0 (7.87) 0.00 (7.6) 0.40 (0.9) MAX 0.9 (4.9) 0.0 (.0) 0. (.9) 0.04 (0.6) 0.00 (0.) (0.) COMPLIANT TO JEDEC STANDARDS MS-00-AF CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 6. 4-Lead Plastic Dual In-Line Package [PDIP] (N-4-) Dimensions shown in inches and (millimeters).60 (0.64). (0.984) (0.99) 7.40 (0.9) 0.6 (0.49) 0.00 (0.97) 0.0 (0.08) 0.0 (0.009) COPLANARITY.6 (0.04). (0.09) (0.000) 0. (0.0) SEATING 0. (0.00) BSC PLANE 0. (0.0) 0. (0.0079) (0.09) 0. (0.0098) 4.7 (0.000) 0.40 (0.07) COMPLIANT TO JEDEC STANDARDS MS-0-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 7. 4-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-4) Dimensions shown in millimeters and (inches) A Rev. E Page 6 of

17 ADM6E/ADM7E/ADM8E/ADME/ADME 8.0 (0.76) 7.70 (0.6969) (0.99) 7.40 (0.9) (0.49) 0.00 (0.97) 0.0 (0.08) 0.0 (0.009) COPLANARITY.6 (0.04). (0.09) (0.000) 0. (0.0) SEATING 0. (0.00) BSC PLANE 0. (0.0) 0. (0.0079) (0.09) 0. (0.0098) 4.7 (0.000) 0.40 (0.07) COMPLIANT TO JEDEC STANDARDS MS-0-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 8. 8-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-8) Dimensions shown in millimeters and (inches) A MAX MIN COPLANARITY BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-0-AG Figure 9. 4-Lead Shrink Small Outline Package [SSOP] (RS-4) Dimensions shown in millimeters A Rev. E Page 7 of

18 ADM6E/ADM7E/ADM8E/ADME/ADME MAX MIN COPLANARITY BSC SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-0-AH A Figure Lead Shrink Small Outline Package [SSOP] (RS-8) Dimensions shown in millimeters BSC PIN BSC COPLANARITY. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO--AD Figure 4. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters BSC PIN COPLANARITY BSC MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO--AE Figure 4. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters Rev. E Page 8 of

19 ADM6E/ADM7E/ADM8E/ADME/ADME ORDERING GUIDE Model Temperature Range Package Description Package Option ADM6EAR 40 C to 8 C 4-Lead SOIC_W RW-4 ADM6EAR-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM6EARZ 40 C to 8 C 4-Lead SOIC_W RW-4 ADM6EARZ-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM7EAN 40 C to 8 C 4-Lead PDIP N-4- ADM7EANZ 40 C to 8 C 4-Lead PDIP N-4- ADM7EAR 40 C to 8 C 4-Lead SOIC_W RW-4 ADM7EAR-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM7EARZ 40 C to 8 C 4-Lead SOIC_W RW-4 ADM7EARZ-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM7EARS 40 C to 8 C 4-Lead SSOP RS-4 ADM7EARS-REEL 40 C to 8 C 4-Lead SSOP RS-4 ADM7EARU 40 C to 8 C 4-Lead TSSOP RU-4 ADM7EARU-REEL 40 C to 8 C 4-Lead TSSOP RU-4 ADM7EARU-REEL7 40 C to 8 C 4-Lead TSSOP RU-4 ADM7EARUZ 40 C to 8 C 4-Lead TSSOP RU-4 ADM7EARUZ-REEL7 40 C to 8 C 4-Lead TSSOP RU-4 ADM8EAN 40 C to 8 C 4-Lead PDIP N-4- ADM8EANZ 40 C to 8 C 4-Lead PDIP N-4- ADM8EAR 40 C to 8 C 4-Lead SOIC_W RW-4 ADM8EAR-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM8EARZ 40 C to 8 C 4-Lead SOIC_W RW-4 ADM8EARZ-REEL 40 C to 8 C 4-Lead SOIC_W RW-4 ADM8EARS 40 C to 8 C 4-Lead SSOP RS-4 ADM8EARS-REEL 40 C to 8 C 4-Lead SSOP RS-4 ADM8EARSZ 40 C to 8 C 4-Lead SSOP RS-4 ADM8EARSZ-REEL 40 C to 8 C 4-Lead SSOP RS-4 ADM8EARU 40 C to 8 C 4-Lead TSSOP RU-4 ADM8EARU-REEL 40 C to 8 C 4-Lead TSSOP RU-4 ADM8EARU-REEL7 40 C to 8 C 4-Lead TSSOP RU-4 ADM8EARUZ 40 C to 8 C 4-Lead TSSOP RU-4 ADM8EARUZ-REEL 40 C to 8 C 4-Lead TSSOP RU-4 ADMEAR 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEAR-REEL 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARZ 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARZ-REEL 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARS 40 C to 8 C 8-Lead SSOP RS-8 ADMEARS-REEL 40 C to 8 C 8-Lead SSOP RS-8 ADMEARSZ 40 C to 8 C 8-Lead SSOP RS-8 ADMEARSZ-REEL 40 C to 8 C 8-Lead SSOP RS-8 ADMEARU 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARU-REEL 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARU-REEL7 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ-REEL 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ-REEL7 40 C to 8 C 8-Lead TSSOP RU-8 Rev. E Page 9 of

20 ADM6E/ADM7E/ADM8E/ADME/ADME Model Temperature Range Package Description Package Option ADMEAR 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEAR-REEL 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARZ 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARZ-REEL 40 C to 8 C 8-Lead SOIC_W RW-8 ADMEARS 40 C to 8 C 8-Lead SSOP RS-8 ADMEARS-REEL 40 C to 8 C 8-Lead SSOP RS-8 ADMEARSZ 40 C to 8 C 8-Lead SSOP RS-8 ADMEARSZ-REEL 40 C to 8 C 8-Lead SSOP RS-8 ADMEARU 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARU-REEL 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARU-REEL7 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ-REEL 40 C to 8 C 8-Lead TSSOP RU-8 ADMEARUZ-REEL7 40 C to 8 C 8-Lead TSSOP RU-8 Z = Pb-free part. 06 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C /06(E) Rev. E Page of