LED Application Design Guide Using Half-Bridge LLC Resonant Converter for 100W Street Lighting

Transcription

1 AN-979 LED Alicatin Design Guide Using Half-Bidge LLC Resnant Cnvete f 00W Steet Lighting Intductin This alicatin nte descibes the LED diving system using a half-bidge LLC esnant cnvete f high we LED lighting alicatins, such as utd steet lighting. Due t the existence f the nn-islatin DC-DC cnvete t cntl the LED cuent and the light intensity, the cnventinal PWM DC-DC cnvete has the blem f lw-we cnvesin efficiency. The half-bidge LLC cnvete can efm the LED cuent cntl and the efficiency can be significantly imved. Meve, the cst and the vlume f the whle LED diving system can be educed. Cnsideatin f LED Dive LED lighting is aidly elacing cnventinal lighting suces like incandescent bulbs, fluescent tubes, and halgens because LED lighting educes enegy cnsumtin. LED lighting has geate lngevity, cntains n txic mateials, and emits n hamful U ays, which ae 5 ~ 0 times lnge than fluescent tubes and incandescent bulbs. All metal halide and fluescent lams, including CFLs, n cntain mecuy. The amunt f cuent thugh an LED detees the light it emits. The LED chaacteistics detee the fwad vltage necessay t achieve the equied level f cuent. Due t the vaiatin in LED vltage vesus cuent chaacteistics, cntlling nly the vltage acss the LED leads t vaiability in light utut. Theefe, mst LED dives use cuent egulatin t sut bightness cntl. Bightness can be cntlled diectly by changing the LED cuent. Cnsideatin f LLC Resnant Cnvete The attemt t btain eve-inceasing we density f switched-mde we sulies has been limited by the size f assive cmnents. Oeatin at highe fequencies cnsideably educes the size f assive cmnents, such as tansfmes and filtes; hweve, switching lsses have been an bstacle t high-fequency eatin. T educe switching lsses and allw highfequency eatin, esnant switching techniques have been develed. These techniques cess we in a sinusidal manne and the switching devices ae sftly cmmutated. Theefe, the switching lsses and nise can be damatically educed [-7]. Amng vaius kinds f esnant cnvetes, the simlest and mst ula is the LC seies esnant cnvete, whee the ectifie-lad netwk is laced in seies with the L-C esnant netwk, as deicted in Figue [-4]. In this cnfiguatin, the esnant netwk and the lad act as a vltage divide. By changing the fequency f diving vltage d, the imedance f the esnant netwk changes. The inut vltage is slit between this imedance and the eflected lad. Since it is a vltage divide, the DC gain f a LC seies esnant cnvete is always <. At light-lad cnditin, the imedance f the lad is lage cmaed t the imedance f the esnant netwk; all the inut vltage is imsed n the lad. This makes it difficult t egulate the utut at light lad. Theetically, fequency shuld be infinite t egulate the utut at n lad. Figue. Half-Bidge, LC Seies Resnant Cnvete T vecme the limitatin f seies esnant cnvetes, the LLC esnant cnvete has been sed [8-]. The LLC esnant cnvete is a mdified LC seies esnant cnvete imlemented by lacing a shunt induct acss the tansfme imay winding, as deicted in Figue. When this tlgy was fist esented, it did nt eceive much attentin due t the cunteintuitive cncet that inceasing the ciculating cuent in the imay side with a shunt induct can be beneficial t cicuit eatin. Hweve, it can be vey effective in imving efficiency f high-inut vltage alicatins whee the switching lss is me dant than the cnductin lss. In mst actical designs, this shunt induct is ealized using the magnetizing inductance f the tansfme. The cicuit diagam f LLC esnant cnvete lks much the same as the LC seies esnant cnvete: the nly diffeence is the value f the magnetizing induct. While the seies esnant cnvete has a magnetizing inductance lage than the LC seies esnant induct (L, the magnetizing inductance in an LLC esnant cnvete is just 3~8 times L, which is usually imlemented by intducing an ai ga in the tansfme. 0 Faichild Semicnduct Catin Rev..0. /6/

2 AN-979 Figue. Half-Bidge LLC Resnant Cnvete An LLC esnant cnvete has many advantages ve a seies esnant cnvete. It can egulate the utut ve wide line and lad vaiatins with a elatively small vaiatin f switching fequency. It can achieve ze vltage switching (ZS ve the entie eating ange. All essential aasitic elements, including junctin caacitances f all semicnduct devices and the leakage inductance and magnetizing inductance f the tansfme, ae utilized t achieve sft switching. This alicatin nte esents design cnsideatins f an LLC esnant half-bidge cnvete emlying Faichild s FLS-XS seies. It includes exlanatin f the LLC esnant cnvete eatin inciles, designing the tansfme and esnant netwk, and selecting the cmnents. The ste-by-ste design cedue, exlained with a design examle, hels design the LLC esnant cnvete. LLC Resnant Cnvete and Fundamental Aximatin Figue 3 shws a simlified schematic f a half-bidge LLC esnant cnvete, whee L m is the magnetizing inductance that acts as a shunt induct, L is the seies esnant induct, and C is the esnant caacit. Figue 4 illustates the tyical wavefms f the LLC esnant cnvete. It is assumed that the eatin fequency is same as the esnance fequency, deteed by the esnance between L and C. Since the magnetizing induct is elatively small, a cnsideable amunt f magnetizing cuent (I m exists, which feewheels in the imay side withut being invlved in the we tansfe. The imay-side cuent (I is sum f the magnetizing cuent and the secnday-side cuent efeed t the imay. In geneal, the LLC esnant tlgy cnsists f thee stages shwn in Figue 3; squae-wave geneat, esnant netwk, and ectifie netwk. The squae-wave geneat duces a squae-wave vltage, d, by diving switches Q and Q altenately with 50% duty cycle f each switch. A small dead time is usually intduced between the cnsecutive tansitins. The squae-wave geneat stage can be built as a full-bidge half-bidge tye. The esnant netwk cnsists f a caacit, leakage inductances, and the magnetizing inductance f the tansfme. The esnant netwk filtes the highe hamnic cuents. Essentially, nly sinusidal cuent is allwed t flw thugh the esnant netwk even thugh a squae-wave vltage is alied t the esnant netwk. The cuent (I lags the vltage alied t the esnant netwk (that is, the fundamental cmnent f the squae-wave vltage ( d alied t the half-bidge ttem le, which allws the MOSFETs t be tuned n with ze vltage. As shwn in Figue 4, the MOSFET tuns n while the vltage acss the MOSFET is ze by flwing cuent thugh the anti-aallel dide. The ectifie netwk duces DC vltage by ectifying the AC cuent with ectifie dides and a caacit. The ectifie netwk can be imlemented as a full-wave bidge cente-taed cnfiguatin with caacitive utut filte. Squae-Wave Geneat IN I DS I D Q d Q I DS + d - C L I m Resnant Netwk L m I n: Rectifie Netwk Figue 3. Schematic f Half-Bidge LLC Resnant Cnvete gs gs I I m IN Figue 4. Tyical Wavefms f Half-Bidge LLC Resnant Cnvete The filteing actin f the esnant netwk allws use f the fundamental aximatin t btain the vltage gain f the esnant cnvete, which assumes that nly the fundamental cmnent f the squae-wave vltage inut t the esnant netwk cntibutes t the we tansfe t the utut. Because the ectifie cicuit in the secnday side acts as an imedance tansfme, the equivalent lad esistance is diffeent fm actual lad I D R I + O - 0 Faichild Semicnduct Catin Rev..0. /6/

3 AN-979 esistance. Figue 5 shws hw this equivalent lad esistance is deived. The imay-side cicuit is elaced by a sinusidal cuent suce, I ac, and a squae wave f vltage, RI, aeas at the inut t the ectifie. Since the aveage f I ac is the utut cuent, I, I ac, is btained as: I ac I sin( t ( and RI is given as: IN d + - C L L m 8n n=n /N s Rac R N:Ns + RI - + O R - RI if sin( t 0 ( RI if sin( t 0 whee is the utut vltage. The fundamental cmnent f RI is given as: F 4 RI sin( t (3 Since hamnic cmnents f RI ae nt invlved in the we tansfe, AC equivalent lad esistance can be calculated by dividing F RI by I ac as: R ac F RI 8 8 R I (4 ac I Cnsideing the tansfme tuns ati (n=n /N s, the equivalent lad esistance shwn in the imay side is btained as: 8n R R (5 ac By using the equivalent lad esistance, the AC equivalent cicuit is btained, as illustated in Figue 6, whee F d and F RO ae the fundamental cmnents f the diving vltage, d, and eflected utut vltage, RO (n RI, esectively. k I ac I ac I F RI sin( wt 4 sin( wt Figue 5. Deivatin f Equivalent Lad Resistance R ac d F C L L m R ac R F (n RI F Figue 6. AC Equivalent Cicuit f LLC Resnant Cnvete With the equivalent lad esistance btained in Equatin 5, the chaacteistics f the LLC esnant cnvete can be deived. Using the AC equivalent cicuit f Figue 6, the vltage gain, M, is btained as: 4n F F sin( t RO nri n M F F 4 d d in sin( t in (6 ( ( m ( j ( ( m Q whee: 8n L L Lm L, Rac R, m L L Q,, C R LC LC ac As can be seen in Equatin (6, thee ae tw esnant fequencies. One is deteed by L and C, while the the is deteed by L and C. Equatin (6 shws the gain is unity at esnant fequency (ω, egadless f the lad vaiatin, which is given as: n ( m M at (7 in The gain f Equatin (6 is ltted in Figue 7 f diffeent Q values with m=3, f =00kHz, and f =57kHz. As bseved in Figue 7, the LLC esnant cnvete shws gain chaacteistics that ae almst indeendent f the lad when the switching fequency is aund the esnant fequency, f. This is a distinct advantage f LLC-tye esnant cnvete ve the cnventinal seies esnant cnvete. Theefe, it is natual t eate the cnvete aund the esnant fequency t imize the switching fequency vaiatin. The eating ange f the LLC esnant cnvete is limited by the eak gain (attainable imum gain, which is indicated with * in Figue 7. Nte that the eak vltage gain des nt ccu at f f. The eak gain fequency whee the eak gain is btained exists between 0 Faichild Semicnduct Catin Rev..0. /6/ 3

4 AN-979 f and f, as shwn in Figue 7. As Q deceases (as lad deceases, the eak gain fequency mves t f and highe eak gain is btained. Meanwhile, as Q inceases (as lad inceases, the eak gain fequency mves t f and the eak gain ds; the full lad cnditin shuld be wst case f the esnant netwk design. f LC M f f Q L / C Rac Figue 7. Tyical Gain Cuves f LLC Resnant Cnvete (m=3 Cnsideatin f Integated Tansfme F actical design, it is cmmn t imlement the magnetic cmnents (seies induct and shunt induct using an integated tansfme; whee the leakage inductance is used as a seies induct, while the magnetizing induct is used as a shunt induct. When building the magnetizing cmnents in this way, the equivalent cicuit in Figue 6 shuld be mdified as shwn in Figue 8 because leakage inductance exists, nt nly in the imay side, but als in the secnday side. Nt cnsideing the leakage inductance in the tansfme secnday side geneally esults in an ineffective design. L L L n L Llk Lm // Llk L L L lk m //( lks lk m : M L ( M L L R ac Figue 8. Mdified Equivalent Cicuit t Accmmdate the Secnday-Side Leakage Inductance In Figue 8, the effective seies induct (L and shunt induct (L -L ae btained by assug n L lks =L lk and efeing the secnday-side leakage inductance t the imay side as: L Lm Llk (8 L Llk Lm //( n Llks Llk Lm // Llk When handling an actual tansfme, equivalent cicuit with L and L is efeed since these values can be measued with a given tansfme. In an actual tansfme, L and L can be measued in the imay side with the secnday-side winding en cicuited and sht cicuited, esectively. In Figue 9, ntice that a vitual gain M is intduced, which is caused by the secnday-side leakage inductance. By adjusting the gain equatin f Equatin (6 using the mdified equivalent cicuit f Figue 9, the gain equatin f integated tansfme is btained by: n M in O ( ( m M e ( j( ( ( m Q ( mm ( ( j( ( ( m Q whee: (9 e 8n R L Rac, m M L e L Q,, e C R LC LC ac The gain at the esnant fequency (ω is fixed egadless f the lad vaiatin, which is given as: L m M M at (0 L L m The gain at the esnant fequency (ω is unity when using individual ce f seies induct, as shwn in Equatin 7. Hweve, when imlementing the magnetic cmnents with integated tansfme, the gain at the esnant fequency (ω is lage than unity due t the vitual gain caused by the leakage inductance in the tansfme secnday side. The gain f Equatin (9 is ltted in Figue 0 f diffeent Q e values with m=3, f =00kHz, and f =57kHz. As bseved in Figue 9, the LLC esnant cnvete shws gain chaacteistics almst indeendent f the lad when the switching fequency is aund the esnant fequency, f. e 0 Faichild Semicnduct Catin Rev..0. /6/ 4

5 AN-979 f L C f LC Gain (M B e Q L / C e Rac A Lad Incease I II Belw Resnance (f s <f Abve Resnance (f s>f f M f f s Figue 0. Oeatin Mdes Accding t the Oeatin Fequency Figue 9. Tyical Gain Cuves f LLC Resnant Cnvete (m=3 Using an Integated Tansfme Cnsideatin f Oeatin Mde and Attainable Maximum Gain Oeatin Mde The LLC esnant cnvete can eate at fequency belw abve the esnance fequency (f, as illustated in Figue 0. Figue shws the wavefms f the cuents in the tansfme imay side and secnday side f each eatin mde. Oeatin belw the esnant fequency (case I allws the sft cmmutatin f the ectifie dides in the secnday side, while the ciculating cuent is elatively lage. The ciculating cuent inceases me as the eatin fequency mves dwnwad fm the esnant fequency. Meanwhile, eatin abve the esnant fequency (case II allws the ciculating cuent t be imized, but the ectifie dides ae nt sftly cmmutated. Belw-esnance eatin is efeed f high utut vltage alicatins, such as steet LED lighting systems whee the evese-ecvey lss in the ectifie dide is sevee. Belw-esnance eatin has a naw fequency ange with esect t the lad vaiatin since the fequency is limited belw the esnance fequency even at n-lad cnditin. On the the hand, abve-esnance eatin has less cnductin lss than the belw-esnance eatin. It can shw bette efficiency f lw utut vltage alicatins, such as Liquid Cystal Dislay (LCD T lat adat, whee Schttky dides ae available f the secnday-side ectifies and evese-ecvey blems ae insignificant. Hweve, eatin abve the esnant fequency may cause t much fequency incease at light-lad cnditin. Abve-fequency eatin equies fequency skiing t event t much incease f the switching fequency. f f S Figue. Wavefms f Each Oeatin Mde Requied Maximum Gain and Peak Gain Abve the eak gain fequency, the inut imedance f the esnant netwk is inductive and the inut cuent f the esnant netwk (I lags the vltage alied t the esnant netwk ( d. This emits the MOSFETs t tun n with ze vltage (ZS, as illustated in Figue. Meanwhile, the inut imedance f the esnant netwk becmes caacitive and I leads d belw the eak gain fequency. When eating in caacitive egin, the MOSFET bdy dide is evese ecveed duing the switching tansitin, which esults in sevee nise. Anthe blem f enteing the caacitive egin is that the utut vltage becmes ut f cntl since the sle f the gain is evesed. The imum switching fequency shuld be limited abve the eak gain fequency. 0 Faichild Semicnduct Catin Rev..0. /6/ 5

6 AN-979 d M Caacitive Regin Peak Gain d Inductive Regin f s Even thugh the eak gain at a given cnditin can be btained using the gain in Equatin (6, it is difficult t exess the eak gain in exlicit fm. T simlify the analysis and design, the eak gains ae btained using simulatin tls and deicted in Figue 4, which shws hw the eak gain (attainable imum gain vaies with Q f diffeent m values. It aeas that highe eak gain can be btained by educing m Q values. With a given esnant fequency (f and Q value, deceasing m means educing the magnetizing inductance, which esults in inceased ciculating cuent. Thee is a tade-ff between the available gain ange and cnductin lss. I I.. I DS I DS Revese Recvey ZS Figue. Oeatin Wavefms f Caacitive and Inductive Regins The available inut vltage ange f the LLC esnant cnvete is deteed by the eak vltage gain. Thus, the esnant netwk shuld be designed s that the gain cuve has an enugh eak gain t cve the inut vltage ange. Hweve, ZS cnditin is lst belw the eak gain int, as deicted in Figue. Theefe, sme magin is equied when deteing the imum gain t guaantee stable ZS eatin duing the lad tansient and statu. Tyically 0~0% f the imum gain is used as a magin, as shwn in Figue 3. Gain (M 0~0% f M Peak Gain Maximum Oeatin Gain (M Peak Gain m=3.0 m=3.5 m=4.0 m=4.5 m=5.0 m=6.0 m=9.0 m=8.0 m=7.0 m=.5 m= Q Figue 4. Peak Gain (Attainable Maximum Gain vs. Q f Diffeent m alues f f s Figue 3. Deteing the Maximum Gain 0 Faichild Semicnduct Catin Rev..0. /6/ 6

7 AN-979 Featues f FLS-XS Seies FLS-XS seies is an integated Pulse Fequency Mdulatin (PFM cntlle and MOSFETs secifically designed f Ze ltage Switching (ZS half-bidge cnvetes with imal extenal cmnents. The intenal cntlle includes an unde-vltage lckut, timized high-side / lw-side gate dive, temeatuecmensated ecise cuent cntlled scillat, and self-tectin cicuity. Cmaed with discete MOSFET and PWM cntlle slutins, FLS-XS seies can educe ttal cst, cmnent cunt, size, and weight; while simultaneusly inceasing efficiency, ductivity, and system eliability. Figue 5. Package Diagam Table. Pin Descitin Pin# Name Descitin DL AR 3 R T 4 CS This in is the dain f the high-side MOSFET, tyically cnnected t the inut DC link vltage. This in is f dischaging the extenal sft-stat caacit when any tectins ae tiggeed. When the vltage f this in ds t 0., all tectins ae eset and the cntlle stats t eate again. This in is t gam the switching fequency. Tyically, t-cule and esist ae cnnected t this in t egulate the utut vltage. This in is t sense the cuent flwing thugh the lw-side MOSFET. Tyically negative vltage is alied n this in. 5 SG This in is the cntl gund. 6 PG This in is the we gund. This in is cnnected t the suce f the lwside MOSFET. 7 L CC This in is the suly vltage f the cntl IC. 8 NC N cnnectin. 9 H CC 0 CTR This in is the suly vltage f the high-side dive cicuit. This in is the dain f the lw-side MOSFET. Tyically tansfme is cnnected t this in. L CC DL 7 REF REF IRT IRT IRT 3 S R Q LCC Gd LU+ / LU- REF Intenal Bias HU+ / HU- 9 H CC R T 3 Time Delay 350ns Level Shifte High-Side Gate Dive 0 CTR Divide AR 5k CssH / CssL Time Delay 350ns Balancing Delay Lw-Side Gate Dive LCC gd S R Q Shutdwn TSD AOCP LCC OP Delay 50ns Delay.5 s OCP - 6 PG 5 SG 4 CS Figue 6. Functinal Blck Diagam f FSFR-Seies 0 Faichild Semicnduct Catin Rev..0. /6/ 7

8 AN-979 FLS-XS Seies Figue 7. Refeence Cicuit f Design Examle f LLC Resnant Half-Bidge Cnvete Design Pcedue In this sectin, a design cedue is esented using the schematic in Figue 7 as a efeence. An integated tansfme with cente ta, secnday side is used and inut is sulied fm Pwe Fact Cectin (PFC eegulat. A DC-DC cnvete with 00W/00 utut has been selected as a design examle. The design secificatins ae as fllws: Nal inut vltage: 400 DC (utut f PFC stage Outut: 00/A (00W Hld-u time equiement: 30ms (50Hz line feq. DC link caacit f PFC utut: 40µF [STEP-] Define System Secificatins Estimated Efficiency (E ff : The we cnvesin efficiency must be estimated t calculate the imum inut we with a given imum utut we. If n efeence data is available, use E ff = 0.88~0.9 f lwvltage utut alicatins and E ff = 0.9~0.96 f highvltage utut alicatins. With the estimated efficiency, the imum inut we is given as: P P ( in E ff Inut ltage Range ( in and in : The imum inut vltage wuld be the nal PFC utut vltage as: in ( O. PFC Even thugh the inut vltage is egulated as cnstant by PFC e-egulat, it ds duing the hld-u time. The imum inut vltage cnsideing the hld-u time equiement is given as: in O. PFC P in T HU (3 C DL whee O.PFC is the nal PFC utut vltage, T HU is a hld-u time, and C DL is the DC link bulk caacit. (Design Examle Assug the efficiency is 9%, P 00 Pin 09W E ff 0.9 in O. PFC 400 in O. PFC PinT C DL HU 364 [STEP-] Detee Maximum and Minimum ltage Gains f the Resnant Netwk As discussed in the evius sectin, it is tyical t eate the LLC esnant cnvete aund the esnant fequency (f t imize switching fequency vaiatin. Since the inut f the LLC esnant cnvete is sulied fm PFC utut vltage, the cnvete shuld be designed t eate at f f the nal PFC utut vltage. 0 Faichild Semicnduct Catin Rev..0. /6/ 8

9 AN-979 As bseved in Equatin (0, the gain at f is a functin f m (m=l /L. The gain at f is deteed by chsing that value f m. While a highe eak gain can be btained with a small m value, t small m value esults in culing f the tansfme and deteiates the efficiency. It is tyical t set m t be 3~7, which esults in a vltage gain f.~. at the esnant fequency (f. With the chsen m value, the vltage gain f the nal PFC utut vltage is btained as: m M (4 which wuld be the imum gain because the nal PFC utut vltage is the imum inut vltage ( in. The imum vltage gain is given as: in M M (5 in (Design Examle The ati (m between L and L is chsen as 5. The imum and imum gains ae btained as: RO M in m m 400 M in m in M M Gain (M M m. m 5. 5 Peak Gain (Available Maximum Gain.3. f IN f IN ( O.PFC [STEP-4] Calculate Equivalent Lad Resistance With the tansfme tuns ati btained fm Equatin (6, the equivalent lad esistance is btained as: 8n R ac P (7 (Design Examle 8n ( F R ac 405 P 00 [STEP-5] Design the Resnant Netwk With m value chsen in STEP-, ead e Q value fm the eak gain cuves in Figue 4 that allws enugh eak gain. Cnsideing the lad tansient and stable zevltage-switching (ZS eatin, 0~0% magin shuld be intduced n the imum gain when deteing the eak gain. Once the Q value is deteed, the esnant aametes ae btained as: C (8 Q f Rac L ( f C (9 L m L (0 (Design Examle Fm STEP-, the imum vltage gain (M f the imum inut vltage ( in is.3. With 5% magin, a eak gain f.4 is equied. m has been chsen as 5 in STEP- and Q is btained as 0.4 fm the eak gain cuves in Figue 9. By selecting the esnant fequency as 00kHz, the esnant cmnents ae deteed as: C 9. 35nF Q f R 3 ac L 7H 3 9 (f C ( L m L 355H Figue 8. Maximum Gain / Minimum Gain f f s [STEP-3] Detee the Tansfme Tuns Rati (n=n /N s With the imum gain (M btained in STEP-, the tansfme tuns ati is given as: N in n M (6 Ns ( F whee F is the secnday-side ectifie dide vltage d. (Design Examle assug F is 0.9, N in 400 n M.. N ( ( s O F Figue 9. Resnant Netwk Design Using the Peak Gain (Attainable Maximum Gain Cuve f m=5 0 Faichild Semicnduct Catin Rev..0. /6/ 9

10 AN-979 [STEP-6] Design the Tansfme The wst case f the tansfme design is the imum switching fequency cnditin, which ccus at the imum inut vltage and full-lad cnditin. T btain the imum switching fequency, lt the gain cuve using gain Equatin 9 and ead the imum switching fequency. The imum numbe f tuns f the tansfme imay-side is btained as: N n ( f M B A F s e ( whee A e is the css-sectinal aea f the tansfme ce in m and B is the imum flux density swing in Tesla, as shwn in Figue 0. If thee is n efeence data, use B =0.3~0.4 T. RI B /(f s n ( + F /M -n ( + F /M B Figue 0. Flux Density Swing Chse the e numbe f tuns f the secnday side that esults in imay-side tuns lage than N as: N n Ns N ( Figue. Gain Cuve [STEP-7] Tansfme Cnstuctin Paametes L and L f the tansfme wee deteed in STEP-5. L and L can be measued in the imay side with the secnday-side winding en cicuited and sht cicuited, esectively. Since LLC cnvete design equies a elatively lage L, a sectinal bbbin is tyically used, as shwn in Figue, t btain the desied L value. F a sectinal bbbin, the numbe f tuns and winding cnfiguatin ae the maj facts deteing the value f L, while the ga length f the ce des nt affect L much. L can be cntlled by adjusting the ga length. Table shws measued L and L values with diffeent ga lengths. A ga length f 0.05mm btains values f L and L clsest t the designed aametes. N (Design Examle EER354 ce (A e =07mm is selected f the tansfme. Fm the gain cuve f Figue, the imum switching fequency is btained as 70KHz. The imum imay-side tuns f the tansfme is given as: n( F N f s B. Ae tuns Figue. Sectinal Bbbin N s N s Chse N s s that the esultant N is lage than N : N n Ns.3 9 N N n Ns.4 3 N N n Ns.5 33 N N n Ns.6 36 N N n Ns.7 38 N Table. Measued L and L with Diffeent Ga Lengths Ga Length L L 0.0mm,95μH 3μH 0.05mm 943μH μh 0.0mm 630μH 8μH 0.5mm 488μH 7μH 0.0mm 49μH 5μH 0.5mm 366μH 4μH 0 Faichild Semicnduct Catin Rev..0. /6/ 0

11 AN-979 (Design Examle Final Resnant Netwk Design Even thugh the integated tansfme aach in LLC esnant cnvete design can imlement the magnetic cmnents in a single ce and save ne magnetic cmnent, the value f L is nt easy t cntl in eal tansfme design. Resnant netwk design smetimes equies iteatin with a esultant L value afte the tansfme is built. The esnant caacit value is als changed since it shuld be selected amng ff-the-shelf caacits. The final esnant netwk design is summaized in Table 3 and the new gain cuves ae shwn in Figue 3. Table 3. Final Resnant Netwk Design Paametes Paametes Initial Design Final Design L 365µH 850µH L 73H 70µH C 9.3nF 5nF f 00kHz 99.7kHz m 5 5 Q M@f.. Minimum Fequency 80kHz 80kHz f f nmal 00% lad 80% lad 60% lad 40% lad 0% lad M M The nal vltage f the esnant caacit in nmal eatin is given as: I (4 RMS nm in C C f C Hweve, the esnant caacit vltage inceases much highe at velad cnditin lad tansient. Actual caacit selectin shuld be based n the Ove-Cuent Ptectin (OCP ti int. With the OCP level, IOCP, the imum esnant caacit vltage is btained as: I C (5 nm in OCP C f (Design Examle RMS IC 0.9 =0.78A E ff [. I O [ ] [ n 4 ] n( F ] f M ( L L v.( [ ] The eak cuent in the imay side in nmal eatin is: eak ms I I.03A C C OCP level is set t.75a with 50% magin n I C eak : RMS nm I in C C f C in IOCP C f C A 630 ated lw-esr film caacit is selected f the esnant caacit Fequency (KHz Figue 3. Gain Cuve f the Final Resnant Netwk Design [STEP-8] Select the Resnant Caacit When chsing the esnant caacit, the cuent ating shuld be cnsideed because a cnsideable amunt f cuent flws thugh the caacit. The RMS cuent thugh the esnant caacit is given as: I I n( [ ] [ ] RMS F C E ff n 4 fm( L L (3 [STEP-9] Rectifie Netwk Design When the cente ta winding is used in the tansfme secnday side, the dide vltage stess is twice f the utut vltage exessed as: D ( F (6 The RMS value f the cuent flwing thugh each ectifie dide is given as: RMS ID I (7 4 Meanwhile, the ile cuent flwing thugh utut caacit is given as: RMS I 8 C ( I I I (8 8 0 Faichild Semicnduct Catin Rev..0. /6/

12 AN-979 The vltage ile f the utut caacit is: (9 I RC whee R C is the effective seies esistance (ESR f the utut caacit and the we dissiatin is the utut caacit is: RMS PLss. C ( IC R (30 C (Design Examle The vltage stess and cuent stess f the ectifie dide ae: D ( F ( RMS I D I A 4 The 600/8A Ulta fast ecvey dide is selected f the ectifie, cnsideing the vltage vesht caused by the stay inductance. The RMS cuent f the utut caacit is: RMS I 8 IC ( I I 0. 48A 8 When tw electlytic caacits with ESR f 00m ae used in aallel, the utut vltage ile is given as: 0. I RC ( The lss in electlytic caacits is: RMS PLss, C ( IC RC W [STEP-0] Cntl Cicuit Cnfiguatin Figue 4 shws the tyical cicuit cnfiguatin f the RT in f FLS-XS seies, whee the t-cule tansist is cnnected t the RT in t cntl the switching fequency. The imum switching fequency ccus when the tcule tansist is fully tuned ff, which is given as: f 5.k 00( khz (3 R Assug the satuatin vltage f the t-cule tansist is 0., the imum switching fequency is deteed as: f 5.k 4.68k ( 00( khz (3 R R Figue 4. Tyical Cicuit Cnfiguatin f RT Pin Sft-Stat T event excessive inush cuent and vesht f utut vltage duing statu, incease the vltage gain f the esnant cnvete gessively. Since the vltage gain f the esnant cnvete is evesely tinal t the switching fequency, sft-stat is imlemented by sweeing dwn the switching fequency fm an initial high fequency (f ISS until the utut vltage is established, as illustated in Figue 5. The sftstat cicuit is made by cnnecting RC seies netwk n the RT in as shwn in Figue 4. FLS-XS seies als has an intenal sft-stat f 3ms t educe the cuent vesht duing the initial cycles, which adds 40KHz t the initial fequency f the extenal sft-stat cicuit, as shwn in Figue 5. The actual initial fequency f the sft-stat is given as: ISS 5.k 5.k f ( ( khz (33 R R SS It is tyical t set the initial fequency f sft-stat (f ISS as ~3 times f the esnant fequency (f. The sft-stat time is deteed by the RC time cnstant: TSS 3~4timesf RSS C (34 SS Figue 5. Fequency Swee f the Sft-Stat 0 Faichild Semicnduct Catin Rev..0. /6/

13 AN-979 (Design Examle The imum fequency is 80kHz in STEP-6. R is deteed as: 00KHz R 5.K 6. 5K f Cnsideing the utut vltage vesht duing tansient (0% and the cntllability f the feedback l, the imum fequency is set as 40kHz. R is deteed as: 4.68K R f.40 5.K ( 00KHz R 4.68K 7.8K 99KHz.40 5.K ( 00KHz 6.5K Setting the initial fequency f sft-stat as 50kHz (.5 times f the esnant fequency, the sft-stat esist R SS is given as: 5.K RSS f ISS 40KHz 5.K ( 00KHz R 5.K 4K 50KHz 40KHz 5.K ( 00KHz 6.5K [STEP-] Cuent Sensing and Ptectin FLS-XS seies senses lw-side MOSFET dain cuent as a negative vltage, as shwn in Figue 6 and Figue 7. Half-wave sensing allws lw-we dissiatin in the sensing esist, while full-wave sensing has less switching nise in the sensing signal. Tyically, RC lwass filte is used t filte ut the switching nise in the sensing signal. The RC time cnstant f the lw-ass filte shuld be /00~/0 f the switching eid. (Design Examle Since the OCP level is deteed as.75a in STEP-8 and the OCP theshld vltage is -0.6, a sensing esist f 0.33 is used. The RC time cnstant is set t 00ns (/00 f switching eid with kesist and 00F caacit. [STEP-] ltage and Cuent Feedback Pwe sulies f LED lighting must be cntlled by Cnstant Cuent (CC Mde as well as a Cnstant ltage (C Mde. Because the fwad-vltage d f LED vaies with the junctin temeatue and the cuent als inceases geatly cnsequently, devices can be damaged. Figue 8 shws an examle f a CC and C Mde feedback cicuit f single utut LED we suly. Duing nmal eatin, CC Mde is dant and C cntl cicuit des nt activate as lng as the feedback vltage is lwe than efeence vltage, which means that C cntl cicuit nly acts as OP f abnmal mdes. (Design Examle The utut vltage ( O is 00 in design taget. O is deteed as: RFU.5( RFL Set the ue-side feedback esistance (R FU as 330K. R FL is deteed as:.5 RFU.5 330K RFL 8. 46K (.5 (00.5 The utut vltage f -am is given as: sense REF sc0oc 0 R0 R03 sc0 R0 R03 sense REF OC ( sc0 R0 R03 Actually, the sense has a negative value and assume all esists have the same value f simlificatin; OC ( sense REF sc0 R The utut vltage f the -am f CC cntl kees ze vltage as lng as the sensing vltages ae lwe than the efeence vltage. Figue 6. Half-Wave Sensing Figue 7. Full-Wave Sensing Figue 8. Examle f CC and C Feedback Cicuit 0 Faichild Semicnduct Catin Rev..0. /6/ 3

14 AN-979 Figue 9 shws anthe examle f a CC and Ove- ltage Regulatin (OR Mde feedback cicuit f multi-utut LED we suly. The FAN7346 is a LED cuent-balance cntlle that cntls fu LED aays t maintain equal LED cuent. T event LED diving vltage being ve the withstanding vltage f cmnent, the FAN7346 cntls LED diving vltage. The OR cntl cicuit activates when the ENA in is in HIGH state. If OR in vltage is lwe than.5, the Feedback Cntl (FB in vltage fllws headm cntl t maintain imum vltage f dain vltages as. If OR in vltage is highe than.5, the FAN7346 cntls FB (FB is ulled LOW thugh FB egulatin s the OR in vltage is nt ve.5. LED cuent is cntlled by FBx in vltage. The extenal cuent balance switch is eating in linea egin t cntl LED cuent. Sensed vltage at the FBx in is cmaed with intenal efeence vltage and cntlle signals the gate ( base f extenal cuent balance switch. Intenal efeence vltage is made fm ADIM vltage. The LED cuent is deteed as: I LED ADIM RSENSE 0 (35 ADIM vltage is clamed intenally fm 0.5 t 4. The tectins; such as en LED Ptectin (OLP, Sht LED Ptectin (SLP, and Ove-Cuent Ptectin (OCP; which incease system eliability, ae alied in individual sting tectin methd. T sense a sht LED cnditin, the FAN7346 senses dain vltage level. If LEDs ae shted, the LED fwad vltage is lwe than the LED stings, s its dain vltage f extenal balance switch is highe than the dain vltage. The SLP cnditin detectin theshld vltage can be gammed by SLPR vltage. The intenal sht LED tectin efeence is deteed as: SLP _ TH 0 SLPR (36 Minimum SLP theshld vltage is 0 and imum SLP theshld vltage is 45. If any sting is in SLP cnditin, SLP sting is tuned ff and the sting is eated nmally. If the sensed dain vltage (CHx vltage is highe than the gammed theshld vltage f 0µs, CHx ges t sht LED tectin. As sn as encunteing SLP, the cesnding channel is fced ff. T sense an en LED cnditin, the FAN7346 senses dain vltage level. If LED sting is ened, its dain vltage f extenal balance switch is gunded, s the FAN7346 detects the en-led cnditin. The detectin theshld vltage is 0.3. If CHx vltage is lwe than 0.3 f 0µs, its dain vltage feedback is ulled u t 5. This means the ened LED sting is eliated fm dain feedback l. Withut OLP, imum dain vltage is 0, s dain vltage feedback fces the FB signal t incease utut we. This can cause SLP themal stess blems in the the channel. OLP functin has aut-ecvey: As sn as dain vltage is highe than 0.3, OLP is finished and dain vltage feedback system is ested. T sense ve-cuent cnditin, the FAN7346 mnits FBx in vltage. If FBx vltage is highe than f 0µs, CHx is cnsideed in ve-cuent cnditin. Afte sensing OCP cnditin, individual channel switch is latched ff. S, even if a channel is in OCP cnditin, the channels kee eating. Any OCP channel is estated afte ULO is eset. (Design Examle The utut vltage ( O is 00 in design taget. O is deteed as: R8.5( R0 Set the ue-side feedback esistance (R8 as M. R0 is deteed as:.5 R8.5M R0 5.3K (.5 (00.5 The utut channel cuent (I LED is 50mA in design taget. Setting the ADIM is abve 4, the cuent sense R SENSE is deteed as: ADIM 4 RSENSE. 0 I 0 50mA 6 LED Chse the sense esist (R9, R30, R3, and R3 is.5, the OCP level is deteed as: OCP _ TH IOCP 666mA R.5 RS RS4 CS RS0 RS8 CS5 RS9 RS7 SENSE CS4 RS3 CS9 CS8 Figue 9. Examle f CC and OR Feedback Cicuit CS7 RS9 CS0 RS30 CS RS3 CS3 RS3 0 Faichild Semicnduct Catin Rev..0. /6/ 4

15 AN-979 Design Summay Figue 30 and Figue 3 shw the final schematic f the LLC esnant half-bidge cnvete f LED lighting design examle. EER3543 ce with sectinal bbbin is used f the tansfme. Efficiency at full-lad is aund 94%. Figue 30. Final Schematic f Half-Bidge LLC Resnant Cnvete f Single Channel RS3 CS3 RS5 RS3 CS RS3 RS30 CS0 RS6 RS9 CS7 RS FLS-XS Seies FAN7346 GND FB4 ADIM OUT4 CH4 SLPR FB3 ENA OUT3 CH3 FB FB MIN OUT CH FB REF PWM PWM OUT CH OR CC PWM3 PWM4 PWM5 RS RS8 RS7 RS5 RS4 Figue 3. Final Schematic f Half-Bidge LLC Resnant Cnvete f Multi Channel 0 Faichild Semicnduct Catin Rev..0. /6/ 5

16 AN-979 Exeimental eificatin T shw the validity f the design cedue esented in this alicatin nte, the cnvete f the design examle was built and tested. All the cicuit cmnents ae used as designed in the design examle. CR [00/div] 300 Figue 3 and Figue 33 shw the eatin wavefms at full-lad and n-lad cnditins f nal inut vltage. As bseved, the MOSFET dain-t-suce vltage ( DS ds t ze by esnance befe the MOSFET is tuned n and ze vltage switching is achieved. Figue 34 shws the wavefms f the esnant caacit vltage and imay-side cuent at full-lad cnditin. The eak values f the esnant caacit vltage and imay-side cuent ae 300 and.a, esectively, which ae well matched with the calculated values in STEP-8 f design cedue sectin. DS [00/div] I P [A/div] Time (5µs/div Figue 34. Resnant Caacit ltage and Pimay- Side Cuent Wavefms at Full-Lad Cnditin I P [A/div].A Figue 35 shws the ectifie dide vltage and cuent wavefms at full-lad cnditin. Due t the vltage vesht caused by stay inductance, the vltage stess is a little bit highe than the value calculated in STEP-9. Figue 36 shws the utut lad cuent and utut vltage f -am wavefms f cnstant-cuent cntl when utut lad is ste changed fm 40mA t 000mA at t 0. I D [A/div] 57 Figue 37 shws the eatin wavefm when LED sting is ened and ested cnditin I P [A/div] D [00/div] Time (5µs/div Figue 35. Rectifie Dide ltage and Cuent Wavefms at Full-Lad Cnditin I DS [A/div] OP_CC [/div] DS [00/div] 000mA 40mA Tansient Mde CC Mde Figue 3. Oeatin Wavefms at Full-Lad Cnditin I P [A/div] Time (5µs/div I LOAD [0.5A/div] t 0 t Time (50ms/div Figue 36. Sft-Stat Wavefms LED [00/div] Oen LED Reste LED I DS [A/div] I LED_OPEN [00mA/div] DS [00/div] DS_NORMAL_LED [500m/div] DSD_OPEN_LED [500m/div] Time (5µs/div Figue 33. Oeatin Wavefms at N-Lad Cnditin Figue 37. Oen LED Ptectin Oeatin 0 Faichild Semicnduct Catin Rev..0. /6/ 6

17 AN-979 Refeences [] Rbet L. Steigewald, A Cmaisn f Half-bidge esnant cnvete tlgies, IEEE Tansactins n Pwe Electnics, l. 3, N., Ail 988. [] A. F. Witulski and R. W. Eicksn, Design f the seies esnant cnvete f imum stess, IEEE Tansactins n Aes. Electn. Syst., l. AES-, , July 986. [3] R. Ouganti, J. Yang, and F.C. Lee, Imlementatin f Otimal Tajecty Cntl f Seies Resnant Cnvetes, Pc. IEEE PESC 87, 987. [4]. eian and S. Cuk, A Cmlete DC Analysis f the Seies Resnant Cnvete, Pc. IEEE PESC 8, 98. [5] Y. G. Kang, A. K. Uadhyay, D. L. Stehens, Analysis and design f a half-bidge aallel esnant cnvete eating abve esnance, IEEE Tansactins n Industy Alicatins, l. 7, Mach-Ail 99, [6] R. Ouganti, J. Yang, and F.C. Lee, State Plane Analysis f Paallel Resnant Cnvetes, Pc. IEEE PESC 85, 985. [7] M. Emsemann, An Aximate Steady State and Small Signal Analysis f the Paallel Resnant Cnvete Running Abve Resnance, Pc. Pwe Electnics and aiable Seed Dives 9, 99, [8] Yan Liang, Wendu Liu, Bing Lu, van Wyk, J.D, Design f integated assive cmnent f a MHz kw halfbidge LLC esnant cnvete, IAS 005, [9] B. Yang, F.C. Lee, M. Cncannn, Ove-cuent tectin methds f LLC esnant cnvete APEC 003, [0] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhag Qian, Guisng Huang, Thee-level LLC seies esnant DC/DC cnvete, IEEE Tansactins n Pwe Electnics l.0, July 005, [] B Yang, Lee, F.C, A.J Zhang, Guisng Huang, LLC esnant cnvete f fnt-end DC/DC cnvesin, APEC [] Bing Lu, Wendu Liu, Yan Liang, Fed C. Lee, Jacbus D. an Wyk, Otimal design methdlgy f LLC Resnant Cnvete, APEC, 006, This alicatin nte based n Faichild Semicnduct Alicatin Nte AN-437. Related Datasheets FLS800XS Half-Bidge LLC Resnant Cntl IC f Lighting FAN Channel LED Cuent Balance Cntl IC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used heein:. Life sut devices systems ae devices systems which, (a ae intended f sugical imlant int the bdy, (b sut sustain life, (c whse failue t efm when ely used in accdance with instuctins f use vided in the labeling, can be easnably exected t esult in significant injuy t the use.. A citical cmnent is any cmnent f a life sut device system whse failue t efm can be easnably exected t cause the failue f the life sut device system, t affect its safety effectiveness. 0 Faichild Semicnduct Catin Rev..0. /6/ 7