Half-Bridge LLC Resonant Converter Design Using FSFR-Series Fairchild Power Switch (FPS ) R o V O

Transcription

1 AN45 HalfBidge LLC esnant Cnvete Design Using FSFSeies Faichild Pwe Switch (FPS Intductin The efft t btain eveinceasing we density f switchedmde we suly has been limited by the size f assive cmnents. Oeatin at highe fequencies cnsideably educes the size f assive cmnents, such as tansfmes and filtes; hweve, switching lsses have been an bstacle t highfequency eatin. T educe switching lsses and allw highfequency eatin, esnant switching techniques have been develed. These techniques cess we in a sinusidal manne and the switching devices ae sftly cmmutated. Theefe, the switching lsses and nise can be damatically educed [7]. Amng vaius kinds f esnant cnvetes, the simlest and mst ula esnant cnvete is the LC seies esnant cnvete, whee the ectifielad netwk is laced in seies with the LC esnant netwk, as deicted in Figue [4]. In this cnfiguatin, the esnant netwk and the lad act as a vltage divide. By changing the fequency f diving vltage d, the imedance f the esnant netwk changes. The inut vltage is slit between this imedance and the eflected lad. Since it is a vltage divide, the DC gain f a LC seies esnant cnvete is always <. At lightlad cnditin, the imedance f the lad is vey lage cmaed t the imedance f the esnant netwk; all the inut vltage is imsed n the lad. This makes it difficult t egulate the utut at light lad. Theetically, fequency shuld be infinite t egulate the utut at n lad. in Q Q d L C n: Figue. HalfBidge LC Seies esnant Cnvete T vecme the limitatin f seies esnant cnvetes, LLC esnant cnvete has been sed [8]. LLC esnant cnvete is a mdified LC seies esnant cnvete imlemented by lacing a shunt induct acss the tansfme imay winding as deicted in Figue. When this tlgy was fist esented, it did nt eceive much attentin due t the cunteintuitive cncet that O inceasing the ciculating cuent in the imay side with a shunt induct can be beneficial t cicuit eatin. Hweve, it can be vey effective in imving efficiency f highinut vltage alicatin whee the switching lss is much me dant than the cnductin lss. In mst f the actical design, this shunt induct is ealized using the magnetizing inductance f the tansfme. The cicuit diagam f LLC esnant cnvete lks much the same as the LC seies esnant cnvete: The nly diffeence is the value f the magnetizing induct. While the seies esnant cnvete has a magnetizing inductance much lage than the LC seies esnant induct (L, the magnetizing inductance in LLC esnant cnvete is just 3~8 times L, which is usually imlemented by intducing an ai ga in the tansfme. in Q Q L L shunt ( L m C Figue. Halfbidge LLC esnant Cnvete An LLC esnant cnvete has many advantages ve a seies esnant cnvete; it can egulate the utut ve wide line and lad vaiatins with a elatively small vaiatin f switching fequency. It can achieve ze vltage switching (ZS ve the entie eating ange. All essential aasitic elements, including junctin caacitances f all semicnduct devices and the leakage inductance and magnetizing inductance f the tansfme, ae utilized t achieve sftswitching. This alicatin nte esents design cnsideatins f an LLC esnant halfbidge cnvete emlying FSFseies FPS. It includes exlanatin f LLC esnant cnvete eatin incile, designing the tansfme and esnant netwk, and selecting the cmnents. The stebyste design cedue exlained with a design examle hels design the LLC esnant cnvete.. LLC esnant Cnvete and Fundamental Aximatin n: O 007 Faichild Semicnduct Catin ev..0. 0//4

2 AN45 Figue 3 shws the simlified schematic f a halfbidge LLC esnant cnvete, whee L m is the magnetizing inductance that acts as a shunt induct, L is the seies esnant induct, and C is the esnant caacit. Figue 4 illustates the tyical wavefms f the LLC esnant cnvete. It is assumed that the eatin fequency is same as the esnance fequency, deteed by the esnance between L and C. Since the magnetizing induct is elatively small, thee exists cnsideable amunt f magnetizing cuent (I m, which feewheels in the imay side withut being invlved in the we tansfe. The imayside cuent (I is sum f the magnetizing cuent and the secndayside cuent efeed t the imay. In geneal, the LLC esnant tlgy cnsists f thee stages shwn in Figue 3; squae wave geneat, esnant netwk, and ectifie netwk. The squae wave geneat duces a squae wave vltage, d, by diving switches Q and Q altenately with 50% duty cycle f each switch. A small dead time is usually intduced between the cnsecutive tansitins. The squae wave geneat stage can be built as a fullbidge halfbidge tye. The esnant netwk cnsists f a caacit, leakage inductances, and the magnetizing inductance f the tansfme. The esnant netwk filtes the highe hamnic cuents. Essentially, nly sinusidal cuent is allwed t flw thugh the esnant netwk even thugh a squae wave vltage is alied t the esnant netwk. The cuent (I lags the vltage alied t the esnant netwk (that is, the fundamental cmnent f the squae wave vltage ( d alied t the halfbidge ttem le, which allws the MOSFETs t be tuned n with ze vltage. As shwn in Figue 4, the MOSFET tuns n while the vltage acss the MOSFET is ze by flwing cuent thugh the antiaallel dide. The ectifie netwk duces DC vltage by ectifying the AC cuent with ectifie dides and caacit. The ectifie netwk can be imlemented as a fullwave bidge centetaed cnfiguatin with caacitive utut filte. Squae wave geneat in Q Q I DS d esnant netwk C L I m L m I n: ectifie netwk Figue 3. Schematic f Halfbidge LLC esnant Cnvete I D I O I DS I D d gs gs I I m in Figue 4. Tyical Wavefms f Halfbidge LLC esnant Cnvete The filteing actin f the esnant netwk allws use f the fundamental aximatin t btain the vltage gain f the esnant cnvete, which assumes that nly the fundamental cmnent f the squaewave vltage inut t the esnant netwk cntibutes t the we tansfe t the utut. Because the ectifie cicuit in the secnday side acts as an imedance tansfme, the equivalent lad esistance is diffeent fm actual lad esistance. Figue 5 shws hw this equivalent lad esistance is deived. The imayside cicuit is elaced by a sinusidal cuent suce, I ac, and a squae wave f vltage, I, aeas at the inut t the ectifie. Since the aveage f I ac is the utut cuent, I, I ac, is btained as: I ac I sin( t ( and I is given as: if sin( t 0 I if sin( t 0 I whee is the utut vltage. The fundamental cmnent f I is given as: F 4 I sin( t (3 Since hamnic cmnents f I ae nt invlved in the we tansfe, AC equivalent lad esistance can be calculated by dividing F I by I ac as: F I 8 8 ac I ac I (4 Cnsideing the tansfme tuns ati (n=n /N s, the equivalent lad esistance shwn in the imay side is btained as: ac ( 8n (5 007 Faichild Semicnduct Catin ev..0. 0//4

3 Gain ( n / in AN45 By using the equivalent lad esistance, the AC equivalent cicuit is btained, as illustated in Figue 6, whee d F and O F ae the fundamental cmnents f the diving vltage, d and eflected utut vltage, O (n I, esectively. I ac I ac I F I k I ac I I O F 4 I I sin( wt I ac sin( wt Figue 5. Deivatin f Equivalent Lad esistance ac in d d F C C L L m 8n n=n /N s ac L L m N :N s I ac O F (n I F Figue 6. AC Equivalent Cicuit f LLC esnant Cnvete With the equivalent lad esistance btained in Equatin 5, the chaacteistics f the LLC esnant cnvete can be deived. Using the AC equivalent cicuit f Figue 6, the vltage gain, M, is btained as: 4n F F sin( t n n M F F 4 d d in sin( t in O I ( ( m ( j ( ( m Q (6 whee: 8n L L m L, ac, m L L Q,, C L C L C ac As can be seen in Equatin 6, thee ae tw esnant fequencies. One is deteed by L and C, while the the is deteed by L and C. Equatin 6 shws the gain is unity at esnant fequency (ω, egadless f the lad vaiatin, which is given as: n ( m M at (7 in The gain f Equatin 6 is ltted in Figue 7 f diffeent Q values with m=3, f =00kHz, and f =57kHz. As bseved in Figue 7, the LLC esnant cnvete shws gain chaacteistics that ae almst indeendent f the lad when the switching fequency is aund the esnant fequency, f. This is a distinct advantage f LLCtye esnant cnvete ve the cnventinal seies esnant cnvete. Theefe, it is natual t eate the cnvete aund the esnant fequency t imize the switching fequency vaiatin. The eating ange f the LLC esnant cnvete is limited by the eak gain (attainable imum gain, which is indicated with * in Figue 7. It shuld be nted that the eak vltage gain des nt ccu at f n f. The eak gain fequency whee the eak gain is btained exists between f and f, as shwn in Figue 7. As Q deceases (as lad deceases, the eak gain fequency mves t f and highe eak gain is btained. Meanwhile, as Q inceases (as lad inceases, the eak gain fequency mves t f and the eak gain ds; thus, the full lad cnditin shuld be the wst case f the esnant netwk design f LC Q=0.5 Q=.0 M f f feq (khz L Q L / C ac Q=.0 Q=0.75 Q=0.50 Q=0.5 Figue 7. Tyical Gain Cuves f LLC esnant Cnvete (m=3 007 Faichild Semicnduct Catin ev..0. 0//4 3

4 Gain ( n / in AN45. Cnsideatin f Integated Tansfme F actical design, it is cmmn t imlement the magnetic cmnents (seies induct and shunt induct using an integated tansfme; whee the leakage inductance is used as a seies induct, while the magnetizing induct is used as a shunt induct. When building the magnetizing cmnents in this way, the equivalent cicuit in Figue 6 shuld be mdified as shwn in Figue 8 because the leakage inductance exists, nt nly in the imay side, but als in the secnday side. Nt cnsideing the leakage inductance in the tansfme secnday side geneally esults in an incect design. n M whee: in O e ac ( ( m M ( j( ( ( m Q ( mm ( ( j( ( ( m Q 8n M L, m L e L Q,, e C L C L C ac e e (9 in in F d C C L L L n L L L lk L L L m lk m //( lks L L // L lk m lk L L L lk m n: : M L lks I L ( M L L O ideal tansfme F O ac (n F I Figue 8. Mdified Equivalent Cicuit t Accmmdate the Secndayside Leakage Inductance In Figue 8, the effective seies induct (L and shunt induct (L L ae btained by assug n L lks =L lk and efeing the secndayside leakage inductance t the imay side as: L L L m lk L L L n L L L L lk m //( lks lk m // lk (8 The gain at the esnant fequency (ω is fixed egadless f the lad vaiatin, which is given as: L m M M at L L m (0 The gain at the esnant fequency (ω is unity when using individual ce f seies induct, as shwn in Equatin 7. Hweve, when imlementing the magnetic cmnents with integated tansfme, the gain at the esnant fequency (ω is lage than unity due t the vitual gain caused by the leakage inductance in the tansfme secnday side. The gain f Equatin 9 is ltted in Figue 0 f diffeent Q e values with m=3, f =00kHz, and f =57kHz. As bseved in Figue 9, the LLC esnant cnvete shws gain chaacteistics almst indeendent f the lad when the switching fequency is aund the esnant fequency, f f LC Q e =0.5 f LC Q e L / C e ac Q e =.00 Q e =0.75 When handling an actual tansfme, equivalent cicuit with L and L is efeed since these values can be easily measued with a given tansfme. In an actual tansfme, L and L can be measued in the imay side with the secndayside winding en cicuited and sht cicuited, esectively. In Figue 9, ntice that a vitual gain M is intduced, which is caused by the secndayside leakage inductance. By adjusting the gain equatin f Equatin 6 using the mdified equivalent cicuit f Figue 9, the gain equatin f integated tansfme is btained: Q e =.0 f M feq (khz Q e =0.50 Q e =0.5 Figue 9. Tyical Gain Cuves f LLC esnant Cnvete (m=3 Using an Integated Tansfme 007 Faichild Semicnduct Catin ev..0. 0//4 4

5 AN45 3. Cnsideatin f Oeatin Mde and Attainable Maximum Gain Oeatin Mde The LLC esnant cnvete can eate at fequency belw abve the esnance fequency (f, as illustated in Figue 0. Figue shws the wavefms f the cuents in the tansfme imay side and secnday side f each eatin mde. Oeatin belw the esnant fequency (case I allws the sft cmmutatin f the ectifie dides in the secnday side, while the ciculating cuent is elatively lage. The ciculating cuent inceases me as the eatin fequency mves dwnwad fm the esnant fequency. Meanwhile, eatin abve the esnant fequency (case II allws the ciculating cuent t be imized, but the ectifie dides ae nt sftly cmmutated. Belw esnance eatin is efeed f high utut vltage alicatins, such as Plasma Dislay Panel (PDP T whee the evese ecvey lss in the ectifie dide is sevee. Belw esnance eatin als has a naw fequency ange with esect t the lad vaiatin since the fequency is limited belw the esnance fequency even at n lad cnditin. On the the hand, abve esnance eatin has less cnductin lss than the belw esnance eatin. It can shw bette efficiency f lw utut vltage alicatins, such as Liquid Cystal Dislay (LCD T lat adat, whee Schttky dides ae available f the secndayside ectifies and evese ecvey blems ae insignificant. Hweve, eatin at abve the esnant fequency may cause t much fequency incease at lightlad cnditin. Abve fequency eatin equies fequency skiing t event t much incease f the switching fequency. Gain (M B A Lad incease I I DS I D I I DS I D I m I m f f S (I f s < f I O (II f s > f Figue. Wavefms f Each Oeatin Mde equied Maximum Gain and Peak Gain Abve the eak gain fequency, the inut imedance f the esnant netwk is inductive and the inut cuent f the esnant netwk (I lags the vltage alied t the esnant netwk ( d. This emits the MOSFETs t tun n with ze vltage (ZS, as illustated in Figue. Meanwhile, the inut imedance f the esnant netwk becmes caacitive and I leads d belw the eak gain fequency. When eating in caacitive egin, the MOSFET bdy dide is evese ecveed duing the switching tansitin, which esults in sevee nise. Anthe blem f enteing int the caacitive egin is that the utut vltage becmes ut f cntl since the sle f the gain is evesed. The imum switching fequency shuld be well limited abve the eak gain fequency. M caacitive egin eak gain inductive egin I O I II f s Belw esnance (f s <f Abve esnance (f s >f d d f f s I I Figue 0. Oeatin Mdes Accding t the Oeatin Fequency I DS I DS evese ecvey ZS Figue. Oeatin Wavefms f Caacitive and Inductive egins 007 Faichild Semicnduct Catin ev..0. 0//4 5

6 eak gain AN45 The available inut vltage ange f the LLC esnant cnvete is deteed by the eak vltage gain. Thus, the esnant netwk shuld be designed s that the gain cuve has an enugh eak gain t cve the inut vltage ange. Hweve, ZS cnditin is lst belw the eak gain int, as deicted in Figue. Theefe, sme magin is equied when deteing the imum gain t guaantee stable ZS eatin duing the lad tansient and statu. Tyically 0~0% f the imum gain is used as a magin f actical design, as shwn in Figue Gain (M 0~0% f M eak gain imum eatin gain (M m=3.0 m=3.5 m=4.0 m=4.5 m=5.0 m=6.0 m=9.0 m=8.0 m=7.0 m=.5 m=.5 f Figue 3. Deteing the Maximum Gain f s Figue 4. Peak Gain (Attainable Maximum Gain vs. Q f Diffeent m alues Q Even thugh the eak gain at a given cnditin can be btained by using the gain in Equatin 6, it is difficult t exess the eak gain in exlicit fm. T simlify the analysis and design, the eak gains ae btained using simulatin tls and deicted in Figue 4, which shws hw the eak gain (attainable imum gain vaies with Q f diffeent m values. It aeas that highe eak gain can be btained by educing m Q values. With a given esnant fequency (f and Q value, deceasing m means educing the magnetizing inductance, which esults in inceased ciculating cuent. Accdingly, thee is a tadeff between the available gain ange and cnductin lss. 007 Faichild Semicnduct Catin ev..0. 0//4 6

7 AN45 4. Featues f FSFSeies FSFseies is an integated Pulse Fequency Mdulatin (PFM cntlle and MOSFETs secifically designed f Ze ltage Switching (ZS halfbidge cnvetes with imal extenal cmnents. The intenal cntlle includes an undevltage lckut, timized highside / lwside gate dive, temeatuecmensated ecise cuent cntlled scillat, and selftectin cicuity. Cmaed with discete MOSFET and PWM cntlle slutin, FSFseies can educe ttal cst, cmnent cunt, size and weight, while simultaneusly inceasing efficiency, ductivity, and system eliability DL TCS SG Lcc CON PG Hcc Figue 5. Package Diagam CT Table. DL CON 3 T 4 CS Pin Descitin This in is the dain f the highside MOSFET, tyically cnnected t the inut DC link vltage. This in is f enable/disable and tectin. When the vltage f this in is abve 0.6, the IC eatin is enabled. Meanwhile, when the vltage f this in ds belw 0.4, gate dive signals f bth MOSFETs ae disabled. When the vltage f this in inceases abve 5, tectin is tiggeed. This in is t gam the switching fequency. Tyically, tcule and esist ae cnnected t this in t egulate the utut vltage. This in is t sense the cuent flwing thugh the lwside MOSFET. Tyically negative vltage is alied n this in. 5 SG This in is the cntl gund. 6 PG 7 Lcc This in is the we gund. This in is cnnected t the suce f the lwside MOSFET. This in is the suly vltage f the cntl IC. 8 NC N cnnectin. 9 Hcc 0 CT This in is the suly vltage f the highside dive cicuit. This in is the dain f the lwside MOSFET. Tyically tansfme is cnnected t this in. Lcc 7 DL EF I CTC I CTC I CTC 3 S Q Q F/F.3 / 4.5 Lcc gd Intenal Bias ef Hcc gd 8.7 / 9. 9 Hcc T CON 3 Lcc I delay 0.6/0.4 Cunte (/4 Time Delay 350ns Time Delay 350ns LevelShift Balancing delay HighSide Gate Dive LwSide Gate Dive 0 CT 5 OLP Lcc OP 3 Lcc gd S Q Q Autestat tectin Q Q S Latch tectin Shutdwn withut delay 50ns delay TSD Lcc < AOCP 8 NC 6 PG delay.5s OCP SG Figue 6. Functinal Blck Diagam f FSFseies 4 CS 007 Faichild Semicnduct Catin ev..0. 0//4 7

8 AN45 C L lks D in (Fm PFC utut C DL cc C Lcc SS C B C SS T CON CS Lcc dam Cntl IC D bt DL Hcc C Hcc CT L lk Lm N Integated tansfme Ns Ns L lks D bias KA43 C d C F F C LPF SG PG LPF sense Figue 7. efeence Cicuit f Design Examle f LLC esnant Halfbidge Cnvete 5. Design Pcedue In this sectin, a design cedue is esented using the schematic in Figue 7 as a efeence. An integated tansfme with cente ta, secnday side is used and inut is sulied fm we fact cectin (PFC eegulat. A DC/DC cnvete with 9W/4 utut has been selected as a design examle. The design secificatins ae as fllws: Nal inut vltage: 400DC (utut f PFC stage Outut: 4/8A (9W Hldu time equiement: 0ms (50Hz line feq. DC link caacit f PFC utut: 0µF [STEP] Define the system secificatins As a fist ste, define the fllwing secificatin. Estimated efficiency (E ff : The we cnvesin efficiency must be estimated t calculate the imum inut we with a given imum utut we. If n efeence data is available, use E ff = 0.88~0.9 f lwvltage utut alicatins and E ff = 0.9~0.96 f highvltage utut alicatins. With the estimated efficiency, the imum inut we is given as: P P ( in E ff Inut vltage ange ( in and in : The imum inut vltage wuld be the nal PFC utut vltage as: in ( O. PFC Even thugh the inut vltage is egulated as cnstant by PFC eegulat, it ds duing the hldu time. The imum inut vltage cnsideing the hldu time equiement is given as: in O. PFC PT in HU (3 C whee O.PFC is the nal PFC utut vltage, T HU is a hldu time, and C DL is the DC link bulk caacit. (Design Examle Assug the efficiency is 9%, P 9 P 09W in E 0.9 ff in O. PFC 400 in O. PFC PT in C DL HU DL [STEP] Detee the Maximum and Minimum ltage Gains f the esnant Netwk As discussed in the evius sectin, it is tyical t eate the LLC esnant cnvete aund the esnant fequency (f t imize switching fequency vaiatin. Since the inut f the LLC esnant cnvete is sulied fm PFC utut vltage, the cnvete shuld be designed t eate at f f the nal PFC utut vltage. As bseved in Equatin 0, the gain at f is a functin f m (m=l /L. The gain at f is deteed by chsing that value f m. While a highe eak gain can be btained with a small m value, t small m value esults in culing f the tansfme and deteiates the efficiency. It is tyical t set m t be 3~7, which esults in a vltage gain f.~. at the esnant fequency (f. 007 Faichild Semicnduct Catin ev..0. 0//4 8

9 eak gain AN45 With the chsen m value, the vltage gain f the nal PFC utut vltage is btained as: M m (4 which wuld be the imum gain because the nal PFC utut vltage is the imum inut vltage ( in. The imum vltage gain is given as: M in M (5 in (Design Examle The ati (m between L and L is chsen as 5. The imum and imum gains ae btained as: M M m 5. m 5 O in in M in 349 M M Gain (M M Peak gain (available imum gain.8 m. m f. f in f in ( O.PFC Figue 8. Maximum Gain / Minimum Gain [STEP3] Detee the Tansfme Tuns ati (n=n /N s With the imum gain (M btained in STEP, the tansfme tuns ati is given as: N in n M N ( s F whee F is the secndayside ectifie dide vltage d. (Design Examle assug F is 0.9, N in 400 n M N ( (4 0.9 s F f s (6 [STEP4] Calculate the Equivalent Lad esistance With the tansfme tuns ati btained fm Equatin 6, the equivalent lad esistance is btained as: 8n ac P (7 (Design Examle 8n ac 97 P 9 [STEP5] Design the esnant Netwk With m value chsen in STEP, ead e Q value fm the eak gain cuves in Figue 4 that allws enugh eak gain. Cnsideing the lad tansient and stable zevltageswitching (ZS eatin, 0~0% magin shuld be intduced n the imum gain when deteing the eak gain. Once the Q value is deteed, the esnant aametes ae btained as: C (8 Q f ac L ( f C (9 L m L (0 (Design Examle As calculated in STEP, the imum vltage gain (M f the imum inut vltage ( in is.8. With 5% magin, a eak gain f.47 is equied. m has been chsen as 5 in STEP and Q is btained as 0.4 fm the eak gain cuves in Figue 9. By selecting the esnant fequency as 00kHz, the esnant cmnents ae deteed as: C 0.nF 3 Q f ac L 6H 3 9 ( f C ( L m L 630H m=4.0 m=4.5 m=5.0 m=6.0 m=9.0 m=8.0 m=7.0 Q Figue 9. esnant Netwk Design Using the Peak Gain (Attainable Maximum Gain Cuve f m=5 007 Faichild Semicnduct Catin ev..0. 0//4 9

10 AN45 [STEP6] Design the Tansfme The wst case f the tansfme design is the imum switching fequency cnditin, which ccus at the imum inut vltage and fulllad cnditin. T btain the imum switching fequency, lt the gain cuve using gain Equatin 9 and ead the imum switching fequency. The imum numbe f tuns f the tansfme imayside is btained as: N n( f M B A F s e ( whee A e is the csssectinal aea f the tansfme ce in m and B is the imum flux density swing in Tesla, as shwn in Figue 0. If thee is n efeence data, use B =0.3~0.4 T. Ntice that a vitual gain M is intduced, which is caused by the secndayside leakage inductance (efe t Figue % lad 80% lad f s f nmal 60% lad s 40% lad 0% lad M M feq (khz Figue. Gain Cuve I B /(f s n ( F /M n ( F /M B Figue 0. Flux Density Swing Chse the e numbe f tuns f the secnday side that esults in imayside tuns lage than N as: N n Ns N ( [STEP7] Tansfme Cnstuctin Paametes L and L f the tansfme wee deteed in STEP5. L and L can be measued in the imay side with the secndayside winding en cicuited and sht cicuited, esectively. Since LLC cnvete design equies a elatively lage L, a sectinal bbbin is tyically used, as shwn in Figue, t btain the desied L value. F a sectinal bbbin, the numbe f tuns and winding cnfiguatin ae the maj facts deteing the value f L, while the ga length f the ce des nt affect L much. L can be easily cntlled by adjusting the ga length. Table shws measued L and L values with diffeent ga lengths. A ga length f 0.0mm btains values f L and L clsest t the designed aametes. N N s N s (Design Examle EE354 ce (A e =07mm is selected f the tansfme. Fm the gain cuve f Figue, the imum switching fequency is btained as 78kHz. The imum imayside tuns f the tansfme is given as n( F N f B. A s e tuns Chse N s s that the esultant N shuld be lage than N : N n N N s N n N N s N n N N s N n N N s Figue. Sectinal Bbbin Table. Measued L and L with Diffeent Ga Lengths Ga length L L 0.0mm,95μH 3μH 0.05mm 943μH μh 0.0mm 630μH 8μH 0.5mm 488μH 7μH 0.0mm 49μH 5μH 0.5mm 366μH 4μH 007 Faichild Semicnduct Catin ev..0. 0//4 0

11 AN45 (Design Examle Final esnant Netwk Design Even thugh the integated tansfme aach in LLC esnant cnvete design can imlement the magnetic cmnents in a single ce and save ne magnetic cmnent, the value f L is nt easy t cntl in eal tansfme design. esnant netwk design smetimes equies iteatin with a esultant L value afte the tansfme is built. The esnant caacit value is als changed since it shuld be selected amng fftheshelf caacits. The final esnant netwk design is summaized in Table 3 and the new gain cuves ae shwn in Figue 3. Table 3. Final esnant Netwk Design Paametes Paametes Initial design Final design L 630µH 630µH L 6H 8µH C 0nF nf f 00kHz 99kHz m Q M@f.. Minimum feq 78kHz 7kHz f feq (khz f nmal M M 00% lad 80% lad 60% lad 40% lad 0% lad Figue 3. Gain Cuve f the Final esnant Netwk Design [STEP8] Select the esnant Caacit When chsing the esnant caacit, the cuent ating shuld be cnsideed because a cnsideable amunt f cuent flws thugh the caacit. The MS cuent thugh the esnant caacit is given as: I I n( [ ] [ ] (3 MS F C E ff n 4 fm ( L L The nal vltage f the esnant caacit in nmal eatin is given as: MS nm in C C f C I (4 Hweve, the esnant caacit vltage inceases much highe than this at velad cnditin lad tansient. Actual caacit selectin shuld be based n the Ove Cuent Ptectin (OCP ti int. With the OCP level, I OCP, the imum esnant caacit vltage is btained as: C in I C (5 OCP fs The imum switching fequency is used in the equatin because the fequency is tyically fced t the imum value by the feedback l when utut is veladed. (Design Examle I I n( [ ] [ ] MS F C E ff n 4 fm ( L L (4 0.9 [ ] [ ] A 3 6 The eak cuent in the imay side in nmal eatin is: eak ms I I.86A C C OCP level is set t 3.0A with 50% magin n I C eak : I MS nm in C C f C C in IOCP f C S ated lwes film caacit is selected f the esnant caacit. [STEP9] ectifie Netwk Design When the cente ta winding is used in the tansfme secnday side, the dide vltage stess is twice the utut vltage exessed as: ( (6 D F The MS value f the cuent flwing thugh each ectifie dide is given as: I MS D I ( Faichild Semicnduct Catin ev..0. 0//4

12 AN45 Meanwhile, the ile cuent flwing thugh utut caacit is given as: Lcc DL MS I 8 C ( I I I (8 8 The vltage ile f the utut caacit is: I (9 C whee C is the effective seies esistance (ES f the utut caacit and the we dissiatin is the utut caacit is: MS PLss. C ( IC (30 C (Design Examle The vltage stess and cuent stess f the ectifie dide ae: ( ( D F MS ID I 6.8A 4 The 00/0A Schttky dide is selected f the ectifie cnsideing the vltage vesht caused by the stay inductance. The MS cuent f the utut caacit is: MS I 8 C I ( I I A 8 When tw electlytic caacits with ES f 80mΩ ae used in aallel, the utut vltage ile is given as: 0.08 I C 8 ( 0.50 The lss in electlytic caacits is: MS PLss. C ( IC C W Extenal S/S SS C SS T Cntl IC SG PG Figue 4. Tyical Cicuit Cnfiguatin f T Pin Sftstat: T event excessive inush cuent and vesht f utut vltage duing statu, incease the vltage gain f the esnant cnvete gessively. Since the vltage gain f the esnant cnvete is evesely tinal t the switching fequency, the sftstat is imlemented by sweeing dwn the switching fequency fm an initial high fequency (f ISS until the utut vltage is established as illustated in Figue 5. The sftstat cicuit is made by cnnecting C seies netwk n the T in as shwn in Figue 4. FSFseies als has an intenal sftstat f 3ms t educe the cuent vesht duing the initial cycles, which adds 40kHz t the initial fequency f the extenal sftstat cicuit, as shwn in Figue 5. The actual initial fequency f the sftstat is given as: f ISS 5.k 5.k ( ( khz (33 It is tyical t set the initial fequency f sftstat (f ISS as ~3 times f the esnant fequency (f. The sftstat time is deteed by the C time cnstant: SS T 3 ~ 4 timesf C (34 SS SS SS f s [STEP0] Cntl Cicuit Cnfiguatin Figue 4 shws the tyical cicuit cnfiguatin f T in f FSFseies, whee the tcule tansist is cnnected t the T in t cntl the switching fequency. The imum switching fequency ccus when the tcule tansist is fully tuned ff, which is given as: 5.k f 00( khz (3 Assug the satuatin vltage f tcule tansist is 0., the imum switching fequency is deteed as: f 5.k 4.68k ( 00( khz (3 f ISS 3ms 40kHz 3~4 times f C time cnstant Cntl l take ve Figue 5. Fequency Swee f the Sftstat time 007 Faichild Semicnduct Catin ev..0. 0//4

13 AN45 (Design Examle The imum fequency is 7kHz in STEP6. is deteed as: 00kHz 5.k 7.k f Cnsideing the utut vltage vesht duing tansient (0% and the cntllability f the feedback l, the imum fequency is set as 40kHz. is deteed as: 4.68k f.40 5.k ( 00kHz 4.68k 7.k 99kHz.4 5.k ( 00kHz 7.k CS Figue 6. Halfwave Sensing CS Cntl IC SG I DS C PG sense I DS CS N Ns Ns Figue 7. Fullwave Sensing Setting the initial fequency f sftstat as 50kHz (.5 times f the esnant fequency, the sftstat esist SS is given as: SS 5.k fiss 40kHz 5.k ( 00kHz 5.k 3.8k 50kHz 40kHz 5.k ( 00kHz 7.k (Design Examle Since the OCP level is deteed as 3A in STEP8 and the OCP theshld vltage is 0.6, a sensing esist f 0.Ω is used. The C time cnstant is set t 00ns (/00 f switching eid with kω esist and 00F caacit. [STEP] Cuent Sensing and Ptectin FSFseies senses lwside MOSFET dain cuent as a negative vltage, as shwn in Figue 6 and Figue 7. Halfwave sensing allws lwwe dissiatin in the sensing esist, while fullwave sensing has less switching nise in the sensing signal. Tyically, C lwass filte is used t filte ut the switching nise in the sensing signal. The C time cnstant f the lwass filte shuld be /00~/0 f the switching eid. C N Ns Ns Cntl IC CS CS I DS SG PG sense I DS CS 007 Faichild Semicnduct Catin ev..0. 0//4 3

14 AN45 Design Summay Figue 8 shws the final schematic f the LLC esnant halfbidge cnvete design examle. EE354 ce with sectinal bbbin is used f the tansfme. The efficiency at full lad cnditin is aund 94%. C0 nf/ 630 D FYP00DN C0 00μF/ 35 C0 00μF/ 35 in=400dc cc 04 7.k JP 0 C05 μf/ k C08 nf C07 6.8μF k T CON Lcc 06 7 Cntl IC D0 N4937 DL Hcc C06 50nF CT N Ns Ns D FYP00DN 0 k 0 0k 04 6k C04 nf 06 k C0 0μF/ 450 CS U3 KA43 C03 47nF 03 33k 0 kω C0 00F SG PG 05 7k 0 0.Ω Figue 8. Final Schematic f Halfbidge LLC esnant Cnvete Ce: EE354 (Ae=07 mm Bbbin: EE354 (Hizntal/sectin tye EE354 6 N N s N 3 N s N s N s 8 9 Figue 9. Tansfme Stuctue Pin(S F Wie Tuns Winding Methd N 8 0.φ 30 (Litz wie 36 Sectin winding N s φ 00 (Litz wie 4 Sectin winding N s 9 0.φ 00 (Litz wie 4 Sectin winding Pin Secificatin emak Pimayside Inductance (L 8 630H ± 5% Secnday windings en 00kHz, Equivalent Leakage Inductance (L 8 8H Max. Sht ne f the secnday windings 00kHz, 007 Faichild Semicnduct Catin ev..0. 0//4 4

15 AN45 6. Exeimental eificatin T shw the validity f the design cedue esented in this alicatin nte, the cnvete f the design examle has been built and tested. All the cicuit cmnents ae used as designed in the design examle. Figue 30 and Figue 3 shw the eatin wavefms at fulllad and nlad cnditins f nal inut vltage. As bseved, the MOSFET daintsuce vltage ( DS ds t ze by esnance befe the MOSFET is tuned n and ze vltage switching is achieved. Figue 3 shws the wavefms f the esnant caacit vltage and imayside cuent at full lad cnditin. The eak values f the esnant caacit vltage and imayside cuent ae 35 and.93a, esectively, which ae well matched with the calculated values in STEP8 f design cedue sectin. Figue 33 shws the wavefms f the esnant caacit vltage and imayside cuent at utut sht cnditin. F utut sht cnditin, ve cuent tectin (OCP is tiggeed when the imayside cuent exceeds 3A. The imum vltage f the esnant caacit is a little bit highe than the calculated value f 49 because the OCP tis at a level little bit highe than 3A, due t the shutdwn delay time f.5µs (efe t the FSF00 datasheet. Figue 34 shws the ectifie dide vltage and cuent wavefms at fulllad and nlad cnditins. Due t the vltage vesht caused by stay inductance, the vltage stess is a little bit highe than the value calculated in STEP9. Figue 35 shws the utut vltage ile at fulllad and nlad cnditins. The utut vltage ile is well matched with the designed value in STEP9. Figue 36 shws the measued efficiency f diffeent lad cnditins. Efficiency at fulllad cnditin is abut 94%. Figue 3. Oeatin Wavefms at Nlad Cnditin Figue 3. esnant Caacit ltage and Pimayside Cuent Wavefms at Fulllad Cnditin Figue 33. esnant Caacit ltage and Pimayside Cuent Wavefms f Outut Sht Ptectin Figue 30. Oeatin Wavefms at Fulllad Cnditin Figue 34. ectifie Dide ltage and Cuent Wavefms at Fulllad Cnditin 007 Faichild Semicnduct Catin ev..0. 0//4 5

16 AN45 Figue 35. Outut ltage ile and PimaySide Cuent Wavefms at FullLad Cnditin Figue 37. Measued Efficiency Figue 36. Sftstat Wavefms 007 Faichild Semicnduct Catin ev..0. 0//4 6

17 AN45 7. efeences [] bet L. Steigewald, A Cmaisn f Halfbidge esnant cnvete tlgies, IEEE Tansactins n Pwe Electnics, l. 3, N., Ail 988. [] A. F. Witulski and. W. Eicksn, Design f the seies esnant cnvete f imum stess, IEEE Tansactins n Aes. Electn. Syst., l. AES, , July 986. [3]. Ouganti, J. Yang, and F.C. Lee, Imlementatin f Otimal Tajecty Cntl f Seies esnant Cnvetes, Pc. IEEE PESC 87, 987. [4]. eian and S. Cuk, A Cmlete DC Analysis f the Seies esnant Cnvete, Pc. IEEE PESC 8, 98. [5] Y. G. Kang, A. K. Uadhyay, D. L. Stehens, Analysis and design f a halfbidge aallel esnant cnvete eating abve esnance, IEEE Tansactins n Industy Alicatins l. 7, MachAil 99, [6]. Ouganti, J. Yang, and F.C. Lee, State Plane Analysis f Paallel esnant Cnvetes, Pc. IEEE PESC 85, 985. [7] M. Emsemann, An Aximate Steady State and Small Signal Analysis f the Paallel esnant Cnvete unning Abve esnance, Pc. Pwe Electnics and aiable Seed Dives 9, 99,. 94. [8] Yan Liang, Wendu Liu, Bing Lu, van Wyk, J.D, " Design f integated assive cmnent f a MHz kw halfbidge LLC esnant cnvete", IAS 005,. 38. [9] B. Yang, F.C. Lee, M. Cncannn, "Ove cuent tectin methds f LLC esnant cnvete" APEC 003, [0] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhag Qian, Guisng Huang, "Theelevel LLC seies esnant DC/DC cnvete" IEEE Tansactins n Pwe Electnics l.0, July 005, [] B Yang, Lee, F.C, A.J Zhang, Guisng Huang, "LLC esnant cnvete f fnt end DC/DC cnvesin" APEC [] Bing Lu, Wendu Liu, Yan Liang, Fed C. Lee, Jacbus D. an Wyk, Otimal design methdlgy f LLC esnant Cnvete, APEC Auth Hangsek Chi, Ph. D Stategic &D / Faichild Semicnduct [email protected] elated Pduct Infmatin FSF00 f 450W Faichild Pwe Switch (FPS f HalfBidge esnant Cnvetes Imtant Ntice DISCLAIME FAICHILD SEMICONDUCTO ESEES THE IGHT TO MAKE CHANGES WITHOUT FUTHE NOTICE TO ANY PODUCTS HEEIN TO IMPOE ELIABILITY, FUNCTION, O DESIGN. FAICHILD DOES NOT ASSUME ANY LIABILITY AISING OUT OF THE APPLICATION O USE OF ANY PODUCT O CICUIT DESCIBED HEEIN; NEITHE DOES IT CONEY ANY LICENSE UNDE ITS PATENT IGHTS, NO THE IGHTS OF OTHES. LIFE SUPPOT POLICY FAICHILD S PODUCTS AE NOT AUTHOIZED FO USE AS CITICAL COMPONENTS IN LIFE SUPPOT DEICES O SYSTEMS WITHOUT THE EXPESS WITTEN APPOAL OF THE PESIDENT OF FAICHILD SEMICONDUCTO COPOATION. As used heein:. Life sut devices systems ae devices systems which, (a ae intended f sugical imlant int the bdy, (b sut sustain life, (c whse failue t efm when ely used in accdance with instuctins f use vided in the labeling, can be easnably exected t esult in significant injuy t the use.. A citical cmnent is any cmnent f a life sut device system whse failue t efm can be easnably exected t cause the failue f the life sut device system, t affect its safety effectiveness. 007 Faichild Semicnduct Catin ev..0. 0//4 7

18 AN Faichild Semicnduct Catin ev..0. 0//4 8