MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A. Single Supply 3.0 V to 44 V Operational Amplifiers

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1 MC347,2,4,A MC337,2,4,A, NCV3372,4,A Single Supply 3. V to 44 V Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC337/72/74, MC347/72/74, NCV3372/74A series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 3 V/ s slew rate and fast settling time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (V EE ). With a Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC337/72/74, MC347/72/74, NCV3372/74,A series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC, QFN and TSSOP surface mount packages. Features Wide Bandwidth: 4.5 MHz High Slew ate: 3 V/ s Fast Settling Time:. s to.% Wide Single Supply Operation: 3. V to 44 V Wide Input Common Mode Voltage ange: Includes Ground (V EE) Low Input Offset Voltage: 3. mv Maximum (A Suffix) Large Output Voltage Swing: 4.7 V to 4 V (with ±5 V Supplies) Large Capacitance Drive Capability: pf to, pf Low Total Harmonic Distortion:.2% Excellent Phase Margin: 6 Excellent Gain Margin: 2 db Output Short Circuit Protection ESD Diodes/Clamps Provide Input Protection for Dual and Quad NCV Prefix for Automotive and Other Applications equiring Unique Site and Control Change equirements; AECQ Qualified and PPAP Capable These Devices are PbFree, Halogen Free/BF Free and are ohs Compliant PDIP P SUFFIX CASE 626 SOIC D SUFFIX CASE 75 WQFN MT SUFFIX CASE 5AJ PDIP4 P SUFFIX CASE 646 SOIC4 D SUFFIX CASE 75A TSSOP4 DTB SUFFIX CASE 94G ODEING INFOMATION See detailed ordering and shipping information on page of this data sheet. DEVICE MAKING INFOMATION See general marking information in the device marking section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 24 July, 24 ev. 22 Publication Order Number: MC347/D

2 MC347,2,4,A MC337,2,4,A, NCV3372,4,A CASE 626/CASE 75 PIN CONNECTIONS CASE 646/CASE 75A/CASE 94G CASE 5AJ Offset Null NC Output Inputs Output Inputs V EE 4 5 Offset Null (Single, Top View) Inputs 2 Output 2 7 Output 2 Output 2 Inputs 3 6 Inputs 2 V EE (Quad, Top View) Output 4 Inputs 4 V EE Inputs 3 Output 3 VCC Output 9 Output 2 NC 2 NC In 3 7 In 2 In 4 6 In 2 5 VEE/GND (Top View) (Dual, Top View) Q Q3 Q4 Q5 Q6 Q7 Bias Q2 Q Q9 C Q Q D2 Q7 6 7 Q Output Inputs C2 D3 Q9 Base Current Cancellation Q2 D Q3 Q4 Q5 5 Q6 Current Limit 3 4 Offset Null (MC337, MC347 only) Figure. epresentative Schematic Diagram (Each Amplifier) V EE /GND 2

3 MC347,2,4,A MC337,2,4,A, NCV3372,4,A MAXIMUM ATINGS ating Symbol Value Unit Supply Voltage (from V EE to ) V S 44 V Input Differential Voltage ange V ID (Note ) V Input Voltage ange V I (Note ) V Output Short Circuit Duration (Note 2) t SC Indefinite Sec Operating Junction Temperature T J 5 C Storage Temperature ange T stg 6 to 5 C ESD Capability, Dual and Quad (Note 3) V Human Body Model Machine Model ESD HBM ESD MM 2 2 Stresses exceeding those listed in the Maximum atings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Either or both input voltages should not exceed the magnitude of or V EE. 2. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded (see Figure 2). 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ2 (JEDEC standard: JESD22A4) ESD Machine Model tested per AECQ3 (JEDEC standard: JESD22A5) 3

4 MC347,2,4,A MC337,2,4,A, NCV3372,4,A ELECTICAL CHAACTEISTICS ( = 5 V, V EE = 5 V, L = connected to ground, unless otherwise noted. See Note 4 for T A = T low to T high ) A Suffix NonSuffix Characteristics Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage ( S =, V CM = V, = V) = 5 V, V EE = 5 V, = 5. V, V EE = V, = 5 V, V EE = 5 V, T A = T low to T high V IO mv Average Temperature Coefficient of Input Offset Voltage S =, V CM = V, = V, T A = T low to T high V IO / T V/ C Input Bias Current (V CM = V, = V) T A = T low to T high I IB na Input Offset Current (V CM = V, = V) T A = T low to T high I IO na Input Common Mode Voltage ange T A = T low to T high V IC V EE to (.) V EE to ( 2.2) V EE to (.) V EE to ( 2.2) V Large Signal Voltage Gain ( = ± V, L = 2. k ) T A = T low to T high A VOL V/mV Output Voltage Swing (V ID = ±. V) = 5. V, V EE = V, L = 2. k, = 5 V, V EE = 5 V, L = k, = 5 V, V EE = 5 V, L = 2. k, T A = T low to T high H V = 5. V, V EE = V, L = 2. k, = 5 V, V EE = 5 V, L = k, = 5 V, V EE = 5 V, L = 2. k, T A = T low to T high L V Output Short Circuit Current (V ID =. V, = V, ) Source Sink I SC ma Common Mode ejection S k, V CM = V IC, Power Supply ejection ( S = ) /V EE = 6.5 V/6.5 V to 3.5 V/3.5 V, CM db PS db Power Supply Current (Per Amplifier, No Load) = 5. V, V EE = V, = 2.5 V, = 5 V, V EE = 5 V, = V, = 5 V, V EE = 5 V, = V, T A = T low to T high I D ma Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. T low = 4 C for MC337,2,4,/A, NCV3374/A T high = 5 C for MC337,2,4,/A, NCV3374/A = C for MC347,2,4,/A = 7 C for MC347,2,4,/A = 4 C for MC3472,4/V, NCV3372,4A = 25 C for MC3472,4/V, NCV3372,4A, NCV3474V Case 5AJ T low /T high guaranteed by product characterization. 4

5 MC347,2,4,A MC337,2,4,A, NCV3372,4,A AC ELECTICAL CHAACTEISTICS ( = 5 V, V EE = 5 V, L = connected to ground., unless otherwise noted.) A Suffix NonSuffix Characteristics Symbol Min Typ Max Min Typ Max Unit Slew ate ( = V to V, L = 2. k, C L = 5 pf) A V =. A V =. Setting Time ( V Step, A V =.) To.% (/2 LSB of 9Bits) To.% (/2 LSB of 2Bits) S Gain Bandwidth Product (f = khz) GBW MHz Power Bandwidth A V =., L = 2. k, = 2 V pp, THD = 5.% t s V/ s BW 6 6 khz s Phase margin L = 2. k L = 2. k, C L = 3 pf Gain Margin L = 2. k L = 2. k, C L = 3 pf Equivalent Input Noise Voltage S =, f =. khz Equivalent Input Noise Current f =. khz Differential Input esistance V CM = V Differential Input Capacitance V CM = V Total Harmonic Distortion A V =, L = 2. k, 2. V pp 2 V pp, f = khz f m A m Deg e n nv/ Hz i n pa/ Hz in 5 5 M C in pf THD.2.2 % db Channel Separation (f = khz) 2 2 db Open Loop Output Impedance (f =. MHz) Z O 3 3 W Single Supply Split Supplies 3. V to 44 V V EE 44 V k 4 V EE 4 V EE V EE V EE Offset nulling range is approximately ± mv with a k potentiometer (MC337, MC347 only). Figure 2. Power Supply Configurations Figure 3. Offset Null Circuit 5

6 MC347,2,4,A MC337,2,4,A, NCV3372,4,A P, D MAXIMUM POWE DISSIPATION (mw) SOIC4 Pkg & 4 Pin Plastic Pkg SOIC Pkg T A, AMBIENT TEMPEATUE ( C) Figure 4. Maximum Power Dissipation versus Temperature for Package Types V, V IO INPUT OFFSET VOLTAGE (mv) T A, AMBIENT TEMPEATUE ( C) = 5 V V EE = 5 V V CM = Figure 5. Input Offset Voltage versus Temperature for epresentative Units /V EE =.5 V/.5 V to 22 V/ 22 V V EE. V EE V EE T A, AMBIENT TEMPEATUE ( C) V, IC INPUT COMMON MODE VOLTAGE ANGE (V) I, IB INPUT BIAS CUENT (NOMALIZED) T A, AMBIENT TEMPEATUE ( C) = 5 V V EE = 5 V V CM = Figure 6. Input Common Mode Voltage ange versus Temperature Figure 7. Normalized Input Bias Current versus Temperature I, IB INPUT BIAS CUENT (NOMALIZED) = 5 V V EE = 5 V V IC, INPUT COMMON MODE VOLTAGE (V) VO, OUTPUT VOLTAGE SWING (Vpp) L Connected to Ground L = k L = 2. k , V EE, SUPPLY VOLTAGE (V) Figure. Normalized Input Bias Current versus Input Common Mode Voltage Figure 9. Split Supply Output Voltage Swing versus Supply Voltage 6

7 MC347,2,4,A MC337,2,4,A, NCV3372,4,A V sat, OUTPUT SATUATION VOLTAGE (V). 2. V EE 2. Source Sink /V EE = 4.5 V/ 4.5 V to 22 V/ 22 V V EE V EE I L, LOAD CUENT (± ma) V sat, OUTPUT SATUATION VOLTAGE (V) GND L, LOAD ESISTANCE TO GOUND ( ) = 5 V L = GND. k k k Figure. Split Supply Output Saturation versus Load Current Figure. Single Supply Output Saturation versus Load esistance to Ground V sat, OUTPUT SATUATION VOLTAGE (V) GND L, LOAD ESISTANCE TO ( ) = 5 V L to. k k k Figure 2. Single Supply Output Saturation versus Load esistance to I, SC OUTPUT CUENT (ma) Source Sink 2 = 5 V V EE = 5 V L. =. V T A, AMBIENT TEMPEATUE ( C) Figure 3. Output Short Circuit Current versus Temperature Z, O OUTPUT IMPEDANCE ( ) Ω = 5 V V EE = 5 V V CM = = I O = ±.5 ma A V = A V = A V = A V =.. k k. M M f, FEQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp) = 5 V V EE = 5 V A V =. L = 2. k THD.% 3. k k 3 k k 3 k. M 3. M f, FEQUENCY (Hz) Figure 4. Output Impedance versus Frequency Figure 5. Output Voltage Swing versus Frequency 7

8 MC347,2,4,A MC337,2,4,A, NCV3372,4,A THD, TOTAL HAMONIC DISTOTION (%).4 A V =.3 = 5 V V EE = 5 V.2 = 2. V pp L = 2. k A V =. A V = A V =.. k k k f, FEQUENCY (Hz) Figure 6. Total Harmonic Distortion versus Frequency THD, TOTAL HAMONIC DISTOTION (%) A V = A V = A V = A V = , OUTPUT VOLTAGE SWING (V pp ) = 5 V V EE = 5 V L = 2. k Figure 7. Total Harmonic Distortion versus Output Voltage Swing A, VOL OPEN LOOP VOLTAGE GAIN (db) = 5 V V EE = 5 V = V to V L = k f Hz T A, AMBIENT TEMPEATUE ( C) Figure. Open Loop Voltage Gain versus Temperature A, VOL OPEN LOOP VOLTAGE GAIN (db) Gain Phase 45 6 Phase Margin 9 4 = 6 = 5 V 35 V EE = 5 V 2 = V L = 2. k.. k k k. M M M f, FEQUENCY (Hz) Figure 9. Open Loop Voltage Gain and Phase versus Frequency φ, EXCESS PHASE (DEGEES) A, VOL OPEN LOOP VOLTAGE GAIN (db) Phase L = 2. k 2. Phase L = 2. k, C L = 3 pf 3. Gain L = 2. k 4. Gain L = 2. k, C L = 3 pf = 5 V V EE = 5 V = V Phase Margin = 6 f, FEQUENCY (MHz) 2 Gain Margin = 2 db Figure 2. Open Loop Voltage Gain and Phase versus Frequency φ, EXCESS PHASE (DEGEES) GBW, GAIN BANDWIDTH PODUCT (NOMALIED) T A, AMBIENT TEMPEATUE ( C) = 5 V V EE = 5 V L = 2. k Figure 2. Normalized Gain Bandwidth Product versus Temperature

9 MC347,2,4,A MC337,2,4,A, NCV3372,4,A 7 PECENT OVESHOOT = 5 V V EE = 5 V L = 2. k = V to V φ m, PHASE MAGIN (DEGEES) = 5 V V EE = 5 V A V =. L = 2. k to = V to V. k k C L, LOAD CAPACITANCE (pf) Figure 22. Percent Overshoot versus Load Capacitance. k k C L, LOAD CAPACITANCE (pf) Figure 23. Phase Margin versus Load Capacitance 4 A, m GAIN MAGIN (db) = 5 V V EE = 5 V A V =. L = 2. k to = V to V φ m, PHASE MAGIN (DEGEES) C L = pf C L = pf C L =, pf C L =, pf = 5 V V EE = 5 V A V =. L = 2. k to = V to V. k k C L, LOAD CAPACITANCE (pf) Figure 24. Gain Margin versus Load Capacitance T A, AMBIENT TEMPEATUE ( C) Figure 25. Phase Margin versus Temperature A, m GAIN MAGIN (db) = 5 V V EE = 5 V A V =. L = 2. k to = V to V C L =, pf C L = pf C L = pf C L =, pf T A, AMBIENT TEMPEATUE ( C) Figure 26. Gain Margin versus Temperature A, m GAIN MAGIN (db) Gain 4. 3 = 5 V V EE = 5 V 2. T = 2 2 Phase A V = = V.. k k k T, DIFFEENTIAL SOUCE ESISTANCE ( ) Figure 27. Phase Margin and Gain Margin versus Differential Source esistance φ m, PHASE MAGIN (DEGEES) 9

10 MC347,2,4,A MC337,2,4,A, NCV3372,4,A S, SLEW ATE (NOMALIZED) = 5 V V EE = 5 V A V =. L = 2. k C L = 5 pf T A, AMBIENT TEMPEATUE ( C) Figure 2. Normalized Slew ate versus Temperature V, O OUTPUT VOLTAGE SWING FOM V (V) Δ mv mv. mv. mv. mv. mv t s, SETTLING TIME ( s) Figure 29. Output Settling Time = 5 V V EE = 5 V A V =. Compensated Uncompensated 5 mv/div = 5 V V EE = 5 V A V =. L = 2. k C L = 3 pf 5. V/DIV = 5 V V EE = 5 V A V =. L = 2. k C L = 3 pf 2. s/div Figure 3. Small Signal Transient esponse. s/div Figure 3. Large Signal Transient esponse CM, COMMON MODE EJECTION (db) T A = 55 C V CM A DM V CM CM = 2 Log x A DM... k k k. M M f, FEQUENCY (Hz) = 5 V V EE = 5 V V CM = V V CM = ±.5 V Figure 32. Common Mode ejection versus Frequency PS, POWE SUPPLY EJECTION (db) 6 4 A DM V EE PS = 2 Log /A DM 2 /A DM PS = 2 Log PS V EE ( V EE =.5 V)... k k k. M M f, FEQUENCY (Hz) = 5 V V EE = 5 V ( =.5 V) Figure 33. Power Supply ejection versus Frequency PS

11 MC347,2,4,A MC337,2,4,A, NCV3372,4,A I CC, SUPPLY CUENT (ma) T A = 55 C Quad device , V EE, SUPPLY VOLTAGE (V) Figure 34. Supply Current versus Supply Voltage PS, POWE SUPPLY EJECTION (db) PS ( V EE =.5 V) PS = 2 Log PS = 2 Log PS ( =.5 V) /A DM /A DM V EE A DM T A, AMBIENT TEMPEATUE ( C) Figure 35. Power Supply ejection versus Temperature = 5 V V EE = 5 V V EE CHANNEL SEPAATION (db) = 5 V V EE = 5 V f, FEQUENCY (khz) Figure 36. Channel Separation versus Frequency nv Hz ) e, n INPUT NOICE VOLTAGE ( Voltage Current. k k k f, FEQUENCY (khz) = 5 V V EE = 5 V V CM = Figure 37. Input Noise versus Frequency i, INPUT NOISE CUENT (pa Hz ) n APPLICATIONS INFOMATION CICUIT DESCIPTION/PEFOMANCE FEATUES Although the bandwidth, slew rate, and settling time of the MC347 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the V EE potential, single supply operation is feasible to as low as 3. V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to ±44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between V EE and supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the voltage by approximately 3. V and decrease below the V EE voltage by.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to approximately 5. ma of current from V EE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pf) than the typical JFET input gate capacitance (5. pf), better frequency response for a given input source resistance can be achieved using the MC347 series of amplifiers. This performance feature becomes evident, for example, in fast settling DtoA current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher

12 MC347,2,4,A MC337,2,4,A, NCV3372,4,A values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2. k of feedback resistance, the MC347 series can settle to within /2 LSB of bits in. s, and within /2 LSB of 2bits in 2.2 s for a V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is ±3 V/ s. In the classic noninverting unity gain configuration, the output positive slew rate is V/ s, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3. mv prime and 5. mv downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A k load resistance can swing within. V of the positive rail ( ), and within.3 V of the negative rail (V EE ), providing a 2.7 V pp swing from ±5 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q 7, and V BE of the NPN pull up transistor Q 7, and the voltage drop associated with the short circuit resistance, 7. The negative swing is limited by the saturation voltage of the pulldown transistor Q 6, the voltage drop I L 6, and the voltage drop associated with resistance 7, where I L is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of V EE. For large valued sink currents (>5. ma), diode D3 clamps the voltage across 6, thus limiting the negative swing to the saturation voltage of Q 6, plus the forward diode drop of D3 ( V EE. V). Thus for a given supply voltage, unprecedented peaktopeak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitterfollower transistor has been eliminated, the MC347 series offers a 2 ma minimum current sink capability, typically to an output voltage of (V EE. V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier s high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (3 MHz) allows capacitive drive capability from pf to, pf without oscillation in the unity closed loop gain configuration. The 6 phase margin and 2 db gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC347 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5. V, these amplifiers are functional to C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted inputoutput coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous pick up at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for ±5 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating. 2

13 MC347,2,4,A MC337,2,4,A, NCV3372,4,A (Typical Single Supply Applications = 5. V) 5. M 3.7 V pp 2 k C. M k in C O VO 6 k MC mv pp C in k MC347 k k L k V. k A V = in 37 mv pp BW (3. db) = 45 khz A V = BW (3. db) = 45 khz C O 3.7 V pp k L Figure 3. AC Coupled Noninverting Amplifier Figure 39. AC Coupled Inverting Amplifier 2.63 V 4.75 V pp 9 k 5. k k 5. k L MC347. M A V = BW (3. db) = 45 khz 2.5 V to, pf MC347 Cable MC54/74XX TTL Gate Figure 4. DC Coupled Inverting Amplifier Maximum Output Swing Figure 4. Unity Gain Buffer TTL Driver.2 Vdc 6 k C. 2. C.2 32 k 6 k C.2 MC347 f o =. khz f o = 4 C. k 5.6 k C.47 C k.4 MC347 Given f o = Center Frequency A O = Gain at Center Frequency Choose Value f o, Q, A o, C Then: Q = = = f 2H o 4Q 2 o C 3 For less than % error from operational amplifier where f o and GBW are expressed in Hz. GBW = 4.5 MHz Typ. f o = 3 khz H o = H o =. Q o f o GBW <. Figure 42. Active HighQ Notch Filter Figure 43. Active Bandpass Filter 3

14 MC347,2,4,A MC337,2,4,A, NCV3372,4,A C F 2. V Bit Switches k 5. k 5. k k k 5. k F MC347 MC k L. V 4. V 3 V/ s t.2 s Delay 25 V/ s () Ladder Network Settling Time. s (Bits, /2 LSB). Delay. s t Figure 44. Low Voltage Fast D/A Converter Figure 45. High Speed Low Voltage Comparator ON" < V ref V ref MC347 ON" > V ref MC347 L MC347 L (A) PNP (B) NPN Figure 46. LED Driver Figure 47. Transistor Driver I Load Ground Current Sense esistor S MC347 = I Load S I Cell F MC347 For >.V BW ( 3. db) = GBW V Cell = V = I Cell F >. V Figure 4. AC/DC Ground Current Monitor Figure 49. Photovoltaic Cell Amplifier 4

15 MC347,2,4,A MC337,2,4,A, NCV3372,4,A Hysteresis V ref L = MC347 (L V ref )V ref H L L V ref H MC347 I out H = (H V ref )V ref V H = (H L ) I out = ±V IO Figure 5. Low Input Voltage Comparator with Hysteresis Figure 5. High Compliance Voltage to Sink Current Converter 4 V V2 = = 4 3 /2 3 MC3472 /2 MC3472 (Critical to CM) 4 3 For (V2 V), V > V2V 4 3 Figure 52. High Input Impedance Differential Amplifier = V ref F MC347 F = V ref < < F 2 2 F > > (. V) Figure 53. Bridge Current Amplifier f OSC.5 C V I B I SC V P t MC347 = (pk) t Base Charge emoval I out L V P, pf C /2 MC3472 /2 MC3472 ±I B V k 47 k k V P Pulse Width Control Group V P Figure 54. Low Voltage Peak Detector t OSC Comparator High Current Output Figure 55. High Frequency Pulse Width Modulation 5

16 MC347,2,4,A MC337,2,4,A, NCV3372,4,A GENEAL ADDITIONAL APPLICATIONS INFOMATION V S = ±5. V C.44 Figure 56. Second Order LowPass Active Filter 5.6 k MC347 C2.2 Choose: f o, H o, C2 Then: C = 2C2 (H o ) f o =. khz H o = 2 = 3 = = 4 f o C2 H o H o C2.5 C. C.. k 46. k Choose: f o, H o, C Then: = Figure 57. Second Order HighPass Active Filter MC347 = C2 = f o = Hz H o = 2 H o.5 f o C f o C (/H o 2) C H o C F * F = V Step 2. k MC347 MC347 L I High Speed DAC Uncompensated Compensated t s =. s to /2 LSB (Bits) t s = 2.2 s to /2 LSB (2Bits) = BW (3. db) = GBW *Optional Compensation S = 3 V/ s S = 3 V/ s Figure 5. Fast Settling Inverter Figure 59. Basic Inverting Amplifier MC347 L MC347 = BW (3. db) = GBW BW p = 2 khz = 2 V pp S = V/ s Figure 6. Basic Noninverting Amplifier Figure 6. Unity Gain Buffer (A V =.) 6

17 MC347,2,4,A MC337,2,4,A, NCV3372,4,A MC3474 E MC3474 MC3474 Example: Let: = E = 2 k Then: A V = 3. BW =.5 MHz A V = 2 E Figure 62. High Impedance Differential Amplifier k MC3474 L MC pf L.93.7 k 5. k k k MC3474 L Figure 63. Dual Voltage Doubler 7

18 MC347,2,4,A MC337,2,4,A, NCV3372,4,A ODEING INFOMATION Op Amp Function Device Operating Temperature ange Package Shipping MC347PG PDIP (PbFree) 5 Units / ail MC347APG PDIP (PbFree) 5 Units / ail MC347DG MC347DG T A = to 7 C SOIC (PbFree) SOIC (PbFree) 9 Units / ail 25 / Tape & eel MC347ADG SOIC (PbFree) 9 Units / ail Single MC347ADG MC337PG SOIC (PbFree) PDIP (PbFree) 25 / Tape & eel 5 Units / ail MC337APG PDIP (PbFree) 5 Units / ail MC337DG MC337DG T A = 4 to 5 C SOIC (PbFree) SOIC (PbFree) 9 Units / ail 25 / Tape & eel MC337ADG SOIC (PbFree) 9 Units / ail MC337ADG SOIC (PbFree) 25 / Tape & eel

19 MC347,2,4,A MC337,2,4,A, NCV3372,4,A ODEING INFOMATION (continued) Op Amp Function Device MC3472PG Dual MC3472APG MC3472DG MC3472ADG MC3472DG MC3472ADG MC3472AMTTBG MC3372PG MC3372APG MC3372DG MC3372ADG MC3372DG MC3372ADG Operating Temperature ange T A = to 7 C T A = 4 to 5 C Package PDIP (PbFree) PDIP (PbFree) SOIC (PbFree) SOIC (PbFree) SOIC (PbFree) SOIC (PbFree) WQFN (PbFree) PDIP (PbFree) PDIP (PbFree) SOIC (PbFree) SOIC (PbFree) SOIC (PbFree) SOIC (PbFree) Shipping 5 Units / ail 9 Units / ail 25 Units / Tape & eel 3 Units / Tape & eel 5 Units / ail 9 Units / ail 25 / Tape & eel MC3472VDG SOIC (PbFree) 9 Units / ail MC3472VDG SOIC 25 / Tape & eel (PbFree) T A = 4 to 25 C MC3472VPG PDIP 5 Units / ail (PbFree) NCV3372DG* SOIC 25 / Tape & eel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, BD/D. *NCV prefix for automotive and other applications requiring unique site and control change requirements; AECQ qualified and PPAP capable. 9

20 MC347,2,4,A MC337,2,4,A, NCV3372,4,A ODEING INFOMATION (continued) Op Amp Function Device MC3474PG Quad MC3474APG MC3474DG MC3474ADG MC3474ADG MC3474DG MC3374PG MC3374APG MC3374DG MC3374ADG MC3374DG NCV3374DG* MC3374ADG NCV3374ADG* MC3374DTBG MC3374DTBG MC3374ADTBG MC3374ADTBG NCV3374ADTBG* Operating Temperature ange T A = to 7 C T A = 4 to 5 C Package PDIP4 (PbFree) PDIP4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) PDIP4 (PbFree) PDIP4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) SOIC4 (PbFree) TSSOP4 (PbFree) TSSOP4 (PbFree) TSSOP4 (PbFree) TSSOP4 (PbFree) TSSOP4 (PbFree) Shipping 25 Units / ail 55 Units / ail 25 Units / Tape & eel 25 Units / ail 55 Units / ail 25 / Tape & eel 25 / Tape & eel 96 Units / ail 25 / Tape & eel 96 Units / ail 25 / Tape & eel MC3474VDG SOIC4 (PbFree) 55 Units / ail MC3474VDG SOIC4 NCV3474VDG* T A = 4 to 25 C (PbFree) SOIC4 (PbFree) 25 / Tape & eel MC3474VPG PDIP4 (PbFree) 25 Units / ail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and eel Packaging Specifications Brochure, BD/D. *NCV prefix for automotive and other applications requiring unique site and control change requirements; AECQ qualified and PPAP capable. 2

21 MC347,2,4,A MC337,2,4,A, NCV3372,4,A MAKING DIAGAMS PDIP P SUFFIX CASE 626 MC3x7P AWL YYWWG MC3x7AP AWL YYWWG MC3x72P AWL YYWWG MC3x72AP AWL YYWWG MC3472VP AWL YYWWG SOIC D SUFFIX CASE 75 3x7 ALYW 3x7 ALYWA 3x72 ALYW 3x72 ALYWA 3472 ALYWV *applies to NCV3372DG 4 4 PDIP4 P SUFFIX CASE MC3x74P AWLYYWWG MC3x74AP AWLYYWWG MC3474VP AWLYYWWG SOIC4 D SUFFIX CASE 75A TSSOP4 DTB SUFFIX CASE 94G MC3x74DG AWLYWW MC3x74ADG AWLYWW MC3474VDG AWLYWW *applies to NCV3474VDG WQFN MT SUFFIX CASE 5AJ MC33 74 ALYW MC33 74A ALYW NCV3 74A ALYW 472 AAYW x = 3 or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package (Note: Microdot may be in either location) 2

22 MC347,2,4,A MC337,2,4,A, NCV3372,4,A PACKAGE DIMENSIONS LEAD PDIP CASE 6265 ISSUE N NOTE A D D 5 4 b2 TOP VIEW e/2 e SIDE VIEW A E B A2 A NOTE 3 L C SEATING PLANE H eb X b END VIEW. M C A M B M NOTE 6 E c END VIEW WITH LEADS CONSTAINED M NOTE 5 NOTES:. DIMENSIONING AND TOLEANCING PE ASME Y4.5M, CONTOLLING DIMENSION: INCHES. 3. DIMENSIONS A, A AND L AE MEASUED WITH THE PACK AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3. 4. DIMENSIONS D, D AND E DO NOT INCLUDE MOLD FLASH O POTUSIONS. MOLD FLASH O POTUSIONS AE NOT TO EXCEED. INCH. 5. DIMENSION E IS MEASUED AT A POINT.5 BELOW DATUM PLANE H WITH THE LEADS CONSTAINED PEPENDICULA TO DATUM C. 6. DIMENSION E3 IS MEASUED AT THE LEAD TIPS WITH THE LEADS UNCONSTAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHEE THE LEADS EXIT THE BODY.. PACKAGE CONTOU IS OPTIONAL (OUNDED O SQUAE CONES). INCHES MILLIMETES DIM MIN MAX MIN MAX A A.5.3 A b b2.6 TYP.52 TYP C D D.5.3 E E e. BSC 2.54 BSC eb L M PDIP4 CASE 6466 ISSUE A D D 4 7 NOTE b2 TOP VIEW e SIDE VIEW A E c B END VIEW WITH LEADS CONSTAINED NOTE 5 A2 A NOTE 3 L C H SEATING PLANE 4X b. M C A M B M E M eb END VIEW NOTE 6 NOTES:. DIMENSIONING AND TOLEANCING PE ASME Y4.5M, CONTOLLING DIMENSION: INCHES. 3. DIMENSIONS A, A AND L AE MEASUED WITH THE PACK AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3. 4. DIMENSIONS D, D AND E DO NOT INCLUDE MOLD FLASH O POTUSIONS. MOLD FLASH O POTUSIONS AE NOT TO EXCEED. INCH. 5. DIMENSION E IS MEASUED AT A POINT.5 BELOW DATUM PLANE H WITH THE LEADS CONSTAINED PEPENDICULA TO DATUM C. 6. DIMENSION E3 IS MEASUED AT THE LEAD TIPS WITH THE LEADS UNCONSTAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHEE THE LEADS EXIT THE BODY.. PACKAGE CONTOU IS OPTIONAL (OUNDED O SQUAE CONES). INCHES MILLIMETES DIM MIN MAX MIN MAX A A.5.3 A b b2.6 TYP.52 TYP C D D.5.3 E E e. BSC 2.54 BSC eb L M 22

23 MC347,2,4,A MC337,2,4,A, NCV3372,4,A PACKAGE DIMENSIONS TSSOP4 CASE 94G ISSUE B.5 (.6) T.5 (.6) T L. (.4) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 4X K EF. (.4) M T U S V S N.25 (.) M B U 7 A V G H N J J F DETAIL E K K DETAIL E ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ SECTION NN NOTES:. DIMENSIONING AND TOLEANCING PE ANSI Y4.5M, CONTOLLING DIMENSION: MILLIMETE. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, POTUSIONS O GATE BUS. MOLD FLASH O GATE BUS SHALL NOT EXCEED.5 (.6) PE SIDE. 4. DIMENSION B DOES NOT INCLUDE INTELEAD FLASH O POTUSION. INTELEAD FLASH O POTUSION SHALL NOT EXCEED.25 (.) PE SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE. (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATEIAL CONDITION. 6. TEMINAL NUMBES AE SHOWN FO EFEENCE ONLY. 7. DIMENSION A AND B AE TO BE DETEMINED AT DATUM PLANE W. MILLIMETES INCHES DIM MIN MAX MIN MAX A B C.2.47 D F G.65 BSC.26 BSC H J J W K K L 6.4 BSC.252 BSC M SOLDEING FOOTPINT* PITCH 4X.36 4X.26 DIMENSIONS: MILLIMETES *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. 23

24 MC347,2,4,A MC337,2,4,A, NCV3372,4,A PACKAGE DIMENSIONS SOIC NB CASE 757 ISSUE AK Y B X A 5 4 S.25 (.) M Y M K NOTES:. DIMENSIONING AND TOLEANCING PE ANSI Y4.5M, CONTOLLING DIMENSION: MILLIMETE. 3. DIMENSION A AND B DO NOT INCLUDE MOLD POTUSION. 4. MAXIMUM MOLD POTUSION.5 (.6) PE SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE DAMBA POTUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATEIAL CONDITION THU 756 AE OBSOLETE. NEW STANDAD IS 757. Z H G D C.25 (.) M Z Y S X S SEATING PLANE. (.4) N X 45 M J MILLIMETES INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC.5 BSC H J K M N S SOLDEING FOOTPINT* SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. 24

25 MC347,2,4,A MC337,2,4,A, NCV3372,4,A PACKAGE DIMENSIONS SOIC4 CASE 75A3 ISSUE K H 4.25 M B M e D 7 3X b A B E.25 M C A S B S A A C SEATING PLANE L DETAIL A h X 45 M A3 DETAIL A NOTES:. DIMENSIONING AND TOLEANCING PE ASME Y4.5M, CONTOLLING DIMENSION: MILLIMETES. 3. DIMENSION b DOES NOT INCLUDE DAMBA POTUSION. ALLOWABLE POTUSION SHALL BE.3 TOTAL IN EXCESS OF AT MAXIMUM MATEIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD POTUSIONS. 5. MAXIMUM MOLD POTUSION.5 PE SIDE. MILLIMETES INCHES DIM MIN MAX MIN MAX A A A b D E e.27 BSC.5 BSC H h L M 7 7 SOLDEING FOOTPINT* 6.5 4X..27 PITCH 4X.5 DIMENSIONS: MILLIMETES *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. 25

26 MC347,2,4,A MC337,2,4,A, NCV3372,4,A PACKAGE DIMENSIONS WQFN CASE 5AJ ISSUE A NOTE 4 PIN ONE EFEENCE.5 C. C. C D ÍÍÍ ÍÍÍ ÍÍÍ.5 C 9X L 4 TOP VIEW DETAIL B SIDE VIEW A DETAIL A 5 6 A3 A B E A C SEATING PLANE L L DETAIL A ALTENATE TEMINAL CONSTUCTIONS EXPOSED Cu ÉÉÉ ÉÉÉ MOLD CMPD DETAIL B ALTENATE CONSTUCTIONS L NOTES:. DIMENSIONING AND TOLEANCING PE ASME Y4.5M, CONTOLLING DIMENSION: MILLIMETES. 3. DIMENSION b APPLIES TO PLATED TEMINAL AND IS MEASUED BETWEEN.5 AND.3mm FOM TEMINAL. 4. COPLANAITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TEMINALS. MILLIMETES DIM MIN MAX A.7. A..5 A3.2 EF b.2.3 D 2.6 BSC E 2.6 BSC e.5 BSC L L..5 L SOLDEING FOOTPINT* PITCH 2.9 L2 9 e X b. C BOTTOM VIEW.5 C A B NOTE 3 X.3 X.73 DIMENSIONS: MILLIMETES *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques eference Manual, SOLDEM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ODEING INFOMATION LITEATUE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales epresentative MC347/D