Integrated Software-Defined Radio on Zynq All Programmable SoC Design Seminar

Transcription

1 Integrated Software-Defined Radio on Zynq All Programmable SoC Design Seminar

2 Course Objectives During this seminar, you will gain insight into Avnet Zynq-7000 AP SoC / AD9361 Software-Defined Radio Kits Principles of wireless communication with examples of IEEE Model-based Design using MATLAB and Simulink for simulation, algorithm validation and automatic code generation for wireless communications Integrating Simulink models into Zynq-based software-defined radio using Xilinx Vivado Design Suite 3

3 Wireless Communications System Design Challenges Systems start as abstract mathematical representations using statistical signal processing to model noise through the signal chain Relentless market demand for higher data throughput requires deep expertise in high speed analog and digital design Signals span wide range of frequencies from RF to baseband through analog and digital domains Requires robust, traceable and verifiable auto code-generation from mathematical model to efficient hardware / software code

4 Advantages of Zynq in Software-Defined Radio High-speed hardware-based digital signal processing PHY layer + software-based upper layer protocol stack Up to Gb/s GT for connectivity to latest generation JESD204B data converters Higher integration for simpler and lower cost PCB Tight coupling of HW & SW integration for seamless algorithm partitioning

5 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 7

6 Commercial Radio Communications Architecture Analog / RF Power Amplifier Baseband Processing Low noise Amp RF IQ De-Mod RF IQ Mod ADC ADC FEC Decode FEC Encode Packet Processing Network Interface Network Interface Focus RX TX Constellation Demapper Constellation Mapper ADC DFE DAC Main Processor DPD & CFR FFT ifft Control Processor Control Interface Digital Analog DDC DUC Baseband Interface (OBSAI / CPRI) Typical OFDMA Basestation

7 Zynq-7000 AP SoC / AD9361 SDR Evaluation Kit Hardware Avnet ZedBoard featuring Zynq 7020 All- Programmable SoC Analog Devices AD-FMCOMMS2-EBZ Highspeed analog FMC module with integrated RF agile transceiver (4) LTE-band antennas 8 GB SD card Software Tools Xilinx Vivado Design Edition UBUNTU desktop Linux on Zynq Reference Designs AES-ZSDR2-ADI-G $1295 Optional Development tools MathWorks DSP Wireless Communications Design Package for Xilinx Kits* * Available in North America only.

8 Zynq-7000 AP SoC / AD9361 SDR Evaluation Kit RF Band Factory-tuned for optimal performance at MHz Aimed at RF engineer seeking datasheet performance connecting to an RF testbench (VSA, Signal generator) Synchronization Supports MIMO radio, with less than 1 sample sync on both ADC and DAC Analog Devices AD-FMCOMMS2 Analog Devices AD9361 RF Agile Transceiver RF 2 2 transceiver with integrated 12-bit DACs and ADCs Supports TDD and FDD operation Tunable channel bandwidth: < 200 khz to 56 MHz RX gain control - Real-time monitor and control signals for manual gain - Independent automatic gain control

9 Zynq-7000 AP SoC / AD9361 SDR Systems Development Kit Hardware Xilinx ZC706 base board featuring XC7Z045 device Analog Devices AD-FMCOMMS3-EBZ High-speed analog FMC module with integrated RF agile transceiver (4) LTE-band antennas 8 GB SD card Software Tools Xilinx Vivado System Edition Device locked to XC7Z045 UBUNTU desktop Linux on Zynq Reference Designs AES-ZSDR3-ADI-G $3595 Optional Development tools MathWorks Wireless Communications Design Package for Xilinx Kits* * Available in North America only.

10 Zynq-7000 AP SoC / AD9361 SDR Systems Development Kit RF Band Operates over wide tuning range (70 MHz 6 GHz) Aimed at the system architect seeking a single platform for fast prototype of wideband wireless systems Synchronization Supports MIMO radio, with less than 1 sample sync on both ADC and DAC Analog Devices AD-FMCOMMS3 Analog Devices AD9361 RF Agile Transceiver RF 2 2 transceiver with integrated 12-bit DACs and ADCs Supports TDD and FDD operation Tunable channel bandwidth: < 200 khz to 56 MHz RX gain control - Real-time monitor + control signals for manual gain

11 Zynq-7000 Family Highlights Complete ARM -based Processing System o Dual ARM Cortex -A9 MPCore o L1, L2 Caches and On-Chip Memory o Fully Integrated Memory Controllers o I/O Peripherals (CAN, USB, Ethernet, UART, ) Tightly Integrated Programmable Logic o Used to extend Processing System o Scalable density and performance 30k 440k LCs, 80 2,020 DSP Blocks Flexible Array of I/O o Wide range of external multi standard I/O o High performance integrated serial transceivers o Analog-to-Digital Converter inputs Performance/power of an ASIC, flexibility of an FPGA, ease of use of an ASSP Page 15

12 Design Flow. Mathematical representation of software-defined radio signal chain Model-based design in Simulink o Captured data as repeatable stimulii o RF impairments o System performance analysis and visualization o Frequency domain o Digital modulation scatter plots, etc Simulink Device Under Test (DUT) Integration with RF Performance analysis and visualization

13 Design Flow Simulink IP Catalog IP Integrator IP Packager HDL Coder + AXI interface Device Under Test (DUT) AXI-Lite Wrapper DUT User IP FMCOMMS2 Base Design HDL Coder auto-code generation to bit-true / cycle-true HDL Import using Vivado IP Packager Vivado IP Integrator connects user model into existing base design

14 Design Flow Simulink IP Catalog IP Integrator IP Packager AXI-Lite Wrapper DUT User IP FMCOMMS2 Base Design HDL Coder + AXI interface Hardware platform + bitstream Device Under Test (DUT) SDK FSBL + Bitstream + Uboot.elf BOOT.bin Update SD card with design changes Test realtime operation on SDR kit

15 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 19

16 Zynq SDR Kit in Operation UBUNTU desktop Linux Analog Devices IIO Scope Manage all settings of FMCOMMS2 radio card

17 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 21

18 Design Flow. Simulink IP Catalog IP Packager HDL Coder Device Under Test (DUT) IP Integrator DUT User IP FMCOMMS2 Base Design Hardware platform + bitstream SDK FSBL + Bitstream + Uboot.elf BOOT.bin Start with base HDL reference design from ADI

19 Zynq / AD9361 SDR Kit Base Reference Design SD card image / includes Linux kernel + devicetree.dtb + BOOT.BIN AD-FMCOMMS2-EBZ + ZedBoard HDL Reference Design [Analog Devices Wiki]

20 Zynq / AD9361 SDR Kit Base Reference Design Download 25

21 Zynq / AD9361 SDR Kit Base Reference Design TCL script within each folder to build AXI peripherals Base reference design built with TCL scripts in Xilinx Vivado 26

22 Vivado Project Management with Tcl Vivado flows can be run using Tcl o Run full flow without interaction launch script and walk away o Enables repeatability and self-documentation Tcl commands can be o Interactively entered at the Tcl prompt in Vivado IDE o Called from a Tcl script within Vivado Tcl shell 27

23 Zynq / AD9361 SDR Kit Base Reference Design Processing System Dual Cortex -A9 MPCore NEON / FPU Engine Programmable Logic LINUX User-space applications VDMA HDMI LINUX drivers VDMA IIO oscilloscope AXI Interconnect IQ Demod ADC ADC ADC Interface FIFO ADI DMA AXI DDS DAC Interface DAC DAC IQ Mod AD-FMCOMMS2-EBZ

24 SDR Kit Base Reference Design with User Peripheral Processing System Dual Cortex -A9 MPCore NEON / FPU Engine Programmable Logic LINUX User-space applications VDMA HDMI LINUX drivers VDMA IIO oscilloscope AXI Interconnect IQ Demod ADC ADC ADC Interface FIFO ADI DMA User signal chain AXI AXI DDS DAC Interface DAC DAC IQ Mod AD-FMCOMMS2-EBZ

25 Agenda Demo 1 Demo 2 Break Demo 3 Demo 4 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Exploring the Base Reference Design in Xilinx Vivado Model-Based Design for Wireless Communications Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 30

26 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 37

27 Part 3 / Model-Based Design for Wireless Communications This lecture and demo will guide you through Model-based Design with MATLAB and Simulink Spread Spectrum Modulation in Digital Communications Simulink Model of IEEE Beacon Frame Receiver 38

28 Design Flow for IEEE Beacon Frame Receiver 39

29 Design Flow Simulink IP Catalog IP Packager IP Integrator DUT User IP FMCOMMS2 Base Design HDL Coder + AXI Hardware platform + bitstream Develop user signal chain (DUT) in Simulink Integrate into existing reference design Device Under Test (DUT) SDK FSBL + Bitstream + Uboot.elf BOOT.bin

30 Challenges of System-Level Design Verifying implementation matches algorithm Hand-coded HDL can be error prone and hard to debug Fixed-point implementation may not match floating-point model Test-benches for hardware and software from different teams may not match Algorithm and System Design HDL FPGAFPGA

31 Solution: Model-Based Design Design, simulate, and validate algorithms and system models in MATLAB and Simulink Automatically generate HDL code Verify the hardware implementation against the system model MATLAB and Simulink Algorithm Design and System Design HDL Code Generation Generate HDL Verify FPGA FPGA

32 Model-Based Design: From Concept to Production RESEARCH REQUIREMENTS DESIGN Environment Models Physical Components Algorithms IMPLEMENTATION TEST & VERIFICATION Model multi-domain systems Explore and optimize system behavior in floating point and fixed point Collaborate across teams and continents Generate efficient code Explore and optimize implementation tradeoffs Model concurrent systems C, C++ VHDL, Verilog Structured Text MCU DSP FPGA ASIC INTEGRATION PLC Automate regression testing Detect design errors Support certification and standards

33 Model-Based Design Tools The leading environment for technical computing The leading environment for modeling, simulating, and implementing dynamic and embedded systems Embedded Coder HDL Coder Toolboxes (signal, comms, etc.)

34 MathWorks Design Package for Software-Defined Radio Develop advanced communications systems on Zynq with tools for algorithm development and simulation along with code generation for C and HDL Algorithm Design and Simulation MATLAB Simulink Fixed-Point Designer Signal Processing Toolbox DSP System Toolbox Communications System Toolbox Code Generation for C and HDL MATLAB Coder Simulink Coder Embedded Coder HDL Coder Avnet part number AES-ZSDR2-ADI-G-MATW-ANUL

35 Device Under Test / Beacon Frame Receiver 49

36 LAN architecture Basic Service Set (BSS) o wireless hosts o access point (AP) Wireless hosts communicate with AP AP Internet hub, switch or router Mitigating interference and noise BSS 1 Frequency Hopping Spread Spectrum (FHSS) Infrared (IR) Orthogonal Frequency Division Multiplexing (OFDM) Direct Sequence Spread Spectrum (DSSS) AP BSS 2 50

37 Direct Sequence Spread Spectrum (DSSS) d t Transmitter tx DSSS Spreading + interference + other SS in channel rx Receiver DSSS de-spreading d t d t (f) Uncorrelated other SS users remain spread d t (f) De-spread signal f f -R s R s -R s R s DSSS increases the transmit signal bandwidth to R c, far beyond R s needed to transmit the underlying information De-spreading at receiver correlates with signal* Noise remains uncorrelated (spread) for lower power spectral density in original bandwidth of interest Processing gain Gp=BWss/BWinfo = Rc/Rs *Assuming synchronization of transmitter / receiver spreading sequences

38 Direct Sequence Spread Spectrum Each symbol is multiplied with a pseudo-noise (PN) sequence (aka chip sequence) T s d t +1-1 T c PN sequence DSSS PN sequences generated using deterministic algorithms (LFSR) but have properties of random sequences (flipping a coin N times) o Equal number of 1 and 0 o Short run-length o Shifting property: if shifted by any nonzero number of elements the resulting sequence has ½ its elements the same as the original sequence and ½ its elements different

39 11 chip BARKER sequence Used for DSSS in frame pre-amble Good autocorrelation properties Minimal sequence allowed by FCC Coding gain = 10log(11) = 10.4 db Received chip stream at time (t-1) Received chip stream at time (t) Received chip stream at time (t+1) +11 autocorrelation time

40 Direct Sequence Spread Spectrum (DSSS) d t I/Q Mod QDAC tx b tx rx I/Q Demod Q ADC rx b d r PN code PN t correlator synchronizer PN code PN r d t binary data with symbol rate R s = 1/T s PN t tx b Pseudo-noise code with chip rate R c = 1/T c (R s /R c = integer) Binary data d t multiplied with PN sequence = d t. PNt

41 Direct Sequence Spread Spectrum (DSSS) d t I/Q Mod QDAC tx b tx rx I/Q Demod Q ADC rx b d r PN code PN t correlator synchronizer PN code PN r d t binary data with symbol rate R s = 1/T s PN t tx b Pseudo-noise code with chip rate R c = 1/T c (R s /R c = integer) 11-chip Barker sequence Binary data d t multiplied with PN sequence = d t. PNt

42 Direct Sequence Spread Spectrum (DSSS) d t I/Q Mod QDAC tx b tx i(t) Interference / other SS rx I/Q Demod Q ADC rx b d r PN code PN t jω T t e ( Ω + ( )) T jω R t e d d PN PN correlator synchronizer PN code PN r j t jωrt r = t te i t e r jω t jω t jω = dt PNt PNre e + i( t) PNre 0 When RX and TX synchronized = 1 = e = 1 d = d PN r t T R R jωt t + i( t) re when carriers synchronized uncorrelated interference remains spread with low power spectral density t

43 Direct Sequence Spread Spectrum (DSSS) d t I/Q Mod QDAC tx b tx i(t) rx I/Q Demod Q ADC rx b d r PN t Interference / other SS with different PN correlator synchronizer PN r PN code PN code At the receiver, the signal correlates but not the interference 57

44 IEEE Beacon Frame Host must associate with an AP scans channels, listening for beacon frames contain AP s service set ID (SSID) & MAC address Host selects AP to associate with May perform authentication Will typically run DHCP to get IP address in AP s subnet BSS 1 AP Internet hub, switch or router AP BSS 2 58

45 Long PLCP Frame Format 1Mbps DBPSK SYNC 128 bits SFD 16 bits SIGNAL 8 bits SERVICE 8 bits LENGTH 16 bits CRC 16 bits Long PLCP Preamble 144 bits in 1 Mbps Long PLCP Header 48 bits in 1 Mbps PSDU/MPDU 1, 2, 5.5, 11 Mbps PPDU 1Mbps DBPSK Barker 2Mbps DQPSK Barker 5.5, 11Mbps DQPSK CCK Preamble and Header always at 1Mb/s DBPSK, 11-chip Barker sequence SYNC field = 128 one bits ( 1 ) o Scrambled by scrambler o Used for receiver synchronization

46 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 60

47 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq / AD9361 SDR Kit in Operation / Base Reference Design Xilinx Vivado Support for Zynq / AD9361 SDR Kit Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 62

48 HDL Simulation of Auto-Generated Code Simulink HDL Simulator Tesbench + stimulii HDL HDL Coder Device Under Test (DUT) Auto-generate code from HDL coder with self-checking testbench Create Vivado project and import HDL through Tcl script Verify HDL simulation matches generated HDL Coder model (bit-true / cycle-true)

49 Simulink HDL Coder / Code Generation with Testbench

50 HDL Simulation in Vivado HDL simulation matches Simulink generated gm_ model

51 Importing IP into Vivado Simulink IP Catalog IP Integrator FMCOMMS2 Base Design IP Packager AXI-Lite Wrapper DUT User IP Import DUT into project IP catalog Connect in Vivado IP Integrator HDL Coder + AXI interface Hardware platform + bitstream Device Under Test (DUT) SDK FSBL + Bitstream + Uboot.elf BOOT.bin

52 MathWorks HDL Peripheral with AXI-Lite Interface Programmable Logic AXI Interconnect AXI-Lite Wrapper Device Under Test HDL Generate HDL code with AXI-Lite interface Includes DUT / algorithm plus AXI-Lite register logic / address decoding for RD/WR Integrate within Vivado top-level project 68

53 Add HDL Code as AXI-Lite IP in Vivado Design Suite IP Packager Vivado Project HDL Code Vivado IP Integrator PL bitstream (.bit) AXI Interconnect Programmable Logic AXI-Lite Wrapper Algorithm HDL 69

54 Vivado IP Integrator Enables reuse to create fully functional IP subsystems IP Packager Source (C, RTL, IP) Simulation models Documentation Example Designs Test bench Standardized IP-XACT IP Subsystem Xilinx IP 3 rd Party IP User IP Uses multiple plug-and-play forms of IP to implement functional subsystem Includes software drivers and API Accelerates integration and productivity

55 Vivado IP Integrator Accelerates hardware design productivity through design reuse Vivado IP Catalog - Standardized IP-XACT Subsystems Xilinx 3 rd Party User o Graphical IP assembly o Correct-by-construction o System centric Generates IP subsystems o Supports multiple plug-and-play IP formats o Generates software drivers and APIs Board and silicon aware o Built in support for Xilinx development baseboards Page 71

56 Connecting Software to Hardware for Zynq Simulation Production Simulink Algorithm Model Algorithm Model Embedded Coder How do I add AXI-Lite HW and SW interfaces HDL Coder Algorithm C Linux Driver AXI Interface Algorithm HDL ARM AXI Bus System Code IP1 IP2 IP3 Programmable Logic Motor Model Motor System 72

57 Add C Code in Xilinx Software Development Kit Xilinx SDK PL bitstream FSBL + U-Boot Boot.bin SD Card C Code User Space Application.ELF Root File System Processing System LINUX User Application AXI Interconnect DeviceTree (.dtb) Linux Kernel Boot SD Card 73

58 SW / HW Integration of Simulink model in Zynq LINUX Algorithm C User Space Application UIO Driver AXI Interconnect AXI-Lite Wrapper Algorithm HDL Linux DeviceTree must be updated with PL peripheral info User space controls peripheral via UIO driver calls Automated build processes are possible with MATLAB and TCL scripting 74

59 ADI Reference Design Linux IIO Drivers The Linux Industrial I/O (IIO) subsystem is intended to provide support for devices that, in some sense, are analog-to-digital or digital-to-analog converters o Devices that fall into this category are: ADCs DACs Accelerometers, gyros, IMUs Capacitance-to-Digital converters (CDCs) Pressure, temperature, and light sensors, etc. RF Transceivers (like the AD9361) o Can be used on ADCs ranging from a 1MSPS SoC ADC to >250 MSPS industrial ADCs o Developed during 2009, committed Jan 2010, moved out of staging Nov 2011, now in all mainline Linux kernels. The IIO Divers for the motor control solution require the HDL cores to have a specified register map A DMA interface is set up for high speed data transfer using multiple multiplexed data channels

60 ADI Reference Design Device Tree Example Each IIO driver has in the device tree an entry related to the actual driver and an entry corresponding to the allocated DMA Each HDL core has a base register map that can be extended to match the desired functionality Having a well established framework allows new devices to be easily added into the system both from a Linux and a HDL perspective

61 Complete Design Flow for Stand-Alone Deployment Simulink IP Catalog IP Integrator IP Packager AXI-Lite Wrapper DUT User IP FMCOMMS2 Base Design HDL Coder + AXI interface Hardware platform + bitstream Device Under Test (DUT) SDK FSBL + Bitstream + Uboot.elf BOOT.bin

62 Stand-alone SDR System for Zynq Processing System Dual Cortex -A9 MPCore NEON / FPU Engine Programmable Logic LINUX User-space applications VDMA HDMI LINUX drivers VDMA IIO oscilloscope AXI Interconnect IQ Demod ADC ADC ADC Interface FIFO ADI DMA User signal chain FIFO ADI DMA AXI DDS DAC Interface DAC DAC IQ Mod AD-FMCOMMS2-EBZ

63 Agenda Demo 1 Topic Introducing the Zynq AP SoC / AD9361 SDR Kit Zynq SDR Kit in Operation / Base Reference Design Analog Devices AD9361 Integrated RF Transceiver Demo 2 Exploring the Base Reference Design in Xilinx Vivado Break Model-Based Design for Wireless Communications Demo 3 Demo 4 Simulink Model of IEEE Beacon Frame Receiver Deploying Simulink models with Xilinx Vivado Design Suite Beacon Frame Receiver in Stand-Alone Operation 80

64 THANK YOU! 82

65 Appendix 83

66 Reference Links AD-FMCOMMS2-EBZ ebz/hardware/functional_overview AD-FMCOMMS2-EBZ HDL Reference Design ebz/reference_hdl AD9361 Integrated RF Agile Transceiver SD Card Image Files for Zynq + AD9361/64 IEEE HDL Optimized Beacon Frame Receiver

67 Xilinx DSP Slice Wide multiplies for greater numerical precision Independent access to accumulators Interconnect DSP48 Tile DSP48 E1 Slice DSP48 E1 Slice B A D C Pre-Add +/- 25x18 X DSP48E1 Slice 48-Bit Accum + - = Pattern Detector P Two DSP48E1 slices / tile connected by 5 highspeed interconnects Flexible access to dedicated pre-adder Pattern detector for efficient rounding hardware Resources per Family Artix Kintex Virtex Zynq Max DSP48E1 Fmax 628 MHz 741 MHz 741 MHz 741 MHz Max DSP48E1 Count