NCN8025 / NCN8025A. Compact SMART CARD Interface IC

Transcription

1 Compact SMART CARD Interface IC The NCN805 / NCN805A is a compact and costeffective single smart card interface IC. It is dedicated for.8 / 3.0 / 5.0 smart card reader/writer applications. The card CC supply is provided by a builtin very low drop out and low noise LDO. The device is fully compatible with the ISO 7863, EM., UICC and related standards including NDS and other STB standards (Nagravision, Irdeto...). It satisfies the requirements specifying conditional access into SetTopBoxes (STB) or Conditional Access Modules (CAM and CAS). This smart card interface IC is available in a QFN package (NCN805A) providing all of the industrystandard features usually required for STB smart card interface. It is also offered in a very compact package profile, QFN6 (NCN805), satisfying the requirements of costefficiency and spacesaving requested by CAM and SIM applications. For details regarding device implementation refer to application note AND8003/D, available upon request (please contact your local ON Semiconductor sales office or representative). Features Single IC Card Interface Fully Compatible with ISO 7863, EM., UICC and Related Standards Including NDS and Other STB Standards (Nagravision, Irdeto...) 3 Bidirectional Buffered I/O Level Shifters (C, C7 and C8) (QFN) Bidirectional I/O Level Shifter for the QFN6 compact version.8, 3.0 or % Regulated Card Power Supply Generation such as ICC 70 ma Regulator Power Supply: DDP =.7 to 5.5 (@.8 ), 3.0 to 5.5 (@ 3.0 ) &.85 to 5.5 (@ 5.0 ) Independent Power Supply range on Controller Interface such as DD =.7 to 5.5 Handles Class A, B and C Smart Cards Short Circuit Protection on all Card Pins Support up to 7 MHz input Clock with Internal Division Ratio /, /, / and /8 through CLKDI and CLKDI ESD Protection on Card Pins up to +8 k (Human Body Model) Activation / Deactivation Sequences (ISO786 Sequencer) Fault Protection Mechanisms Enabling Automatic Device Deactivation in Case of Overload, Overheating, Card Takeoff or Power Supply Dropout (OCP, OTP, UP) QFN MN SUFFIX CASE 85L QFN6 MT SUFFIX CASE 88AK MARKING DIAGRAMS NCN 805A ALYW NCN 805 ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week = PbFree Package (*Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Interrupt Signal INT for Card Presence and Faults External Underoltage Lockout Threshold Adjustment on DD (PORADJ Pin) (Except QFN6) Available in Package Formats: QFN (NCN805A) and QFN6 (NCN805) These are PbFree Devices Typical Application Pay T, Set Top Box Decoder with Conditional Access and Payperiew Conditional Access Module (CAM / CAS) SIM card interface applications (UICC / USIM) Point Of Sales and Transaction Terminals Electronic Payment and Identification Semiconductor Components Industries, LLC, 0 May, 0 Rev. Publication Order Number: NCN805/D

2 DDP 00 nf DD 0 uf 00 nf DD DDP Host Controller CONTROL R R DD INT PORADJ CMDCC SEL0 SEL CLKDI CLKDI NCN805A CCC CRST CCLK CAUX CAUX 00 nf 0 nf 3 SMART CARD DET CC RST CLK C DET PP I/O C NO CLKIN CI/O DATA PORT RSTIN I/Ouc AUXuc AUXuc Figure. Typical Smart Card Interface Application SEL CLKDI CLKDI AUXuc AUXuc 3 0 I/Ouc 9 SEL CLKDI CLKDI I/Ouc SEL0 8 CLKIN DDP CI/O 3 5 NCN805A 5 Exposed Pad INT DD RSTIN SEL0 DDP CI/O 3 NCN805 7 Exposed Pad 0 9 CLKIN INT DD RSTIN CAUX 6 3 PORADJ CAUX CCLK CRST CCC CMDCC CCLK CRST CCC CMDCC Figure. NCN805A QFN Pinout (Top iew) Figure 3. NCN805 QFN6 Pinout (Top iew)

3 DD 5 6 DDP Supply oltage Monitoring Thermal Control PORADJ 3.8 / 3 / 5 LDO CCC SEL0 SEL CMDCC INT 7 Control Logic and Fault Detection ISO786 Sequencer Card Detection 3 CLKDI CLKDI CLKIN RSTIN I/Ouc 8 9 Card Pin Level Shifters & Drivers 9 CCLK 0 CRST 5 CIO AUXuc 0 7 CAUX AUXuc 3 Clock Divider 6 CAUX 5 8 Figure. NCN805A Block Diagram (QFN Pin Numbering) PIN FUNCTION AND DESCRIPTION Pin (QFN) Pin (QFN6) Name Type Description SEL0 Input Allows selecting card CC power supply voltage mode (5/3 or.8/3) SEL0 = Low; CCC = 5 when SEL = High or 3 when SEL = Low SEL0 = High; CCC =.8 when SEL = High or 3 when SEL = Low DDP Power Regulator power supply. 3 3 Input Card presence pin active (card present) when = Low. A builtin debounce timer of about 8 ms is activated when a card is inserted. Convenient for Normally Open (NO) Smart card connector. Input Card presence pin active (card present) when = High. A builtin debounce timer of about 8 ms is activated when a card is inserted. Convenient for Normally Closed (NC) smart card connector. 5 CI/O Input/ Output This pin handles the connection to the serial I/O (C7) of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the micro controller. A k (typical) pull up resistor to CCC provides a High impedance state for the smart card I/O link. 3

4 PIN FUNCTION AND DESCRIPTION Pin (QFN) Pin (QFN6) Name Type 6 CAUX Input/ Output 7 CAUX Input/ Output 8 Ground Card Ground Description This pin handles the connection to the chip card s serial auxiliary AUX I/O pin (C8). A bidirectional level translator adapts the serial I/O signal between the card and the micro controller. A k (typical) pull up resistor to CCC provides a High impedance state for the smart card C8 pin. This pin handles the connection to the chip card s serial auxiliary AUX I/O pin (C). A bidirectional level translator adapts the serial I/O signal between the card and the micro controller. A k (typical) pull up resistor to CCC provides a High impedance state for the smart card C pin. 9 5 CCLK Output This pin is connected to the CLOCK card connector s pin (Chip card s pin C3). The Clock signal comes from the CLKIN input through clock dividers and level shifter. 0 6 CRST Output This pin is connected to the chip card s RESET pin (C) through the card connector. A level translator adapts the external Reset (RSTIN) signal to the smart card. 7 CCC Power Output This pin is connected to the smart card power supply pin (C). An internal low dropout regulator is programmable using the pins SEL0 and SEL to supply either 5 or 3 or.8 output voltage. An external distributed ceramic capacitor ranging from 80 nf to. F recommended must be connected across CCC and C. This set of capacitor (if distributed) must be low ESR (< 00 m ). 8 CMDCC Input Command CC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is enabled by toggling CMDCC High to Low and when a card is present. 3 PORADJ Input Poweron reset threshold adjustment input pin for changing the reset threshold ( DD ULO threshold) thanks to an external resistor power divider. Needs to be connected to ground when unused. 9 RSTIN Input This Reset input connected to the host and referred to DD (microcontroller side), is connected to the smart card Reset pin through the internal level shifter which translates the level according to the CCC programmed value. 5 0 DD Power input 6 Ground Ground This pin is connected to the system controller power supply. It configures the level shifter input stage to accept the signals coming from the controller. A 0. F decoupling capacitor shall be used. When DD is below.30 typical the card pins are disabled. 7 INT Output The interrupt request is activated LOW on this pin. This is enabled when a card is present and the card presence is detected by or pins. Similarly an interrupt is generated when CCC is overloaded. Inverter output (An opendrain output configuration with 50 k pullup resistor is available under request (metal change)). 8 CLKIN Input Clock Input for External Clock 9 3 I/Ouc Input / Output 0 AUXuc Input / Output AUXuc Input / Output This pin is connected to an external microcontroller. A bidirectional level translator adapts the serial I/O signal between the smart card and the external controller. A builtin constant k (typical) resistor provides a high impedance state. This pin is connected to an external microcontroller. A bidirectional level translator adapts the serial C signal between the smart card and the external controller. A builtin constant k (typical) resistor provides a high impedance state. This pin is connected to an external microcontroller. A bidirectional level translator adapts the serial C8 signal between the smart card and the external controller. A builtin constant k (typical) resistor provides a high impedance state. CLKDI Input This pin coupled with CLKDI is used to program the clock frequency division ratio (Table ). 3 5 CLKDI Input This pin coupled with CLKDI is used to program the clock frequency division ratio (Table ). 6 SEL Input Allows selecting card CC power supply voltage. SEL0 = Low: CCC = 5 when SEL = High or 3 when SEL = Low. SEL0 = High: CCC =.8 when SEL = High or 3 when SEL = Low. 5 7 Ground Regulator Power Supply Ground NOTE: All information below refers to QFN pin numbering unless otherwise noted. This information can be transposed to the QFN6 package according to the above PIN FUNCTION AND DESCRIPTION Table.

5 ATTRIBUTES Characteristics ESD protection Human Body Model (HBM) (Note ) Card Pins (card interface pins 3) All Other Pins Machine Model (MM) Card Pins (card interface pins 3) All Other Pins alues 8 k k Moisture sensitivity (Note ) QFN and QFN6 Level Flammability Rating Oxygen Index: 8 to 3 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test. Human Body Model (HBM), R = 500, C = 00 pf.. For additional information, see Application Note AND8003/D. UL in MAXIMUM RATINGS (Note 3) Rating Symbol alue Unit Regulator Power Supply oltage DDP 0.3 DDP 5.5 Power Supply from Microcontroller Side DD 0.3 DD 5.5 External Card Power Supply CCC 0.3 CCC 5.5 Digital Input Pins in 0.3 in DD Digital Output Pins (I/Ouc, AUXuc, AUXuc, INT) out 0.3 out DD Smart card Output Pins out 0.3 out CCC Thermal Resistance JunctiontoAir (Note ) QFN QFN6 R JA 37 8 C/W Operating Ambient Temperature Range T A 0 to +85 C Operating Junction Temperature Range T J 0 to +5 C Maximum Junction Temperature T Jmax +5 C Storage Temperature Range T stg 65 to + 50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T A = +5 C.. Exposed Pad () must be connected to PCB. 5

6 POWER SUPPLY SECTION ( DD = 3.3 ; DDP = 5 ; T amb = 5 C; F CLKIN = 0 MHz) Symbol Rating Min Typ Max Unit DDP Regulator Power Supply, CCC = 5.0, ICC 70 ma (EM Conditions) ICC 70 ma (NDS Conditions) CCC = 3.0, ICC 70 ma CCC =.8, ICC 70 ma I DDP Inactive mode (CMDCC = High) A I DDP DC Operating supply current, F CLKIN = 0 MHz, Cout CCLK = 33 pf, I CCC = 0 (CMDCC = Low) I DDP DC Operating supply current, CCC = 5, I CCC = 70 ma CCC = 3, I CCC = 70 ma CCC =.8, I CCC = 70 ma 3.0 ma DD Operating oltage I DD Inactive mode standby current (CMDCC = High) 60 A I DD Operating Current F CLK_IN = 0 MHz, Cout CCLK = 33 pf I CCC = 0 (CMDCC = Low) ma ma ULO DD Under oltage LockOut (ULO), no external resistor at pin PORADJ (connected to ), falling DD level ULOHys ULO Hysteresis, no external resistor at pin PORADJ (Connected to ) m PORADJ pin PORth+ External Rising threshold voltage on DD for Power On Reset pin PORADJ PORth External Falling threshold voltage on DD for Power On Reset pin PORADJ PORHys Hysteresis on PORth (pin PORADJ) m t POR Width of PowerOn Reset pulse (Note 5) No external resistor on PORADJ External resistor on PORADJ 8 8 ms ms I IL Low level input leakage current, IL < 0.5 (Pulldown source current) 5 A Low Dropout Regulator C CCC Output Capacitance on card power supply CCC (Note 6) F CCC Output Card Supply oltage (including ripple).8 CCC ICC 70 ma 3.0 CCC ICC 70 ma 5.0 CCC ICC 70 ma with.85 DDP 5.5 (NDS) 5.0 CCC ICC 70 ma with.75 DDP 5.5 (EM) CCC Current pulses 5 nas (t < 00 ns & I CC < 00 ma peak) (Note 5).8 mode / Ripple 50 m (.7 DDP 5.5 ) Current pulses 0 nas (t < 00 ns & I CC < 00 ma peak) 3.0 mode / Ripple 50 m (.9 DDP 5.5 ) Current pulses 0 nas (t < 00 ns & I CC < 00 ma peak) 5.0 mode / Ripple 50 m (.85 DDP 5.5 ) I CCC Card Supply CCC CCC = CCC = 5.0 I CCC_SC Short Circuit Current CCC shorted to ground 0 50 ma CCC Output Card Supply oltage Ripple peaktopeak f ripple = 00 Hz to 00 MHz (load transient frequency with 65 ma peak current and 50% Duty Cycle) (Note 5) ma 300 m CCC SR Slew Rate on CCC turnon / turnoff (Note 5) 0. / s 5. Guaranteed by design and characterization. 6. These values take into account the tolerance of the cms capacitor used. CMS capacitor very low ESR (< 00 m, X5R / X7R). 6

7 HOST INTERFACE SECTION CLKIN, RSTIN, I/Ouc, AUXuc, AUXuc, CLKDI, CLKDI, CMDCC, SEL0, SEL ( DD = 3.3 ; DDP = 5 ; T amb = 5 C; F CLKIN = 0 MHz) Symbol Rating Min Typ Max Unit F CLKIN Clock frequency on pin CLKIN (Note 7) 7 MHz IL IH Input oltage level Low: CLKIN, RSTIN, CLKDI, CLKDI, CMDCC, SEL0, SEL Input oltage level High: CLKIN, RSTIN, CLKDI, CLKDI, CMDCC, SEL0, SEL x DD 0.7 x DD DD I IL CLKDI, CLKDI, CMDCC, RSTIN, CLKIN, SEL0, SEL Low Level Input Leakage Current, IL = 0 A I IH CLKDI, CLKDI, CMDCC, RSTIN, CLKIN, SEL0, SEL Low Level Input Leakage Current, IH = DD A IL Input oltage level Low: I/Ouc, AUXuc, AUXuc IH Input oltage level High: I/Ouc, AUXuc, AUXuc 0.7 x DD DD I IL I/Ouc, AUXuc, AUXuc Low level input leakage current, IL = A I IH I/Ouc, AUXuc, AUXuc High level input leakage current, IH = DD 0 A OH I/Ouc, AUXuc, AUXuc data Cs 30 pf High Level Output oltage (CRD_I/O = CAUX = CAUX = CCC) I OH = 0 A for DD > (I OH = 0 A for DD ) 0.75 x DD DD + 0. OL Low Level Output oltage (CRD_I/O = CAUX = CAUX = 0 ) I OL = + ma t Ri/Fi Input Rising/Falling times (Note 7). s t Ro/Fo Output Rising/Falling times (Note 7) 0. s R pu I/0uc, AUXuc, AUXuc Pull Up Resistor 8 6 k OH OL Output High oltage I OH = 5 A (source) 0.75 x DD Output Low oltage I OL = ma (sink) R INT INT Pull Up Resistor (opendrain output configuration option) (Note 8) k 7. Guaranteed by design and characterization. 8. Option available under request (metal change). The current option is an inverterlike output. 7

8 SMART CARD INTERFACE SECTION CI/O, CAUX, CAUX, CCLK, CRST,, ( DD = 3.3 ; DDP = 5 ; T amb = 5 C; F CLKIN = 0 MHz) Symbol Rating Min Typ Max Unit OH OL CCC =.8, 3.0, 5.0 Output RESET I rst = 00 A Output RESET I rst = 00 A 0.9 x CCC 0 CCC 0.0 t R tf t R/F Output RESET Rise C out = 00 pf (Note 9) Output RESET Fall C out = 00 pf (Note 9) Output Rise/Fall CCC =.8 & C out = 00 pf (Note 9) ns ns ns td RSTIN to CRST delay Reset enabled (Note 9) s CCC =.8, 3.0 or 5.0 F CRDCLK Output Frequency (Note 9) 7 MHz OH OL Output CCLK I clk = 00 A Output CCLK I clk = 00 A 0.9 x CCC 0 CCC +0. F DC Output Duty Cycle (Note 9) 5 55 % t rills t ulsa Rise & Fall time Output CCLK Rise C out = 33 pf (Note 9) Output CCLK Fall C out = 33 pf (Note 9) 6 6 ns ns SR Slew C out = 33 pf (CCC = 3.0 or 5.0 ) (Note 9) 0. /ns CAUX, CAUX, CCC =.8, 3.0, 5.0 IH Input oltage High Level.8 Mode 3.0 Mode 5.0 Mode..6.3 CCC CCC CCC IL Input oltage Low Level.8 mode 3.0 and 5.0 modes I IL I IH Low Level Input current IL = 0 High Level Input current IH = CCC A A OH Output OH@ IOH = 0 A for CCC = 3.0 and I OH = 0 A for CCC = x CCC 0.75 x CCC CCC + 0. CCC + 0. OL Output OL@ IOL = ma, IL = t Ri / Fi Input Rising/Falling times (Note 9). s t Ro / Fo Output Rising/Falling times / C out = 80 pf (Note 9) F bidi Maximum data rate through bidirectional I/O, AUX & AUX channels (Note 9) MHz R PU CAUX, CAUX, CI/O Pull Up Resistor 8 6 k t IO Propagation delay IOuc > CI/O and CI/O > IOuc (falling edge) (Note 9) 00 ns tpu Active pullup pulse width buffers I/O, AUX and AUX (Note 9) 00 ns C in Input Capacitance on data channels 0 pf IH IL I IH I IL, Card Presence oltage High Level Card Presence oltage Low Level, High level input leakage current, IH = DD Low level input leakage current, IL = x DD DD x DD 0 0 s A 8

9 SMART CARD INTERFACE SECTION CI/O, CAUX, CAUX, CCLK, CRST,, ( DD = 3.3 ; DDP = 5 ; T amb = 5 C; F CLKIN = 0 MHz) Symbol Rating T debounce Debounce time and (Note 9) 5 8 ms I CI/O CI/O, CAUX, CAUX current limitation 5 ma I CCLK CCLK current limitation 70 ma I CRST CRST current limitation 0 ma T act Activation Time (Note 9) s T deact Deactivation Time (Note 9) s Temp SD Shutdown temperature (Note 9) 50 C 9. Guaranteed by design and characterization. Min Typ Max Unit POWER SUPPLY The NCN805 / NCN805A smart card interface has two power supplies: DD and DDP. DD is common to the system controller and the interface. The applied DD range can go from.7 up to 5.5. If DD goes below.30 typical (ULO DD ) a powerdown sequence is automatically performed. In that case the interrupt (INT) pin is set Low. A Low DropOut (LDO) and low noise regulator is used to provide the.8, 3 or 5 power supply voltage (CCC) to the card. DDP is the LDO s input voltage. CCC is the LDO output. The typical distributed reservoir output capacitor connected to CCC is 00 nf + 0 nf. The capacitor of 00 nf is connected as close as possible to the CCC s pin and the 0 nf one as close as possible to the card connector C pin. Both feature very low ESR values (lower than 50 m ). The decoupling capacitors on DD and DDP respectively 00 nf and 0 F + 00 nf have also to be connected close to the respective IC pins. The CCC pin can source up to 70 ma at.8, 3 and 5 continuously over the DDP range (see corresponding specification table), the absolute maximum current being internally limited below 50 ma (Typical at 0 ma). The card CC voltage (CCC) can be programmed with the pins SEL0 and SEL and according to the below table: Table. CCC PROGRAMMING SEL0 SEL CCC SEL0 can be used to select the CCC programming mode which can be 5/3 (SEL0 connected to Ground) or.8/3 (SEL0 connected to DD ). SEL0 and SEL are usually programmed before activating the smart card interface that is when /CMDCC is High. There s no specific sequence for applying DD or DDP. They can be applied to the interface in any sequence. After powering the device INT pin remains Low until a card is inserted. SUPPLY OLTAGE MONITORING The supply voltage monitoring block includes the PowerOn Reset (POR) circuitry and the undervoltage lockout (ULO) detection ( DD voltage dropout detection). PORADJ pin allows the user, according to the considered application, to adjust the DD ULO threshold. If not used PORADJ pin is connected to Ground (recommended even if it may be left unconnected). The input supply voltage is continuously monitored to prevent under voltage operation. At power up, the system initializes the internal logic during POR timing and no further signal can be provided or supported during this period. The system is ready to operate when the input voltage has reached the minimum DD. Considering this, the NCN805 / NCN805A will detect an Underoltage situation when the input supply voltage will drop below.30 typical. When DD goes down below the ULO falling threshold a deactivation sequence is performed. The device is inactive during poweron and poweroff of the DD supply (8 ms reset pulse). PORADJ pin is used to modify the ULO threshold according to the below relationship considering an external resistor divider R / R (see block diagram Figure ): R R ULO R POR (eq. ) If PORADJ is connected to Ground the DD ULO threshold ( DD falling) is typically.30. In some cases it can be interesting to adjust this threshold at a higher value and by the way increase the DD supply dropout detection level which enables a deactivation sequence if the DD voltage is too low. For example, there are microcontrollers for which the minimum supply voltage insuring a correct operating is higher than.6 ; increasing ULO DD ( DD falling) is consequently necessary. Considering for instance a resistor bridge with R = 56 k, R = k and POR =.7 typical the DD dropout detection level can be increased up to: 56k k ULO k POR.96 (eq. ) 9

10 CLOCK DIIDER: The input clock can be divided by /, /, /, or /8, depending upon the specific application, prior to be applied to the smart card driver. These division ratios are programmed using pins CLKDI and CLKDI (see Table ). The input clock is provided externally to pin CLKIN. Table. CLOCK FREQUENCY PROGRAMMING CLKDI CLKDI F CCLK 0 0 CLKIN / 8 0 CKLKIN / 0 CLKIN CLKIN / The clock input stage (CLKIN) can handle a 7 MHz maximum frequency signal. Of course, the ratio must be defined by the user to cope with Smart Card considered in a given application In order to avoid any duty cycle out of the 5% / 55% range specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio /, / or /8. On the other hand, the output signal Duty Cycle cannot be guaranteed 50% if the division ratio is and if the input Duty Cycle signal is not within the 6% 56% range at the CLKIN input. When the signal applied to CLKIN is coming from the external controller, the clock will be applied to the card under the control of the microcontroller or similar device after the activation sequence has been completed. DATA I/O, AUX and AUX LEEL SHIFTERS The three bidirectional level shifters I/O, AUX and AUX adapt the voltage difference that might exist between the microcontroller and the smart card. These three channels are identical. The first side of the bidirectional level shifter dropping Low (falling edge) becomes the driver side until the level shifter enters again in the idle state pulling High CI/O and I/Ouc. Passive k pullup resistors have been internally integrated on each terminal of the bidirectional channel. In addition with these pullup resistors, an active pullup circuit provides a fast charge of the stray capacitance. The current to and from the card I/O lines is limited internally to 5 ma and the maximum guaranteed frequency on these lines is MHz. STANDBY MODE After a Poweron reset, the circuit enters the standby mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: All card contacts are inactive Pins I/Ouc, AUXuc and AUXuc are in the highimpedance state ( k pullup resistor to DD ) Card pins are inactive and pulled Low Supply oltage monitoring is active POWERUP In the standby mode the microcontroller can check the presence of a card using the signals INT and CMDCC as shown in Table 3: Table 3. CARD ENCE STATE INT CMDCC State HIGH HIGH Card present LOW HIGH Card not present If a card is detected present ( or active) the controller can start a card session by pulling CMDCC Low. Card activation is run (t0, Figure 6). This PowerUp Sequence makes sure all the card related signals are LOW during the CCC positive going slope. These lines are validated when CCC is stable and above the minimum voltage specified. When the CCC voltage reaches the programmed value (.8, 3.0 or 5.0 ), the circuit activates the card signals according to the following sequence (Figure 6): CCC is poweredup at its nominal value (t) I/O, AUX and AUX lines are activated (t) Then Clock is activated and the clock signal is applied to the card (typically 500 ns after I/Os lines) (t3) Finally the Reset level shifter is enabled (typically 500 ns after clock channel) (t) The clock can also be applied to the card using a RSTIN mode allowing controlling the clock starting by setting RSTIN Low (Figure 5). Before running the activation sequence, that is before setting Low CMDCC RSTIN is set High. The following sequence is applied: The Smart Card Interface is enable by setting CMDCC LOW (RSTIN is High). Between t (Figure 5) and t5 = 00 s, RSTIN is reset to LOW and CCLK will start precisely at this moment allowing a precise count of clock cycles before toggling CRST Low to High for ATR (Answer To Reset) request. CRST remains LOW until 00 s; after t5 = 00 s CRST is enabled and is the copy of RSTIN which has no more control on the clock. If controlling the clock with RSTIN is not necessary (Normal Mode), then CMDCC can be set LOW with RSTIN LOW. In that case, CLK will start minimum 500 ns after the transition on I/O (Figure 6), and to obtain an ATR, CRST can be set High by RSTIN also about 500 ns after the clock channel activation (T act ). The internal activation sequence activates the different channels according to a specific hardware builtin sequencing internally defined but at the end the actual activation sequencing is the responsibility of the application software and can be redefined by the microcontroller to comply with the different standards and the different ways the standards manage this activation (for example light differences exist between the EM and the ISO786 standards). 0

11 CMDCC CCC CIO ATR CCLK RSTIN CRST t0 t t t t5 ~00 s Figure 5. Activation Sequence RSTIN Mode (RSTIN Starting High) CMDCC CCC CIO ATR CCLK RSTIN CRST t0 t t t3 t T act Figure 6. Activation Sequence Normal Mode

12 POWERDOWN When the communication session is completed the NCN805 / NCN805A runs a deactivation sequence by setting High CMDCC. The below power down sequence is executed: CRST is forced to Low CCLK is set Low s after CRST. CI/O, CAUX and CAUX are pulled Low Finally CCC supply can be shutoff. CMDCC CRST CCLK CIO CCC T deact Figure 7. Deactivation Sequence FAULT DETECTION In order to protect both the interface and the external smart card, the NCN805 / NCN805A provides security features to prevent failures or damages as depicted here after. Card extraction detection DD under voltage detection Shortcircuit or overload on CCC DC/DC operation: the internal circuit continuously senses the CCC voltage (in the case of either over or under voltage situation). DC/DC operation: undervoltage detection on DDP Overheating Card pin current limitation: in the case of a short circuit to ground. No feedback is provided to the external MPU. /INT CMDCC debounce debounce CCC Powerdown resulting of card extraction Powerdown caused by shortcircuit Figure 8. Fault Detection and Interrupt Management Interrupt Pin Management: A card session is opened by toggling CMDCC High to Low. Before a card session, CMDCC is supposed to be in a High position. INT is Low if no card is present in the card connector (Normally open or normally closed type). INT is High if a card is present. If a card is inserted (INT = High) and if DD drops below the ULO threshold then INT pin drops Low immediately. It switches High when DD increases again over the ULO limit (including hysteresis), a card being still present. During a card session, CMDCC is Low and INT pin goes Low when a fault is detected. In that case a deactivation is immediately and automatically performed (see Figure 7). When the microcontroller resets CMDCC to High it can sense the INT level again after having got completed the deactivation.

13 As illustrated by Figure 8 the device has a debounce timer of 8 ms typical duration. When a card is inserted, output INT goes High only at the end of the debounce time. When the card is removed a deactivation sequence is automatically and immediately performed and INT goes Low. ESD PROTECTION The NCN805 / NCN805A includes devices to protect the pins against the ESD spike voltages. To cope with the different ESD voltages developed across these pins, the built NCN805 / NCN805A APPLICATION SCHEMATIC in structures have been designed to handle either k, when related to the micro controller side, or 8 k when connected with the external contacts (HBM model). Practically, the CRST, CCLK, CI/O, CAUX, CAUX, and pins can sustain 8 k. The CCC pin has the same ESD protection and can source up to 70 ma continuously, the absolute maximum current being internally limited with a max at 50 ma. The CCC current limit depends on DDP and CCC. DD nf XTAL XTAL SEL CLKDI CLKDI AUXuc AUXuc I/Ouc DD +3.3 DDP nf + 0 F SEL0 DDP 3 Exposed Pad 5 CI/O 5 CAUX CAUX CCLK CRST CCC CMDCC 8 CLKIN INT 7 6 DD 5 RSTIN PORADJ 3 00 nf Optional R/R resistor divider if not used it is recommended to connect PORADJ to Ground R R 3.3 Microcontroller 0 nf 3 CC RST CLK C PP I/O C nf DET Normally Open SMART CARD ORDERING INFORMATION NCN805AMNTXG NCN805MTTBG Figure 9. Application Schematic Device Package Shipping QFN (PbFree) QFN6 (PbFree) 3000 / Tape & Reel 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 3

14 PACKAGE DIMENSIONS QFN, x, 0.5P CASE 85L0 ISSUE A PIN IDENTIFICATION D A B E NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.5M, 99.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.30 MM FROM TERMINAL.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. X SEATING PLANE 0.5 C X 0.5 C 0.0 C 0.08 C A A A3 REF A C MILLIMETERS DIM MIN MAX A A A A3 0.0 REF b D.00 BSC D E.00 BSC E e 0.50 BSC L L 7 D e 6 3 E X b 0.0 C A B 0.05 C 9 8 e

15 PACKAGE DIMENSIONS QFN6, 3x3, 0.5 P CASE 88AK ISSUE O PIN LOCATION 0.5 C 0.0 C 0.5 C D ÇÇÇ ÇÇÇ TOP IEW (A3) A B E A NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.5M, 99.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.30 MM FROM TERMINAL.. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. L max CONDITION CAN NOT IOLATE 0. MM SPACING BETWEEN LEAD TIP AND FLAG. MILLIMETERS DIM MIN MAX A A A3 0.0 REF b D 3.00 BSC D E 3.00 BSC E e 0.50 BSC K 0.0 L X 0.08 C SIDE IEW A C SEATING PLANE D 6X L NOTE e EXPOSED PAD 9 6X K E 0.0 C 0.05 C 6X b A B NOTE BOTTOM IEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada [email protected] N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCN805/D