DESIGN AND IMPLEMENTATION OF FPGA BASED G CODE COMPATIBLE CNC LATHE CONTROLLER

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1 International Journal of Electronics and Communication Engineering & Technology (IJECET) Volume, Issue, Jan-Feb, pp. -, Article ID: IJECET Available online at Journal Impact Factor ():. (Calculated by GISI) ISSN Print: - and ISSN Online: - IAEME Publication DESIGN AND IMPLEMENTATION OF FPGA BASED G CODE COMPATIBLE CNC LATHE CONTROLLER Mufaddal A. Saifee M.Tech. by Research Student, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India Dr. Usha S. Mehta Associate Professor, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India ABSTRACT The conventional machining done in the past like lathe and milling operations were done manually. Accuracy and consistency between two produced parts vary tremendously due to human errors and limitations. With the advent of processor and controllers, came the Computerized Numerically Controlled (CNC) machines, having the advantage of using universally accepted G code machining language to machine the parts. It became really easy to produce the parts with same accuracies and consistency on different machines with the same G code being used. G codes are CNC machine assembly language having various Interpolation Instructions G codes, Tool Instruction T codes, Feed-rate Instruction F codes, Principal Axis Speed Instruction S codes and various Controlling and Input - Output Instructions M codes. G code based CNC systems available till date, are implemented using controllers and processors using software interpolation. Software implementation of complex interpolation algorithms by serial pipelined processors is time consuming, difficult and impractical for real time applications. Thus the efficient, real time complex computation approach is only feasible with hardware logic circuits like FPGA or ASIC having parallel and low power processing architectures. In the presented work, for the first time a G code based, CNC Lathe controller is designed and implemented in a FPGA. It is implemented and validated on Xilinx Artix, atcsg- FPGA based kit, with its heart being a stage Multi InstructionMulti Data (MIMD) Complex Instruction Set computers (CISC) G code processor. The Rapid Positioning Controller, Linear Interpolation Controller and Circular Interpolation Controller are also designed as a co-processor for the G editor@iaeme.com

2 Mufaddal A. Saifee and Dr. Usha S. Mehta processor to perform rapid positioning (G), linear d (G) and circular d arc clockwise (G) and anticlockwise (G) interpolated movements respectively of the CNC Lathe machine. The simulation and hardware results of the integrated CNC controller with its central CISC G code Processor and its interpolation controllers shows the efficient and precise operation for the CNC Lathe machines. Implemented CNC lathe Controller was able to achieve the maximum frequency of. MHz while utilizing LUTs and Flip Flops of Artix FPGA, proving it to be performance and hardware efficient. Keywords: CNC, D Linear Interpolation, D Circular Interpolation, FPGA, CISC Processor, MIMD Processor. Cite this Article: Mufaddal A. Saifee and Dr. Usha S. Mehta. Design and Implementation of FPGA Based G Compatible CNC Lathe Controller. International Journal of Electronics and Communication Engineering & Technology, (),, pp INTRODUCTION The conventional machining done in the past like lathe and milling operations were done manually. With the advent of processor and controllers, came the CNC machines, with the advantage of using universally accepted G code machining language to machine the parts. It became really easy to produce the parts with same accuracies and consistency on different machines with the same G code being used. The Heart of Industrial Automation Devices like CNC Machines are Motion Controllers, which sequentially executes G codes to machine the parts. Motion controllers control the motion conveyed through G code in a predetermined direction through motors. The circular motion of the motor is translated to the CNC tool linearly in small steps. A motor each is required for motion in one particular axis. Therefore, for a D motion, the tool is controlled by providing varying rate of pulses to each of the three motors, corresponding to an axis. The controlled motion (line/arc) along the required path trajectory is achieved through various interpolation algorithms run in D or D space, which are responsible for providing varying rate of pulses to corresponding axis. Till date available CNC systems are implemented using controllers and processors. These processors implement CNC motions using software interpolation. Most of the interpolation algorithm uses complex parametric function like sine and cosine for necessary calculations. Software implementation of such algorithms by serial pipelined processors is time consuming and as well as difficult and impractical for real time applications. As employment with single CPU in traditional control system, the CPU is busy with kinds of tasks; in this case, the high requirement for real time in interpolation is impractical and difficult. Thus the efficient, real time complex computation approach is only feasible with hardware logic circuits like FPGA or ASIC having parallel and lower power processing architectures. As compared to ASIC, FPGAs have lower time to market and simpler design cycle making it an excellent solution for the implementation of motion controllers. The FPGA-based implementation of control algorithm offers advantages such as high speed computation, complex functionality and real-time processing capabilities. Takahashi and Goetz presented the design and implementation of FPGA based high- editor@iaeme.com

3 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller performance ac servo system. A new motion control hardware architecture was presented by Shao etal. where FPGA was used for position and velocity control, and for dynamic compensation, inverse kinematics, and trajectory generation a DSP was utilized. The design and implementation of a motor control IC for the permanent magnet ac (PMAC) servo was presented by Tzou and Kuo. For system initialization and parameter setting DSP was used. Oldknow and Yellowley presented FPGA based -D dynamic interpolation motion controller and proved the implementation on a two axis test stand. Park and Oh presented the hardware realization of straight line interpolation using inverse kinematics for robot manipulators. An FPGA-based motion controller was developed by Yau et al. in order to realize the real-time nonuniform rational B-spline (NURBS) interpolator and CNC controller in an FPGA. The NURBS interpolation algorithm and the infinite impulse response filter algorithm were implemented to control an XY table using an FPGA-based motion controller. Kung et al. used a soft-core embedded processor to perform motion trajectory and position control of a servo control IC for the XY table. Chan et al. used distributed arithmetic (DA) to implement a PID controller. This DA-based PID controller offers the advantage of optimal resource utilization and power consumption when implemented in an FPGA. In the research listed to date, FPGAs were used to realize only the logic circuits of motion control systems or particular functions of the motion control systems such as interpolation, velocity profile generator, PID controller, and inverse kinematics calculator. Moreover the controllers implemented were propriety and none targeted the universally accepted G code base motion controller implementation. The work presented over here implements a FPGA based G code - motion controller, which implements all the G codes required for a Lathe operations. To achieve this stage Multi Instruction Multi Data (MIMD) Complex Instruction Set computers (CISC) G code processor is designed and implemented. It is capable of executing Interpolation Instructions G codes, Tool Instruction T codes, Feed-rate Instruction F codes, Principal Axis Speed Instruction S codes and various Controlling and Input - Output Instructions M codes, required for controlling a Lathe Machine. To support various G codes conveying the interpolated motion of the tool for machining, Linear Interpolation, Circular Interpolation and Rapid Positioning Controllers are implemented as co-processors to the G code processor. G codes are written to the Block Ram of the FPGA through UART, for which a UART controller is implemented. G code Processor fetches the G codes sequentially from the Block Ram and executes the machining operations. For G codes requiring the linear, circular or rapid interpolation movements, the G code processor communicates the coordinates to the respective co-processors which then does the corresponding machining operations. Thus the hardware interpolation performed by the respective co-processors - controllers highly improves the motion controller performance. The proposed motion controller is implemented using Verilog HDL in Xilinx Artix FPGA. Simulation is performed using Modelsim. simulator and hardware is implemented using Xilinx ISE. in Digilent Nexus Artix FPGA based board. Hardware results are validated using Xilinx ChipScope Pro on chip debugging tool. The paper is organized as follows: Section briefs the proposed CNC Lathe Controller, Section explains implementation of CNC Motion Controller, briefs the Proposed FPGA based CNC Lathe Controller, its heart Application Specific G Processor, its different co-processor interpolation controllers. It also explains implementation and verification of Application Specific G CISC processor with editor@iaeme.com

4 Mufaddal A. Saifee and Dr. Usha S. Mehta its G, M, T, F and S codes instructions. and Section describes Synthesis, Simulation and Hardware results. Conclusions are detailed in Section.. PROPOSED CNC LATHE CONTROLLER Proposed FPGA-based G code compatible, -axis motion controller will be capable of controlling axes of either stepper motor or pulse type servo drivers for position, speed, and interpolation controls. The overall structure of the proposed CNC controller is modularized with different functional modules as shown in figure below... UART UART (Universal Asynchronous Receiver Transmitter) is used for asynchronous serial data communication to configure the G code Processor and its instruction memory. It s a generic UART supporting all baud rates. Our design uses the baud rate. A moving average low pass filter is used to remove noise samples from data samples at receiver. Reference gives more detail on the implementation... UART Register Interface UART Register Interface appropriately interprets and writes data to the bit displacement coefficient registers. These registers provide data like displacement coefficients in X, Y and Z axes for the respective servo drives. UART Register Interface writes the bit G instructions for the ASSP G code processor in a bit x Block RAM. The heart of the UART Register Interface is the Finite State Machine (FSM) which has states and controls the configuring of above registers and RAM. The states are ) Idle, ) reg write and ) RAM write. Start lin Done lin Feedrate, displacement coefficient, axis parameters Linear Interpolation Direction_ axis Pulses_ axis Pulse_x Start cir Done cir Feedrate, displacement coefficient, axis parameters Cicular Interpolation Direction_ axis Pulses_ axis Mux Pulse_z Tx Rx UART Start rapid Done rapid Feedrate, displacement coefficient, axis parameters Rapid Positioning Direction_ axis Pulses_ axis Direction_x wr Sbuf_out(:) Tx_int Rx_int Sbuf_in(:) Direction_z Interpolation_selection UART reg interface Application Specific G Processor Principal axis parameters Principal axis control Pulse_spindle wr Instr (:) Tool offset bits Direction_spindle RAM Cycle_start Instruction_valid Instruction Address Address valid rd instr ( bit) Tool No bits Coolant on Coolant off Lubricant on Lubricant off Tailstock forward Tailstock backward Principle axis forward rotation Principle axis backward rotation Principle axis stop Chuck clamped Chuck released programmable outputs programmable inputs programmable inputs alarm Figure CNC Controller Block Diagram editor@iaeme.com

5 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller.. RAM RAM used is a simple dual port RAM with one side read only and other write only. It's a bit width and deep synchronous block RAM of Artix FPGA. It is used to hold instructions. Instructions are written in RAM by UART register interface through UART, while they are read by G code processor. G code processor fetches the next bunch after it has positioned the two servo motors according to the instruction fetched previously... Linear Interpolation It performs the linear interpolation algorithm, to cause the tool to cut in straight line from current position to the specified end point. It is called by G code processor for G, G and G G codes processing. Reference gives more detail on the implementation... Circular Interpolation It performs the Circular interpolation algorithm, to cause the tool to cut in circular arc from current position to the specified end point with the provided radius. It is called by G code processor for G and G G codes processing. Reference gives more detail on the implementation... Rapid Positioning It performs the rapid positioning to cause the tool to move at maximum speed from current position to the specified end point. It is called by G code processor for G, G, G and G G codes processing. Implementation similar to Linear interpolation... Principal axis Control Depending on the S code parameters used in G and G G codes, it controls the speed of the principal axis rotation... Application Specific G code Processor It is the heart of the CNC controller. It is a stage pipelined bit application specific CISC processor. It fetches the instruction from the RAM, decodes them and accordingly either controls the outputs, or provides data to various interpolation modules to drive the servo motors according to the interpolated motion required. It then waits for the interpolated motion to get completed after which it fetches the next instruction.. G CODE PROCESSOR Application G code processor is designed to support the G, M, S and T codes used in a standard lathe machines. It is a - bit, stage pipeline, CISC (Complex Instruction Set Computers) processor. It is implemented on Xilinx Artix FPGA. Its basic features are: - bit Program Counter. bit Instruction Register. Four stage pipeline architecture: editor@iaeme.com

6 Mufaddal A. Saifee and Dr. Usha S. Mehta Instruction Fetch: bit instructions are fetched from the external memory in this stage. Instruction Decode: Fetched instruction is accordingly decoded into M, T or G code Execute: Instructions depending on their type are executed in single clock or multiple clock. Current position update: If the instructions are any of the G code interpolation or M code program end then depending on the motion executed the current position is updated... G Processor Block Diagram reset X D clk clr Q Program Counter Instruction register(:) Adder bit Sig_Program Counter PC mux branch_taken branch_taken Immed_data(:) Current position Instruction Fetch Coolant on Coolant off Lubricant on Lubricant off Tailstock forward Pricipal axis rotation/ min calculation Start lin Feedrate, displacement coefficient, axis parameters Start cir Feedrate, displacement coefficient, axis parameters Start rapid Tailstock backward Principle axis forward rotation Principle axis backward rotation Principle axis stop Chuck clamped Chuck released Feedrate mm/min calculation Instruction Decoder Non_restoring_divider Feedrate, displacement coefficient, axis parameters Interpolation_selection Instruction Decode programmable outputs Principal axis parameters opcode ` Timer paramet ers Pipeline Registers Wait complete operation Instruction Execute Current position register update Instruction write back Timer Current position Timer_up Done lin programmable inputs programmable inputs alarm Cycle start opcode Done cir Done rapid done Figure G Processor Block Diagram Block diagram of stage pipeline G code processor is shown in figure. Program counter is incremented and given out to the external ram, which then returns with the instruction back. Instruction is then decoded. Axis parameters, feedrate, coordinates are decoded and given out to external interpolation modules to do the machining. Once they are finished with the machining process they send a done signal. Processor editor@iaeme.com

7 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller waits for the done signals and accordingly updates the current position register. The program counter increments by to fetch the next instruction. If there is block change instruction, it is decoded in the instruction decode stage and accordingly instruction is fetched from the next decoded address. For the M codes depending on whether they are control instructions or programmable input output instructions they are executed in single or multiple clock cycles. Tool selection and offset instruction is executed in single clock... G Instructions Supported Table G s Supported No Instruction Function M codes M Program Pauses M Program Ends M Subroutine calling M Return from subroutine M Principal axis forward direction M Principal axis backward direction M Principal axis stop M Coolant on M Coolant off M Tailstock forward M Tailstock backward M Chuck clamped M Chuck released M Lubricant on M Lubricant off M Check the signal of specified input pin M Control the switch of specified output pin T T Tool change and its offset set G G Fast moving / rapid interpolation G Linear interpolation G Arc interpolation clockwise G Arc interpolation anticlockwise G Pause, Quasi Stop G Return to mechanical home G Thread cutting G Z axis taping cycle G Maximum Principal axis rotation speed G Axial cutting cycle G Thread cutting cycle G Radial cutting cycle G Principal axis rotation speed m/min G Principal axis rotation speed r/min G Feedrate mm/min G Feedrate mm/r editor@iaeme.com

8 Mufaddal A. Saifee and Dr. Usha S. Mehta.. Instructions Formats... M////////////... code M - M- No.... M.. M M- No. Input Port Address Input To Wait For Q Millisecond For Waiting... M.. code M M- No. Output Port Address Output... M.. M M- No. Repeat Subroutine Subroutine Address... M.. M M- No. P code Subroutine Address... T... code T - Tool Number Tool Offset editor@iaeme.com

9 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller editor@iaeme.com... G/.. code G G- No. / G - Principal Axis In Rotation/min G - Principal Axis Max Allowed In Rotation/min... G/.. code G G- No. / G - Feedrate in mm/min G - Feedrate in mm/r => prin axis r/min x given mm/r = mm/min... G.. code G G- No. Timer.. G/... G G- No. / x/u code z/w... G G G- No. x/u code z/w f F... G///... Cod e G G- No. /// x/u code z/w R... f... F

10 Mufaddal A. Saifee and Dr. Usha S. Mehta. RESULTS.. Synthesis Report - Device utilization summary: Selected Device: atcsg- Slice Logic Utilization: Number of Slice Registers: out of % Number of Slice LUTs: out of % Number used as Logic: out of % IO Utilization: Number of bonded IOBs: out of % Specific Feature Utilization: Number of Block RAM/FIFO: out of % Number of BUFG/BUFGCTRLs: out of % Number of DSPAs: out of %.. Simulation Results... M Test Case M - Principal axis forward direction M - Pause Figure M Waveform... G Test Case G Feedrate mm/min G X Z Linear interpolation to coordinates, with above feedrate G X Z F Linear interpolation to coordinates, with feedrate M Pause editor@iaeme.com

11 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller Figure G Waveform.. Hardware Setup The Hardware setup shown in figure consists of Artix FPGA based Digilent Nexus kit, JTAG cable, UART cable, Power cable and a PC having Xilinx. ISE and Chipscope Analyzer installed. The various G codes are dumped into FPGA block RAM memory. The processor on getting enable signal from the enable switch on kit, starts fetching and executing M, T and G instructions. The in chip FPGA signals are viewed and verified for each instructions using Chipscope analyzer. Figure Hardware Setup editor@iaeme.com

12 Mufaddal A. Saifee and Dr. Usha S. Mehta.. Hardware Results... T - Tool Change and its Offset Set Figure T - Tool change and its offset set... M - Check the Signal of Specified Input Pin Figure M -Check the signal of specified input pin editor@iaeme.com

13 Design and Implementation of FPGA Based G Compatible CNC Lathe Controller... G - Radial Cutting Cycle Figure G - Radial Cutting Cycle. CONCLUSION A G based motion controller was implemented to control a multiple-axis motion system for a CNC Lathe machine for the first time in FPGA, with its heart being a stage Multi Instruction Multi Data (MIMD) Complex Instruction Set computers (CISC) G code processor. The G Processor supports most of the G codes, M codes, T code, F code and S code required for performing Lathe machining operation. It was designed using Verilog and implemented on Xilinx Artix, atcsg- FPGA. It consumed, input LUTs and Flip Flops and was able to achieve maximum frequency of. MHz. The feasibility to realize reconfigurable G code based CNC system within FPGA were validated. Simulation results show the precision and performance to be excellent. Synthesis report also shows it to be hardware efficient by consuming fewer Flip Fops and LUTS. Excellent real time operation, good precision and optimum hardware resources makes the FPGA-based CNC Lathe controller have excellent performance and useful for any motion controller for CNC machines. editor@iaeme.com

14 Mufaddal A. Saifee and Dr. Usha S. Mehta REFERENCES [] Weihai Chen, Zhaojin Wen, ZhiyueXu and Jingmeng Liu, Implementation of - axis Linear Interpolation in a FPGA-based -axis Motion Controller. [] Mufaddal A. Saifee and Dr. Usha S. Mehta, Design and Implementation of Axis Linear Interpolation Controller in FPGA for CNC Machines and Robotics, International Journal of Advanced Research in Engineering and Technology, Volume, Issue, Sept, pp. - [] Mufaddal A. Saifee and Dr. Usha S. Mehta, Design and Implementation of - Axis Circular Interpolation Controller in Field Programmable Gate Array (FPGA) for Computer Numerical Control (CNC) Machines and Robotics, International Journal of Computer Applications ():-, November [] Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty, A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance, Conference Proceedings: th VLSI Design - th Embedded Systems, The Institute of Electrical and Electronics Engineers, Inc. January, pp -. [] K Goldberg, and M Goldberg, XY interpolation algorithms, ROBOTICS AGE, No, May, pp.- [] Z. Zhang, C. W. Peng, and L. G. Yin, Motion Controller Introduction and Application of MCX, Electronics World, No.,, pp. - [] J. L. Liu, W. Liu, and C. Y. Yu, Complete Numeric CNC System and Its Kernel Chip MCX, Electronic Design & Application World,no.,, pp.- [] P. Q.Yue, and J. S. Wang, Motion Controller IC MCX and Numerical Control System Design, Beijing: Beihang University Press.Nov. [] Fengge Li, Jiaxin You and Weiming Tong, A Design of Full-Digital CNC Interface Based on FPGA, International Conference on Information Technology and Computer Science [] G.Prasad and N.Vasantha. Design and Implementation of Multi Channel Frame Synchronization in FPGA. International Journal of Electronics and Communication Engineering & Technology, (),, pp. -. [] Prof. Abhinav v. Deshpande. System Designing and Modelling Using FPGA. International Journal of Electronics and Communication Engineering & Technology, (),, pp. -. [] Devanshi S. Desai and Dr. Nagendra P. Gajjar. Low Bitrate Modulator Using. International Journal of Electronics and Communication Engineering & Technology, (),, pp. -. [] Jung Uk Cho, Quy Ngoc Le, and Jae WookJeon, An FPGA-Based Multiple-Axis Motion Control Chip, IEEE Transactions on Industrial Electronics Vol., No., Mar. [] Xilinx Spartan data sheet from editor@iaeme.com

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