Virtual Memory and Address Translation

Transcription

1 Memry and Address Translatin Review Prgram addresses are virtual addresses. Relative set rgram regins can nt change during rgram executin. E.g., hea can nt mve urther rm cde. addresses == hysical address incnvenient. Prgram lcatin is cmiled int the rgram. A single set register allws the OS t lace a rcess virtual address sace anywhere in hysical memry. address sace must be smaller than hysical. Prgram is swaed ut ld lcatin and swaed int new. Segmentatin creates external ragmentatin and requires large regins cntiguus hysical memry. We lk t ixed sized units, memry ages, t slve the rblem. 2

2 Memry Cncet Key rblem: Hw can ne surt rgrams that require mre memry than is hysically available? Hw can we surt rgrams that d nt use all their memry at nce? Hide hysical size memry rm users Memry is a large virtual address sace 2 n bytes Only rtins VAS are in hysical memry at any ne time (increase memry utilizatin). Issues Placement strategies Where t lace rgrams in hysical memry Relacement strategies What t d when there exist mre rcesses than can it in memry Lad cntrl strategies Determining hw many rcesses can be in memry at ne time 2 n - 0 Prgram P s VAS 3 Realizing Memry Paging ( MAX -, MAX -) memry artitined int equal sized age rames Page rames avid external ragmentatin. A memry address is a air (, ) rame number ( max rames) rame set ( max bytes/rames) address = max + (,) Memry PA: lg 2 ( max max ) lg 2 max (0,0) 4

3 Address Seciicatins Frame/Oset air v. An abslute index Examle: A 6-bit address sace with ( max =) 52 byte age rames Addressing lcatin (3, 6) =,542 (3,6),542 PA: ,542 0 Memry (0,0) 0 5 Questins The set is the same in a virtual address and a hysical address. A. True B. False I yur level data cache is equal t r smaller than 2 number age set bits then address translatin is nt necessary r a data cache tag check. A. True B. False 6

4 Realizing Memry Paging A rcess s virtual address sace is artitined int equal sized ages age = age rame A virtual address is a air (, ) age number ( max ages) age set ( max bytes/ages) address = max + 2 n - = ( MAX -, MAX -) (,) Address Sace VA: lg 2 ( max max ) lg 2 MAX (0,0) 7 Paging Maing virtual addresses t hysical addresses Address Sace Pages ma t rames Pages are cntiguus in a VAS... But ages are arbitrarily lcated in hysical memry, and Nt all ages maed at all times (, ) ( 2, 2 ) (, ) Memry ( 2, 2 ) 8

5 Frames and ages Only maing virtual ages that are in use des what? A. Increases memry utilizatin. B. Increases errmance r user alicatins. C. Allws an OS t run mre rgrams cncurrently. D. Gives the OS reedm t mve virtual ages in the virtual address sace. Address translatin is A. Frequent B. Inrequent Changing address maings is A. Frequent B. Inrequent 9 Paging address translatin Prgram P A age table mas virtual ages t hysical rames (,) CPU P s Address Sace (,) Memry Page Table 0

6 Address Translatin Details Page table structure table er rcess Part rcess s state Cntents: Flags dirty bit, resident bit, clck/reerence bit Frame number CPU PTBR Page Table Address Translatin Details Examle P s Address Sace (4,0) (3,023) CPU A system with 6-bit addresses 32 KB hysical memry 024 byte ages (4,023) 0 Memry Page Table (0,0) 2

7 Address Translatin Perrmance Issues Prblem VM reerence requires 2 memry reerences! One access t get the age table entry One access t get the data Page table can be very large; a art the age table can be n disk. Fr a machine with 64-bit addresses and 024 byte ages, what is the size a age table? What t d? Mst cmuting rblems are slved by sme rm Caching Indirectin 3 Address Translatin Using TLBs t Seedu Address Translatin CPU Cache recently accessed age-t-rame translatins in a TLB Fr TLB hit, hysical age number btained in cycle Fr TLB miss, translatin is udated in TLB Has high hit rati (why?) 6 0 9? Key Value TLB X Page Table 4

8 Dealing With Large Page Tables Multi-level aging Add additinal levels indirectin t the age table by sub-dividing age number int k arts Create a tree age tables TLB still used, just nt shwn The architecture determines the number levels age table Secnd-Level Page Tables 2 2 Address 3 3 First-Level Page Table Third-Level Page Tables 5 Dealing With Large Page Tables Multi-level aging Examle: Tw-level aging CPU Memry PTBR + age table + 2 First-Level Page Table Secnd-Level Page Table 6

9 The Prblem Large Address Saces With large address saces (64-bits) rward maed age tables becme cumbersme. E.g. 5 levels tables. Instead making tables rrtinal t size virtual address sace, make them rrtinal t the size hysical address sace. address sace is grwing aster than hysical. Use ne entry r each hysical age with a hash table Size translatin table ccuies a very small ractin hysical memry Size translatin table is indeendent VM size 7 Address Translatin Using Page Registers (aka Inverted Page Tables) Each rame is assciated with a register cntaining Residence bit: whether r nt the rame is ccuied Occuier: age number the age ccuying rame Prtectin bits Page registers: an examle memry size: 6 MB Page size: 4096 bytes Number rames: 4096 Sace used r age registers (assuming 8 bytes/register): 32 Kbytes Percentage verhead intrduced by age registers: 0.2% Size virtual memry: irrelevant 8

10 Page Registers Hw des a virtual address becme a hysical address? CPU generates virtual addresses, where is the hysical age? Hash the virtual address Must deal with cnlicts TLB caches recent translatins, s age lku can take several stes Hash the address Check the tag the entry Pssibly rehash/traverse list cnlicting entries TLB is limited in size Diicult t make large and accessible in a single cycle. They cnsume a lt wer (27% n-chi r StrngARM) 9 Dealing With Large Inverted Page Tables Using Hash Tables Hash age numbers t ind crresnding rame number Page rame number is nt exlicitly stred ( rame er entry) Prtectin, dirty, used, resident bits als in entry 20 9 CPU Address PID running 6 9 Memry PTBR Hash =? =? tag check + PID age 0 max max 2 h(pid, ) Inverted Page Table 0 20

11 Searching Inverted Page Tables Using Hash Tables Page registers are laced in an array Page i is laced in slt (i) where is an agreed-un hash unctin T lku age i, errm the llwing: Cmute (i) and use it as an index int the table age registers Extract the crresnding age register Check i the register tag cntains i, i s, we have a hit Otherwise, we have a miss 2 Searching the Inverted Page Table Using Hash Tables (Cnt d.) Minr cmlicatin Since the number ages is usually larger than the number slts in a hash table, tw r mre items may hash t the same lcatin Tw dierent entries that ma t same lcatin are said t cllide Many standard techniques r dealing with cllisins Use a linked list items that hash t a articular table entry Rehash index until the key is und r an emty table entry is reached (en hashing) 22

12 Questins Why use inverted age tables? A. Frward maed age tables are t slw. B. Frward maed age tables dn t scale t larger virtual address saces. C. Inverted ages tables have a simler lku algrithm, s the hardware that imlements them is simler. D. Inverted age tables allw a virtual age t be anywhere in hysical memry. 23 Memry (Paging) The bigger icture A rcess s VAS is its cntext Cntains its cde, data, and stack Cde ages are stred in a user s s ile n disk Sme are currently residing in memry; mst are nt Data and stack ages are als stred in a ile Althugh this ile is tyically nt visible t users File nly exists while a rgram is executing OS determines which rtins a rcess s VAS are maed din memry at any ne time Cde Data Stack File System (Disk) OS/MMU Memry 24

13 Memry Page ault handling Memry Reerences t nn-maed ages generate a age ault CPU Page ault handling stes: Prcessr runs the interrut handler OS blcks the running rcess OS starts read the unmaed age OS resumes/initiates sme ther rcess Read age cmletes OS mas the missing age int memry OS restart the aulting rcess 0 Page Table Prgram P s VAS Disk 25 Memry Perrmance Page ault handling analysis T understand the verhead aging, cmute the eective memry access time (EAT) EAT = memry access time rbability a age hit + age ault service time rbability a age ault Examle: Memry access time: 60 ns Disk access time: 25 ms Let = the rbability a age ault EAT = 60( ) ( + 25,000,000, T realize an EAT within 5% minimum, what is the largest value we can tlerate? 26

14 Vista reading rm the ageile 27 Vista writing t the ageile 28

15 Memry Summary and virtual memry artitined int equal size units Size VAS unrelated t size hysical memry ages are maed t hysical rames Simle lacement strategy There is n external ragmentatin Key t gd errmance is minimizing age aults 29 Segmentatin vs. Paging Segmentatin has what advantages ver aging? A. Fine-grained rtectin. B. Easier t manage transer segments t/rm the disk. C. Requires less hardware surt D. N external ragmentatin Paging has what advantages ver segmentatin? A. Fine-grained rtectin. B. Easier t manage transer ages t/rm the disk. C. Requires less hardware surt. D. N external ragmentatin. 30