COSIDE RESEARCH AND SERVICES AT FRAUNHOFER IIS/EAS

Transcription

1 COSIDE RESEARCH AND SERVICES AT FRAUNHOFER IIS/EAS COSIDE User Group Meeting 2014 MEV Verlag Stephan Schulz Group Manager Heterogeneous System Specification Fraunhofer IIS/EAS

2 COSIDE Research and Services at Fraunhofer IIS/EAS Comprehensive support of TIER levels and domains TIER2 TIER1 value chain Source: Wolfgang Scherr Infineon AIM 2

3 Design and Simulation of heterogeneous systems Coverage of different domains 32 MHz / 4 MHz 32 MHz down to 8 khz subscriber/line protection net SLIC prefi adc afe_ac ac PCM codec hook tip kit pofi dac ctrl afe_ iomeas control line voltage ring line drv prefi adc Data flow (SystemC AMS) Linear electric network (SystemC AMS) Digital (SystemC) Linear DAEs (SystemC AMS) afe_dc dac pofi dac 4 MHz down to 2 khz 3

4 Design and Simulation of heterogeneous systems Coverage of different domains 4

5 Import of foreign HDL models into SystemC (AMS) Increasing re-use of existing IP Verified HDL design components in SystemC models enable precision in system level models User-readable SystemC source instead of binary blob Compiled SystemC design originating from e.g. VHDL usable as IP-protected customer model Verilog (AMS), SystemVerilog, VHDL (AMS), Saber/Mast, Modelica, ARCHITECTURE a OF e IS ENTITY e IS BEGIN END e; END; SC_MODULE(e) { }; 5

6 SystemC Virtual Prototyping Higher efficiency through customized domain libraries Development of customer specific libraries for Line models Radio Frequency Mechanics TLM UVM 6

7 SystemC Virtual Prototyping Seamless inclusion in external simulators Support of most commercial simulators available within COSIDE Support of existing work flows Re-use of existing prototyping hardware simulator libraries Customer specific integration of SystemC and SystemC AMS in third party products??? Third party Simulator/Tool 7

8 SystemC Virtual Prototyping Improving confidence with Hardware-in-the-Loop Embedded Software simulation running on HiL-Systems Efficient Hardware-Prototyping without model changes SystemC AMS Model ds1006.x86 Source: dspace 8

9 SystemC Virtual Prototyping Improving confidence with Hardware-in-the-Loop Customer specific FPGA adaption of SystemC and SystemC AMS Early validation of first silicon SystemC AMS Model Zynq.arm Source: D-Kuru/Wikimedia Commons 9

10 SystemC Verification Improving usability of formal verification Research of new approaches to formal verification Accessibility improvements of formal methods to common users Formal verification of customer designs 10

11 SystemC Verification Improving structured verification using UVM Provides mechanism for modular, scalable, configurable, and reusable test benches Enabling structured and well known verification methodologies for ESL designs Migration from directed testing towards Coverage Driven Verification (CDV) Setup of UVM-SystemC environments for customer designs Verification and Validation Methodology UVM-SystemC* TLM SCV SystemC C++ -AMS -AMS SystemC-AMS * UVM-SystemC = UVM implemented in SystemC/C++ 11

12 Standardisation SystemC AMS, VHDL-AMS, Modelica SystemC AMS Extensions of SystemC for modelling analog mixed-signal behaviour Proof-of-Concept simulator developed at EAS VHDL-AMS Frequency Domain Modelling & Table-driven Modelling Contributions to SAE J2748 VHDL-AMS Statistical Analysis Packages Modelica Contributions to language standardisation and standard library Provision of application-oriented trainings 12

13 COSIDE Research and Services at Fraunhofer IIS/EAS Services for our customers Design and simulation of complex heterogeneous systems in all major HDL SystemC (AMS) verification e.g. using UVM-SystemC, Formal approaches, Development of customer specific models and domain libraries Enable re-use of existing IP by importing them to SystemC (AMS) Fraunhofer IIS/EAS Integration of Hardware-inthe-loop systems (dspace, FPGAs, ) for SystemC (AMS) Research on SystemC (AMS) related topics Integration of customer specific tools Consulting and training 13

14 THANK YOU FOR YOUR ATTENTION YOUR CONTACT Stephan Schulz Group Manager Heterogeneous System Specification Fraunhofer Institute for Integrated Circuits IIS Design Automation Division EAS Zeunerstraße Dresden 14