System / Verification: Performance & Debug Track Abstracts

Transcription

1 System / Verification: Performance & Debug Track Abstracts VER2.201 Reducing Snapshot Creation Turnaround for UVM- SV Based TB Using MSIE Approach STMicroelectronics Abhishek Jain - STMicroelectronics Deepak Chauhan - STMicroelectronics Vishal Jain - STMicroelectronics Piyush Kumar Gupta - STMicroelectronics While developing and running the testcases in the SystemVerilog UVM based Verification Environments, Verification Engineers need to do recompilation and re- elaboration of the Verification Environment multiple times. If we are using single snapshot for both RTL and Verification Environment then, it takes lot of time to create the snapshot (having both RTL and Verification Environment) even for a small change in the testcase/sequence file and it results in delay in Verification activity. In this session we will discuss Multi- Snapshot Incremental Elaboration approach (MSIE) from cadence to improve the snapshot creation time of SystemVerilog UVM based Verification Environments. We found significant reduction in the snapshot creation time after using proposed approach which results in significant saving of the time in development of SoC verification environment. VER2.202 A Novel Approach for Low Power Verification Using Randomization on a Given Power and Clocking Matrix Freescale Semiconductor Siddharth Garg - Freescale Semiconductor Naveen Jakhar - Freescale Semiconductor Amit Bathla - Freescale Semiconductor Naveen Srivastava - Freescale Semiconductor With the growing complexity of SoCs, multiple clock sources are available to support the design. Moreover depending upon the power and functionality requirements, we can have different power modes in SoCs. The challenge is to verify all the clock sources configurations in all modes by sweeping past across all modes and having different clock configurations in each mode. We need to cover m*(2^n)*p cases, where m is the number of power modes, n is the number of clock sources and p is the number of possible system clock sources. It will be very tedious to cover all these possible combinations by directed test cases. In this session, an approach, based on the concept of adjacency matrices, is presented in which clocking and mode verification has been done together using randomization which provides full coverage for the valid combinations.

2 VER2.203 Usage of SV 2012 Real Number Models with UVM for Enhanced Mixed- Signal Verification: A Case Study Analog Devices Dushyant Juneja - Analog Devices Jogendra Patel - Analog Devices Sandeep Bojja - Analog Devices Kunal Jani - Analog Devices Swati Ramachandran - Cadence Design Systems The work intends to present a case study on enhancing digital mixed signal verification using the facilities provided by the latest IEEE standard, specifically the nettype syntax for Real Number Modeling (RNM). The standard introduces fuller analog system level modeling capacities as opposed to prevalent RNM technologies that have a strict signal chain orientation. This enables us to lower the burden on slower methods such as co- simulations, while enabling exhaustive mixed signal regressions. In this session, we intend to give an overview of the standard the facilities and the gotchas brought about by the standard, and present the effort it took to leverage this to accomplish mixed signal metric driven verification (MDV- MS) for an Ultra- Low Power Mixed Signal SoC. VER2.204 Low Power UTP Based Efficient and Effective Verification of Complex Power Intent in NextGen SoCs Freescale Semiconductor Deepak Mahajan - Freescale Semiconductor Abhinav Nawal - Freescale Semiconductor Saloni Raina - Freescale Semiconductor Ever increasing complexity low power design architecture and corresponding significant increase in scope of low power intent verification, necessitates a well defined verification plan which leverages all avenues of verification. An Unified Test Plan (UTP) based approach for a selection of design features to be verified, as well as the optimum platform for verification like Digital Verification, Analog and Mixed Simulations, Pre Silicon Emulation can ensure we achieve comprehensive verification of low power intent in an efficient manner with coverage of all planned items. This paper showcases the UTP (Unified Test plan) based Low Power verification methodology employed for Effectively and Efficiently verifying the power intent in a next generation automotive SoC.

3 VER2.205 Performance Guidelines and Techniques to Get Breakthrough Simulation Speeds in Module/SoC Level Environments for Functional Verification. Samsung Raghavendra Sosle Padmanabha - Samsung Kotragoud H G - Samsung Ann Sheena - Samsung Akshay Surendran - Samsung Vijay Kumar Birange - Cadence Design Systems VER2.206 Unleashing SimVision's Power Through TK Plugins SanDisk India Design Private Limited Omprakash Jha - SanDisk As the complexity of Verification grows and time- to- market shrinks, it becomes imperative the Verification Engineer s time and effort is used more efficiently. DV engineers debugging complex scenarios often have to spend time to gather meaningful data from the simulation, and then interpret them to conclude the nature of the issue. If the burden of data- collection and translation of data to useful information can be automated and presented to the user in an interactive Graphical User Interface, then the debug time can be reduced significantly. In this session, we will see how in a short time we built a classic CPU disassembler and debugger plugin, which is an interactive GUI made with TCL- Tk and SimVision callbacks, which reduced our debug time and effort.

4 VER2.207 Modeling and Verification Using System Verilog in Virtuoso and Incisive Enterprise Simulator (NCSIM) SilabTech Tom Thomas - SilabTech Sharath N - SilabTech Nanda Kumar U - SilabTech Design of Mixed Signal IP is becoming increasingly complex and compute- intensive that it is critical to detect architectural or functional issues early in the design cycle so that there is minimal debug- redesign cycles at later stages of IP design. Verifying complete behavior of the IP, before creating transistor level design, is one method to achieve this required confidence. Also, in mixed signal designs, RTL and AFE (Analog Front End) designs depend heavily on each other. So validating the correctness of analog- digital interface is also a key concern. In this session we discuss a methodology to model and verify real behavior of a mixed- signal IP using SystemVerilog in Virtuoso and NCsim. We explain this approach with a 12.5Gbps SERDES transmitter design. VER2.208 SoC Gate Level Simulations: Taming the Beast! Open- Silicon Abhijit Dongre - Open- Silicon Mitesh Thakkar - Open- Silicon Gate Level Simulations (GLS) for complex SOC s are considered as very challenging among all verification tasks as they have greater debug complexity, complex timing checks and long runtimes. In addition lack of planning, knowledge of tool options and information on GLS makes it much more difficult. Significant time is wasted in trying out different tool option and debugging tool related issues, rather than concentration on real issues. This paper discuss commonly faced GLS issues and their solutions that will allow engineers to complete GLS on time.

5 VER2.209 Smart Debug Using Incisive Debug Analyzer (IDA) Texas Instruments Harish M - Texas Instruments Vijay Kumar Birange - Cadence Design Systems Vinay Rawat - Cadence Design Systems Debugging of IP random verification failure have been challenging due the complexity of the design/test bench. Typically iteration of the failure seed may be required to isolate failure point or just to get information on the failure. In case of re- used IP DV environments, significant time is spent to get an idea on the environment, simulation flow etc. Significant time is lost in these redundant iterations, environment debug. This session details the evaluation of cadence Incisive Debug Analyzer on one of the IPs. This can greatly reduce the debug effort. The simulation performance impact also has been analyzed and defined a usemodel based on the feature set / performance. Also describes the methods to fine tune the simulation performance.