University of Maiduguri Faculty of Engineering Seminar Series Volume 6, december 2015

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1 University of Maiduguri Faculty of Engineering Seminar Series Volume 6, december 25 RAPID PROTOTYPING OF DIGITAL SYSTEMS: THE ROLE OF FIELD PROGRAMMABLE GATE ARRAYS C. U. Ngene and P. Y. Dibal Department of Computer Engineering, University of Maiduguri Abstract Today electronic vendors are jostling to satisfy the ever increasing and complicated consumer requirements. In order to meet these demands in a timely and efficient manner it becomes imperative to use a robust prototyping platform that would reduce non-recurring engineering cost (NRE), improve reliability and reduce time-to-market pressures. This paper examines the shortcomings of handcrafting designs and the use of small-, medium- and large-scale integrated components and the benefits of using field programmable gate arrays (FPGA) as a single prototyping platform. FPGAs are viable implementation alternative for larger and complex designs ensuring small final device area, high speed and low power consumption. The FPGA design flow using appropriate electronic design automation (EDA) tool and hardware description language such as VHDL have been considered. It has also been shown that design reuse and availability of intellectual property (IP) cores provided by various FPGA vendors facilitate rapid prototyping of digital systems. Keywords: Digital Design, EDA, FPGA, Rapid Prototyping, VHDL. Introduction The appearance of any electronic product in the market is preceded by rigorous specification formulation, design, verification, and testing. Specification formulation, design and verification can be done using EDA tools, but it is only a physical device that can be tested. This implies that a physical model of the would-be device must be created and properly tested to be sure that it conforms to the initial specification. Improperly tested devices are prone to failure and subsequently more devices are recalled. This of course is not a good business strategy considering the high nonrecurring engineering costs of the overall design. In the early days these prototypes are handcrafted, which takes a long time to be completed even for small scale integrated circuits (SSI) and medium scale integrated circuits (MSI) which populated the board. Another important issue with handcrafted prototypes is long time to market (TTM). With complicated designs like application specific integrated circuits (ASIC) and system on chip (SoC) the TTM will be prohibitively long leading to late delivery of products to the market with the associated high NRE. Recently, the world of electronic devices is becoming more and more complex as consumer requirements are increasingly becoming more sophisticated by the day. In today's technologically driven society TTM period is shrinking. New products are introduced rapidly, and failing to have a product ready at a given market window, can cost a company a considerable amount of revenue. Considering the importance of TTM and the need to improve yield, FPGAs are currently used for prototyping. The problems encountered by early designers are clearly depicted in Figure, where prototypes were built using wire wrap technology. Three of them were built by IBM engineers and only two worked. This prototype was delivered to Microsoft for program development(david, 2). Initially, it was decided that custom ICs like ASIC would be a better replacement of the large amount of interconnects. To a greater extent custom ICs reduced system complexity and manufacturing cost, and improved performance. However, they are relatively very expensive to develop and long TTM because of increased design time. Because of its insensitivity to TTM high cost custom IC was only viable for products with very high volume. The introduction Seminar Series Volume 6, 25 Page 23

2 of FPGAs by Xilinx in 985 as an alternative to custom IC gave the users the opportunity to implement an entire system on single chip. Furthermore, with the help of EDA tools circuits could be implemented in short amount of time. This is because there is no need for physical layout process no IC manufacturing. FPGAs provide a single prototyping platform, which facilitates verification for hardware, firmware, and application software design functionality before the first silicon pass. The use of FPGAs for prototyping has gained wide spread acceptance because of its low startup costs, low financial risk, quick manufacturing turnaround and easy design changes. a b Figure IBM PC Motherboard Prototype (a) front (b) back Source IEEE Computer August 2 2. Rapid Prototyping In view of the need to quickly respond to customer demands it becomes mandatory that a product should not only adapt to software changes but should also have the capability to adapt to hardware changes. This situation becomes more demanding for embedded systems where it is important to close the gap between specification and implementation and to support co-design and validation of large embedded systems (Frank et al, 2). The motivation for using a prototype varies according to the application and company s interest. In (Kordon, 23), two levels of prototyping were examined: one that reduces the TTM and cost of a system and the other increases security and reliability of a system. These are elaborated in Table. Table : Motivation for Rapid Prototyping Interest Description Systems Benefits Level Level 2 Reduction of cost and time-tomarket of a system Increases security and reliability of a system Complex Systems embedded, distributed, real-time, etc Safety Critical Systems Cost of skilled engineers increases rapidly Automated development could reduce the need for skilled engineers, standard engineers can work the prototyping tools Prototyping allows formal verification to be operated when required. This method allows high levels of reliability in system design and implementation 3. Overview of FPGAs Following some of the deficiencies inherent in programmable logic devices (PLD) and complex programmable gate arrays (CPLD) in terms of gate densities and TTM, Xilinx in 985 introduced the all time programmable gate arrays with gate densities that can accommodate more complex Seminar Series, Volume 6, 25 Page 24

3 designs. At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt logic blocks and programmable routing resources, you can configure these chips to implement custom hardware functionality without ever having to pick up a breadboard or soldering iron (NI, 22). There are two major types of FPGAs: one-time programmable and SRAM-based. As the name implies one-time programmable is rigid and cannot be reprogrammed after it has been programmed. On the other hand SRAM-based FPGAs can be reprogrammed as many times as the engineer chooses. SRAM determines interconnection and defines logic look-up table (LUT). SRAM-based FPGAs is the dominant type that is widely used in the industry today. A simple generic FPGA architecture is depicted in Figure 2, where programmable logic blocks (PLBs) are arranged in a two dimensional grid and are interconnected by programmable routing resources. Xilinx calls its PLB configurable logic block (CLB) whereas Altera refers to it as logic array block (LAB). I/O blocks though not shown in Figure 2 are arranged at the periphery of the grid and they are also connected to the programmable routing interconnect. Today s FPGA architectures are LUT-based. FPGAs can be based on 3-, 4-, 5- and even 6-input LUTs. A typical logic block consists of LUT, multiplexer and flip-flop as shown in Figure 3. Figure 2: Simple Generic FPGA Architecture Figure 3: Key Elements of Logic Blocks LUT are usually built as small RAMs that are loaded with a truth table. For example, an eight-bit RAM can perform a three-input and operation if it is loaded as follows (Figure 4): Truth Table Programmed LUT Required Function A2 A A O/P SRAM Cells 8: Multiplexer O/P A2 A A O/P Figure 4: Logic Function Realisation A2 A A Surveys indicate that FPGAs are now a part of 5 to 7 percent of all embedded systems (Glenn, 2). All FPGA vendors provide comprehensive solutions consisting of boards and kits, Intellectual property (IP), software, and design tools. Apart from the distributed RAMs formed by the LUT, FPGAs contain other embedded devices that can be leveraged by other applications. Some of these embedded devices are shown in Figure 5. Recently, processors which hitherto were a discrete component on a board have migrated to stay on the same chip as the FPGA fabric. Sophisticated FPGAs contain one or more embedded processors, which are known as Seminar Series, Volume 6, 25 Page 25

4 microprocessor cores (hard and soft cores). A hard microprocessor core is located on a strip as shown in Figure 5. Other FPGA vendors are Altera, Lattice Semiconductor, Microseni (Actel), Quicklogic, Atmel, Achronix and Cypress. In Figure 6 is shown that Xilinx and Altera are the two top FPGA companies that have taken 89% of the market (Jeff, 2). The rest of the companies are gradually winning market share by targeting specific applications and sub-markets. Xilinx who is the leader for many years has good range of FPGAs in terms of cost and performance. In recent years, the popular Spartan series has covered the low-to-mid-end market while the Virtex series has covered the high-end. Recently, Xilinx released the 7 family of FPGAs which are built on 28-nm process and for the first time introduced the Artex-7 and Kintex-7 series which provide better coverage of the lower and mid-end applications previously covered by the Spartan series. Main FPGA Fabric Stripe up RAM I/O etc. 4% 49% 6% 4% % xilinx Altera Lattice Semiconductor Microsemi (Actel) Quicklogic Logic Block MAC RAM Block Figure 5: A chip containing FPGA Fabric Figure 6: FPGA Market Share by 2 and other Embedded Devices revenue Millions. (Source Jeff, 2) 4. FPGA Design Flow The implementation of FPGA targeted designs requires a robust EDA tools. Some of these tools provide support for multiple HDLs (VHDL and Verilog). Apart from FPGA HDL design flow, these tools also provide support for FPGA schematic-based design procedure. FPGA schematicbased design is rather time-consuming especially for large designs with over, gates, as it requires that each components, gates, interconnections and input/outputs must be inserted physically by the engineer. Another inherent problem with using schematic capture is the difficulty in migrating between vendors and technologies as vendor s component library differs. Xilinx calls its free edition ISE Design Suite Webpack edition whereas Altera has Quartus II web edition. The FPGA design flow is divided into three major stages of design specification, Functional (behavioural) Verification and Implementation as depicted in Figure Specification The design specification starts with a means of describing the design leading finally to the generation of a netlist (text equivalent of the circuit: gates used and their interconnection). The netlist is a compact way for other programs to understand what gates are in the circuit and how they are connected (Xilinx, 26). A design targeting an FPGA is specified using either the schematic Seminar Series, Volume 6, 25 Page 26

5 Specification Schematic Design Entry HDL (RTL) VHDL Verilog Translate Map Implementation Synthesis Design Specification Pre-Synthesis Simulation Place and Route Netlist Functional Verification TIMING VERIFICATION Timing Analysis (Back Annotation) Simulation Simulation Test Vectors Download and Program FPGA Figure 7: Typical FPGA Design Flow capture tool or HDL. Schematic tools provide graphic interface for design entry. However, some designs employ a combination of schematic capture (state transition diagrams for state machine design) and HDL descriptions (Alain, 29). HDLdescription offers a number of advantages which includes: Allows design functionality to be verified early in the design process; It is more easily read and understood by schematic or netlist description. It is important to know that the initial HDL design description is technology independent. For example the VHDL code in Figure 8a is portable across various vendor EDAs but the synthesised circuit in Figure 8b is technology dependent. Electronic Design Automation vendors provide integrated software environment that controls all aspects of the development flow. For instance the Xilinx design suite s project navigator is a graphical interface for users to access software tools and relevant files associated with a project. library IEEE; use IEEE.STD_LOGIC_64.ALL; entity three_to_one_mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sel : in STD_LOGIC_VECTOR ( downto ); F : out STD_LOGIC); end three_to_one_mux; architecture Behavioral of three_to_one_mux is begin with sel select F <= a when "", b when "", c when "", 'X' when others; end Behavioral; (a) (b) Figure 8: Design of 3-to- Multiplexer : a) Multiplexer VHDL Code, b) Synthesised Multiplexer Circuit Seminar Series, Volume 6, 25 Page 27

6 This suite consists of a number of tools that enables one to capture the design, simulate, synthesise and implement the design. Tools provided by EDA companies (like Mentor Graphics, Synopsys, Cadence, Aldec etc) are sophisticated, expensive and supports multi-language and FPGAs from multiple vendors. Design tools provided by FPGA vendors are shown in Table 4. Although each software design tool differs in appearance and the manner in which the designer interacts with it, all have a common set of basic features required to create and implement designs within a particular tool. These features include: Project Management; Design entry; Design simulation; Design synthesis; Place and route; Post-layout Delay extraction; Post-layout simulation; Configuration file generation; FPGA configuration and Interface to third-party tools for simulation or synthesis. Table 4 FPGA Design Tools by Vendor FPGA Vendors and Tools Vendors Tools Characteristics Xilinx ISE TM Design Suite Vivado FPGA Design Entry, Simulation, Synthesis and Device Programming 7-series FPGA and upward. SoC Altera Quartus II FPGA design entry 4.2 Verification After the design has been captured using schematic or HDL or a combination of both, it is simulated in order to validate the design. Simulation is done using appropriate testbenches that are applied to the HDL design presynthesis simulation. If the behaviour of the design is in conformity with the specification the design is further synthesised using appropriate user constraint features (e.g. area, power requirement) to produce the design netlist. After the design has been synthesised it is further simulated postsynthesis simulation. The same testbench used for presynthesis simulation is also used for postsynthesis simulation and the simulation results on both designs are compared to ensure that the two design operations are equivalent. Postsynthesis simulation of design before implementation, allows you to evaluate architectural and design decisions. 4.3 Implementation Choosing the right FPGA device is critical to a successful design that meets the area and timing constraints. Once the netlist has been generated by the synthesis tool the stage is now clear for the design to be put on a chip design implementation. Generally the netlist describes the design using the gates for a specific vendor/device family. Design implementation involves the following steps: translate mapping, place and route, timing verification, and download or programming. The translate stage involves the preparation of the netlist for layout of the FPGA. This stage interprets the design and runs a design rule check. (e.g,. does the design exceed the number of input/output ports or the number of clock buffers available in this device?). The Map stage calculates and allocates resources in the targeted device. Place and route places the CLBs in a logical position and utilises the routing resources. Timing analysis stage provides timing information about paths in the design. This information is very accurate and can be viewed in many different ways, such as displaying all paths in the design Seminar Series, Volume 6, 25 Page 28

7 and ranking them from longest to shortest delay. After obtaining timing information we go back to the simulator to re-simulate the design. This is known as back annotation. Back annotation has the advantage of providing the accurate timing as well as the zeros and ones operation of your design. Generally timing is all about the delays associated with the speed of operation of the logic gates in the logic blocks. The longest path (highest delay) actually determines the speed of the overall system. 5. Infrastructure for Rapid prototyping FPGA devices in conjunction with the various tools for implementing designs provide facilities that enhance rapid prototyping. Such facilities include prototyping boards for different types or categories of FPGAs, the use of Intellectual properties and design reuse. 5. FPGA Prototyping Boards Xilinx and other FPGA vendors parade array of prototyping boards through their partners. Digilent is one of the partners of Xilinx that provides boards for Spartan 3E, virtex FPGAs etc as shown in Figure. These boards contain LCD display, seven segment LED, switches and buttons that enable the designer or student to visualise the workings of his design. Figure Xilinx FPGAs on Digilent Boards 5.2 Intellectual Property (IP) IP are ready to use standard designs that are in most cases sold or may be provided for free depending on the vendor. These IP cores have been properly and rigorously verified and tested, thus allowing them to be used directly in a design without slightest worry about their reliability. Xilinx for example has standard CORE Generator System, which is a design tool that delivers parameterized cores optimized for Xilinx FPGAs. This provides you with a catalogue of readymade functions ranging in complexity from simple arithmetic operators such as adders, accumulators, and multipliers, to system-level building blocks such as filters, transforms, FIFOs, and memories. These Cores can be re-customised and regenerated by the designer. Designers leverage on the availability of these cores to deliver new designs to the market in an efficient and timely manner. 5.3 Design Reuse Effective design reuse is a critical objective for every electronic design company as 75% of future productivity gains will come through reuse (Mentor, 26). Ever since hardware description languages (HDLs) were first put into use to specify electronic designs, designers have recycled code with permission of course. In view of the fact that designs targeting FPGAs are first captured in HDL- VHDL for example, it is possible to reuse previous designs for the current ongoing designs. For example if an 8-bit processor specifications were previously captured in Seminar Series, Volume 6, 25 Page 29

8 VHDL, subsequent designs requiring the use of the same type of processor will only instantiate it in the top level design rather than designing it afresh.. 6. Conclusion Generally, design prototyping creates a physical prototype or the overall system that allows the operation of the real design to be evaluated. HDL and FPGAs allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on prototyping device, and verify operation of the physical implementation. It has been shown that FPGA-based design flow as a top-down design methodology speeds up design in an integrated manner without the need for soldering of any sort. This ensures rapid delivery of prototypes with the flexibility of reprogramming anytime anywhere. Successful design requires a robust EDA tool with all necessary software tools that supports design capture in HDL, verification, synthesis and implementation tools. This paper has demonstrated that the necessary ingredients for aiding rapid prototyping using FPGA constitute the design reuse which is facilitated by the use of HDL and IP-cores provided by vendors as an integral part of the EDA tool. References Alain Vachoux (29), Top-Down Digital Design Flow, Version 4., Online: accessed May 5, 25 David Bradly (2), A Personal History of the IBM PC, IEEE Computer, August 2, pg 2. Frank S., Mathias D., Ralf M. and Richard H. (2), Hardware/Software Codesign and Rapid Prototyping of Embedded Systems, IEEE Design and Test of Computers NI (22), Introduction to FPGA Technology: 5 Top Benefits, Online: accessed July 9, 24 Glenn Steiner and Dan Isaacs (2), Demystifying FPGAs for Software Engineers, Xcell Magazine issue 75, pg 44 Kordon, F., Henkel, J., (23), An overview of Rapid System Prototyping Today- Design Automation for Embedded System, vol. 8, issue 4, pg Jeff Johnson (2), List and comparison of FPGA companies by, Online: accessed 24 October 24 Mentor (26), Design Reuse, Online: Accessed May 6, 25 Xilinx (26), Spartan-3E FPGA Starter Kit Board User Guide, Online: accessed October 4, 24. Seminar Series, Volume 6, 25 Page 3