Signal Integrity Bit Error Rate Testing
|
|
|
- Barbara Williamson
- 7 years ago
- Views:
Transcription
1 Signal Integrity Bit Error Rate Testing APEMC 2015 Toshihiro SUZUKI Marketing Division Anritsu Company May 2015 PBD3-1SG150001
2 Presenter Bio Toshihiro SUZUKI Marketing Manager Global Business Development Anritsu Corporation 14 years experience in high speed physical layer testing. Development Engineering for BERT Business Development for BERT, Jitter, Scope and OSA.
3 Agenda High-Speed data Market Trends Growing Telecom and Datacom Market trends and technologies Anritsu s role in high-speed data Market Tips for Basic Signal Integrity Measurements Differential Signals Jitter Tolerance Frequency Components Signal Integrity Test & Measurement Considerations Emphasis implementation Pulse Amplitude Modulation (PAM) generation Differential Skew Tolerance Summary
4 Agenda High-Speed data Market Trends Growing Telecom and Datacom Market trends and technologies Anritsu s role in high-speed data Market Tips for Basic Signal Integrity Measurements Differential Signals Jitter Tolerance Frequency Components Signal Integrity Test & Measurement Considerations Emphasis implementation Pulse Amplitude Modulation (PAM) generation Differential Skew Tolerance Summary
5 Market Trend The global network traffic is increasing 32% annually The mobile traffic is increasing 61% annually Cloud service via Datacenter 140,000 Petabytes (PB) per month 120, ,000 80,000 60,000 40,000 20, Fixed Internet Managed IP Mobile data Total Source: Cisco Virtual Network Index
6 Market Trend Cloud service drives growth of Mega Data Center. Challenge is efficiency : high speed and less power
7 Market Trend Data Center Traffic Traffic within data center have 76% share in all of data center traffic. Further demand of AOC/QSFP+ can be expected. Source: Cisco, Cloud Traffic Booming
8 Market Trend Optical Transceiver Market Size and Forecast Revenue growth in CAGR 11% 100G 40G 10G Source: Infonetics Research 8 Slide Title or URL
9 Market Trend IBTA (Infiniband): Start discussing EDR(28G) IEEE (Ethernet): 802.3bs starts discussing 400GbE 8x50G? FCIA (Fibre Channel): 32GFC in 2013, 128GFC in 2014 Product Name Line Rate (GBaud) T11 Spec Completed 16GFC GFC GFC 4 x Market Availability 64GFC TBD 2016 Market Demand 9
10 Market Trend Growing Telecom and Datacom Market trends and technologies Recent activity from OIF, IEEE, PCIe & IBTA Growth in 100G Telecom Market Growth in IBTA & FCIA Datacom Market Market Trends featuring Industry reported growth Anritsu s role in high-speed data Market High Speed BERT Vector Network Analyzer Combination BERT & Sampling Scope 10
11 Market Trend Anritsu s role in high-speed data market Anritsu manufactures Test and Measurement products for highspeed data applications 11
12 Agenda High-Speed data Market Trends Growing Telecom and Datacom Market trends and technologies Anritsu s role in high-speed data Market Tips for Basic Signal Integrity Measurements Differential Signals Jitter Tolerance Frequency Components Signal Integrity Test & Measurement Considerations Emphasis implementation Pulse Amplitude Modulation (PAM) generation Differential Skew Tolerance Summary
13 Tips for Basic Signal Integrity Measurement Differential Signal Measurements Phase matched cables High tolerance to voltage side noise Cable length & bend radius affect differential phase margin Jitter Tolerance Testing Trace Path Length difference Propagation delay including internal circuit Clock and data drift Frequency components Square wave contains odd harmonic spectrum Difference in Tr/Tf in waveforms Connectors, LPF, Attenuators and cables examples 13
14 Tips for Basic Signal Integrity Measurement Differential signals Recommended for greater threshold margins. However 8 Gbit/s 10 Gbit/s 25 Gbit/s 32 Gbit/s (ps) Faster data rates result in shorter bit periods Shorter bit periods result in smaller margins of error Phase Matched Cables become essential when signal speed increase. 14
15 Tips for Basic Signal Integrity Measurement Differential Signal Measurement Why Phase Matched Cables? Electrical Speed Distance (cable length) 4.75 nanoseconds 1 Meter (40 Inch) 4750 Picoseconds 1 Meter (40 Inch) 4.75 Picoseconds 1 Millimeter (0.04 Inch) How does cable length difference affect differential phase margin? Bit rate: 25.78Gbit/s (1UI = 38.8psec) 1 mm (0.04 inch) cable length difference 12.2% 15
16 Tips for Basic Signal Integrity Measurement Differential Signals Caution when bending Phase Matched Cables 30 Gbps = 33 ps 15 degree = ps 4.2% of bit period Bent cable never returns to original performance 15 degree = ps at 33Gbps Bent cables increase total jitter due to increase of propagation delay 16
17 Tips for Basic Signal Integrity Measurement Jitter Tolerance The maximum jitter limit that the receiver can be in error free. CDR determines jitter tolerance in the receiver. Phase difference is generated at high-jitter-frequency in the Decision Circuit due to jitter transfer characteristic. The PLL loop band design and the phase margin of the Decision Circuit determine jitter tolerance. Jitter Tolerance Jitter + PPG DUT Receiver ED Data Limit. Amp. Data Decision Circuit Data Clock Recovery PLL Clock 17
18 Tips for Basic Signal Integrity Measurement Jitter Tolerance Jitter Components break down Thermal noise RJ Random Jitter TJ Total Jitter DJ Deterministic Jitter Caused by crosstalk Caused by system noise such as switching PSU PJ Periodic Jitter DCD Duty Cycle Distortion DDJ Data Dependent Jitter ISI Inter Symbol Interference BUJ Bounded Uncorrelated Jitter DDPWS Data Dependent - Pulse Width Shrinkage Caused by bit threshold shift at Tx or Rx Caused by lack of bandwidth and impedance mismatch in transmission path 18
19 Tips for Basic Signal Integrity Measurement Jitter Tolerance Test instrument generates several Jitter Components Sine-wave jitter (SJ) Random jitter (RJ) Bounded uncorrelated jitter (BUJ) Half Period Jitter
20 Tips for Basic Signal Integrity Measurement Jitter Tolerance Attention must be given to the trace length difference between Data and Clock trace path. Two types of phase A: Phase difference between Data and Clock in ONE BIT (ONE UI) B: Difference of Absolute Phase (Electric length) between Data and Clock due to propagation delay Jitter Data Clock 1m 3m Decision Circuit 1m = 4.35ns 3m = 13.05ns A: Phase Difference in one bit 20 B: Absolute Phase Difference
21 Tips for Basic Signal Integrity Measurement Jitter Tolerance Even if A: Phase in one bit was matched (adjusted), B: Absolute Phase difference might occur phase mismatch at high-frequency-jitter. Jitter is the change of the Phase. The edge timing will be different depends on the Absolute Phase (Electric Length) witch is determined by propagation delay (cable length). Jitter (change of the phase) will reach at the end point with propagation delay. 21
22 Tips for Basic Signal Integrity Measurement Jitter Tolerance How does Trace Path Distance impact Jitter? Increased Jitter frequency Increased Jitter amount 22 Slide Title or URL
23 Tips for Basic Signal Integrity Measurement Jitter Tolerance Testing Attention must be given to the trace length difference between Data and Clock trace path of test instrument. Using internal CRU of ED avoid these problem PPG DUT EXTERNAL CRU ERROR DETECTOR DATA OUT DATA IN DATA OUT DATA IN DATA OUT DATA IN CLK OUT RECOVERY CIRCUIT CLK IN PPG DUT INTERNAL CRU ERROR DETECTOR DATA OUT DATA IN DATA OUT DATA IN DATA OUT DATA IN CLK OUT RECOVERY CIRCUIT CLK IN 23
24 Tips for Basic Signal Integrity Measurement Frequency Components Square Wave Fundamentals Square wave contains odd harmonic spectrum such as 3rd and 5th harmonic. 10 Gbit/s PRBS Signal 3rd harmonic (15 GHz) Carrier (5 GHz) 5th harmonic (25 GHz) 24
25 Tips for Basic Signal Integrity Measurement Frequency Components: High Frequency = Fast Tr/Tf Adding the 7th harmonic affects the square wave 12.5Gbps PRBS Signal Generator A 12.5Gbps PRBS Signal Generator A Tr/Tf = 28 ps 31.25GHz 12.5Gbps PRBS Signal Generator B Tr/Tf = 12.5 ps 43.75GHz 12.5Gbps PRBS Signal Generator B Carrier 3 rd 5 th harmonics Carrier 3 rd 5 th 7 th harmonics 25
26 Tips for Basic Signal Integrity Measurement Frequency Component Example #1: SMA-SMP Adapter S21: Almost flat up to 50GHz. 26
27 Tips for Basic Signal Integrity Measurement Frequency Component Example #1: SMA-SMP Adapter No significant difference after the SMP-SMA adapter. 27
28 Tips for Basic Signal Integrity Measurement Frequency Component Example #2: BNC Adapter 28
29 Tips for Basic Signal Integrity Measurement Frequency Component Example #2: BNC Adapter Generator B suffers greater distortion than Generator A due to higher Frequency Components 29
30 Tips for Basic Signal Integrity Measurement Frequency Component Example #3: LPF 6.8Ghz 30
31 Tips for Basic Signal Integrity Measurement Frequency Component Example #3: LPF 6.8Ghz Generator B suffers greater distortion, exhibiting Double traces and more Jitter than Generator A due to higher Frequency Components 31
32 Tips for Basic Signal Integrity Measurement Frequency Components Example #4: Attenuators Generator C generates the same 28Gbps PRBS waveform Two different 20dB Attenuators are tested The Same Sampling Scope was used for measurement Need to adjust Bandwidth Frequency through the entire path 32
33 Tips for Basic Signal Integrity Measurement Frequency Components Example #5: Cables Generator C generates the same 28Gbps PRBS waveform Two different cables are tested The Same Sampling Scope was used for measurement Cable Bandwidth directly affects the observed waveform quality 33
34 Tips for Basic Signal Integrity Measurement Frequency Components Example #6: Sampling Scopes Generator C generates the same 28Gbps PRBS waveform Two different Sampling Scopes are tested The cables was used for measurement Distorted 70GHz Bandwidth Slower Tr/Tf 50GHz Bandwidth Sampling Scope Bandwidth directly affects the observed waveform quality 34
35 Agenda High-Speed data Market Trends Growing Telecom and Datacom Market trends and technologies Anritsu s role in high-speed data Market Tips for Basic Signal Integrity Measurements Differential Signals Jitter Tolerance Frequency Components Signal Integrity Test & Measurement Considerations Emphasis implementation Pulse Amplitude Modulation (PAM) generation Differential Skew Tolerance Summary
36 Signal Integrity Test & Measurement Considerations Emphasis Implementation Emphasis attenuated High-frequency components VNA S-parameters to identify ideal emphasis Pulse Amplitude Modulation (PAM) Generation Increase information density using same data rate Bit & Pattern synch PPG Measurement mask capable ED High input sensitivity ED Differential Skew Tolerance Precise differential trace length adjustment Differential skew tolerance receiver Trace Path Length difference 36
37 Signal Integrity Test & Measurement Considerations Emphasis Implementation 37
38 Signal Integrity Test & Measurement Considerations Emphasis Implementation Emphasis technology (transmitter emphasizes those highfrequency components which could be attenuated) assures large Eye opening at receiver. 38
39 Signal Integrity Test & Measurement Considerations Emphasis Implementation S Parameters from a Vector Network Analyzer are key to creating optimal Emphasis 39
40 Signal Integrity Test & Measurement Considerations PAM (Pulse Amplitude Modulation) Applications: Backplane transmission 40GBase-KP4, 400GbE, CEI-56G Multi bit info in time slot Maintaining symbol rate while increasing the data transfer capacity Minimized voltage level causing a degraded signal to noise ratio (SNR) 2PAM (NRZ) 1bit / time slot 4PAM 2bits / time slot 8PAM 3bits / time slot EYE Diagram Bit Pattern 40
41 Signal Integrity Test & Measurement Considerations Pulse Amplitude Modulation (PAM) Generation How to generate PAM signal? Multiple PPGs should have precise phase adjustment Need to care about Tr/Tf, jitter and waveform distortion Attenuators & Power Dividers 41
42 Signal Integrity Test & Measurement Considerations Pulse Amplitude Modulation (PAM) Generation Requirements for Measuring PAM4 Signal BER Mask Capability to eliminate false BER High Input Sensitivity for Error Detector 42
43 Signal Integrity Test & Measurement Considerations Differential Skew Tolerance Differential Skew Tolerance test is recommend for Receivers Precise Differential Trace Length Adjustment is required Data / Xdata skew tolerance test 43
44 Summary As high speed data rates continue to increase and evolve, so to must the test equipment capabilities. In addition, high speed device testing requires different components, cables and T&M equipment from the previous generation of device testing. To ensure high quality Signal Integrity for high speed devices and components, attention must be given to not only the test equipment, but the components being used in the test environment. 44
45
Keysight Technologies Characterizing and Verifying Compliance of 100Gb Ethernet Components and Systems. Application Brief
Keysight Technologies Characterizing and Verifying Compliance of 100Gb Ethernet Components and Systems Application Brief Overview The expansion in Ethernet data bandwidth from 10Gb/s through 40G to 100G
PCI-SIG ENGINEERING CHANGE NOTICE
PCI-SIG ENGINEERING CHANGE NOTICE TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE: Updated 10 January 013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev. 3.0 SPONSOR: Intel, HP, AMD Part
Timing Errors and Jitter
Timing Errors and Jitter Background Mike Story In a sampled (digital) system, samples have to be accurate in level and time. The digital system uses the two bits of information the signal was this big
Advanced Modulation Formats in Data Centre Communications Michael J. Wale Director Active Products Research
Advanced Modulation Formats in Data Centre Communications Michael J. Wale Director Active Products Research 2 nd Symposium on Optical Interconnects in Data Centres ECOC, Cannes, 23rd September 2014 1 2014
Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance
Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Page 1 Agenda Introduction PCIe 2.0 changes from 1.0a/1.1 Spec 5GT/s Challenges Error Correction Techniques Test tool
The Effect of Network Cabling on Bit Error Rate Performance. By Paul Kish NORDX/CDT
The Effect of Network Cabling on Bit Error Rate Performance By Paul Kish NORDX/CDT Table of Contents Introduction... 2 Probability of Causing Errors... 3 Noise Sources Contributing to Errors... 4 Bit Error
Jitter Measurements in Serial Data Signals
Jitter Measurements in Serial Data Signals Michael Schnecker, Product Manager LeCroy Corporation Introduction The increasing speed of serial data transmission systems places greater importance on measuring
Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers
White Paper: 7 Series FPGAs WP419 (v1.0) March 27, 2012 Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers By: Harry Fu The appetite for data is exploding, and the industry
Module 13 : Measurements on Fiber Optic Systems
Module 13 : Measurements on Fiber Optic Systems Lecture : Measurements on Fiber Optic Systems Objectives In this lecture you will learn the following Measurements on Fiber Optic Systems Attenuation (Loss)
Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer
Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer Hermann Ruckerbauer EKH - EyeKnowHow 94469 Deggendorf, Germany Hermann.Ruckerbauer@EyeKnowHow.de Agenda 1) PCI-Express Clocking
Technical Innovation. Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications
Technical Innovation Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications Increasing Speeds Present New Challenges The fundamental technology at the heart
Selecting the Optimum PCI Express Clock Source
Selecting the Optimum PCI Express Clock Source PCI Express () is a serial point-to-point interconnect standard developed by the Component Interconnect Special Interest Group (PCI-SIG). lthough originally
81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing
81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing Application Note Introduction Industry sectors including computer and components, aerospace defense and education all require
How To Get A Better Signal From A Fiber To A Coax Cable
Gigabit Transmission What s the Limit? Fanny Mlinarsky Page 1 What s the Limit? Speed Faster higher frequency higher attenuation less headroom Distance Longer higher attenuation more jitter less headroom
Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc
Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc Copyright 2015, PCI-SIG, All Rights Reserved 1 Disclaimer Presentation Disclaimer: All opinions, judgments,
6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course
6.976 High Speed Communication Circuits and Systems Lecture 1 Overview of Course Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott Wireless Systems Direct conversion
T = 1 f. Phase. Measure of relative position in time within a single period of a signal For a periodic signal f(t), phase is fractional part t p
Data Transmission Concepts and terminology Transmission terminology Transmission from transmitter to receiver goes over some transmission medium using electromagnetic waves Guided media. Waves are guided
Optical Fibres. Introduction. Safety precautions. For your safety. For the safety of the apparatus
Please do not remove this manual from from the lab. It is available at www.cm.ph.bham.ac.uk/y2lab Optics Introduction Optical fibres are widely used for transmitting data at high speeds. In this experiment,
Signal Types and Terminations
Helping Customers Innovate, Improve & Grow Application Note Signal Types and Terminations Introduction., H, LV, Sinewave, Clipped Sinewave, TTL, PECL,,, CML Oscillators and frequency control devices come
Jitter Transfer Functions in Minutes
Jitter Transfer Functions in Minutes In this paper, we use the SV1C Personalized SerDes Tester to rapidly develop and execute PLL Jitter transfer function measurements. We leverage the integrated nature
LONGLINE 10Gbps 10km SFP+ Optical Transceiver
LONGLINE 10Gbps 10km SFP+ Optical Transceiver Features Optical interface compliant to IEEE 802.3ae 10GBASE-LR Electrical interface compliant to SFF-8431 Hot Pluggable 1310nm DFB transmitter, PIN photo-detector
10Gb/s SFP+ LRM 1310nm FP with PIN Receiver 220meters transmission distance
Feature 10Gb/s serial optical interface compliant to 802.3aq 10GBASE-LRM Electrical interface compliant to SFF-8431 specifications for enhanced 8.5 and 10 Gigabit small form factor pluggable module SFP+
High Speed Characterization Report
ECUE-E-12-XXX-T1-P2 Mated with: UEC5-019-1-H-D-RA-1-A Description: FireFly Equalized Micro Flyover System, 36 AWG Micro Twinax Ribbon Cable Samtec, Inc. 2005 All Rights Reserved Table of Contents Cable
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Date: March 10, 2015 Revision: 1.0a SuperSpeed Electrical Compliance i Copyright 2015, USB Implementers Forum, Inc. All rights reserved.
Direct Attach Cable with Micro Coaxial Wire for Data Center
FEATURED TOPIC Direct Attach Cable with Micro Coaxial Wire for Data Center Yasuhiro MAEDA*, Kensaku SHIMADA, Yuki ISOYA, Tatsunori HAYASHISHITA and Michiko HARUMOTO ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions
Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions PCI Express Bus In Today s Market PCI Express, or PCIe, is a relatively new serial pointto-point bus in PCs. It was introduced as an AGP
8B/10B Coding 64B/66B Coding
8B/10B Coding 64B/66B Coding 1. Transmission Systems 2. 8B/10B Coding 3. 64B/66B Coding 4. CIP Demonstrator Test Setup PeterJ Slide 1 Transmission system General Data Clock D C Flip Flop Q @ 1 Gbps = 1
Dispersion penalty test 1550 Serial
Dispersion penalty test 1550 Serial Peter Öhlen & Krister Fröjdh Optillion Irvine, January 2001 Dispersion penalty test, 1550 serial Page 1 SMF Transmission at 1550 nm Different from multi-mode transmission
Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System
Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System INOUE Takanori Abstract As one of the foundations of the global network, the submarine cable system is required
Using Pre-Emphasis and Equalization with Stratix GX
Introduction White Paper Using Pre-Emphasis and Equalization with Stratix GX New high speed serial interfaces provide a major benefit to designers looking to provide greater data bandwidth across the backplanes
RF Measurements Using a Modular Digitizer
RF Measurements Using a Modular Digitizer Modern modular digitizers, like the Spectrum M4i series PCIe digitizers, offer greater bandwidth and higher resolution at any given bandwidth than ever before.
MODULATION Systems (part 1)
Technologies and Services on Digital Broadcasting (8) MODULATION Systems (part ) "Technologies and Services of Digital Broadcasting" (in Japanese, ISBN4-339-62-2) is published by CORONA publishing co.,
SIGNAL GENERATORS and OSCILLOSCOPE CALIBRATION
1 SIGNAL GENERATORS and OSCILLOSCOPE CALIBRATION By Lannes S. Purnell FLUKE CORPORATION 2 This paper shows how standard signal generators can be used as leveled sine wave sources for calibrating oscilloscopes.
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Date: September 14, 2009 Revision: 0.9 Preface 6/3/2009 Scope of this Revision The 0.7 revision of the specification describes the
Loop Bandwidth and Clock Data Recovery (CDR) in Oscilloscope Measurements. Application Note 1304-6
Loop Bandwidth and Clock Data Recovery (CDR) in Oscilloscope Measurements Application Note 1304-6 Abstract Time domain measurements are only as accurate as the trigger signal used to acquire them. Often
Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D.
Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D. Abstract: The definition of a bit period, or unit interval, is much more complicated than it looks. If it were just the reciprocal of the data
HSS Serial Standards Measurement @ 10G and 25G, Electrical Focus. David Yang
HSS Serial Standards Measurement @ 10G and 25G, Electrical Focus David Yang Agenda Transmitter (TX) test Mask test changes to Statistical Mask TWDP measurement: SFP+, 10 and 8 Gb/s due to IP problems Bandwidth
The ABC of Direct Attach Cables
The ABC of Direct Attach Cables Thomas Ko, RCDD Product Manager TE Connectivity Network Speed and Technology 10/40/100 Gbps the transition is occurring right now What are Customers Saying about their 10/40/100
The Evolution of Copper Cabling Systems from Cat5 to Cat5e to Cat6 Copper Cabling Standards and Technical Aspects
The Evolution of Copper Cabling Systems from Cat5 to Cat5e to Cat6 Copper Cabling Standards and Technical Aspects White Paper /7/0 Executive Summary Now that the TIA/EIA-568-B.- Category 6 Copper Cabling
Keysight Technologies Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-Performance Serial BERT.
Keysight Technologies Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-Performance Serial BERT Application Note Introduction J-BERT N4903B highperformance serial BERT with
Public Switched Telephone System
Public Switched Telephone System Structure of the Telephone System The Local Loop: Modems, ADSL Structure of the Telephone System (a) Fully-interconnected network. (b) Centralized switch. (c) Two-level
USB 3.0 CDR Model White Paper Revision 0.5
USB 3.0 CDR Model White Paper Revision 0.5 January 15, 2009 INTELLECTUAL PROPERTY DISCLAIMER THIS WHITE PAPER IS PROVIDED TO YOU AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
Lecture 2. High-Speed I/O
Lecture 2 High-Speed I/O Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2007 by Mark Horowitz, with material from Stefanos Sidiropoulos, and Vladimir Stojanovic
Highly Reliable Testing of 10-Gb/s Systems (STM-64/OC-192)
Highly Reliable Testing of 10-Gb/s Systems (STM-64/OC-192) Meeting the Growing Need for Bandwidth The communications industry s insatiable need for bandwidth, driven primarily by the exploding growth in
11. High-Speed Differential Interfaces in Cyclone II Devices
11. High-Speed Differential Interfaces in Cyclone II Devices CII51011-2.2 Introduction From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the
How To Understand And Understand Jitter On A Network Device
Understanding and Characterizing Timing Jitter Table of Contents Introduction... 3 Section 1: The Consequences of Jitter... 3 Computer Bus Design 3 Serial Data Link 4 Section 2: Just What is Jitter?...
How To Get 40G Over Copper (Wired) And 40G On Coaxian (Wireless) Cable (Wired Coaxian) (Wired Cable) (Wireline) (Powerline) And 50G Over Coaxian Cable (Wire Coaxian
Copper for Beyond 10GBASE-T David Zambrano Agenda Market Drivers Standards Cabling and Ethernet Field Test Considerations Agenda Market Drivers Standards Cabling and Ethernet Field Test Considerations
IN RECENT YEARS, the increase of data transmission over
1356 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 8, AUGUST 2004 A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet Rong-Jyi Yang, Student Member, IEEE, Shang-Ping Chen, and
Duobinary Modulation For Optical Systems
Introduction Duobinary Modulation For Optical Systems Hari Shanar Inphi Corporation Optical systems by and large use NRZ modulation. While NRZ modulation is suitable for long haul systems in which the
Eye Doctor II Advanced Signal Integrity Tools
Eye Doctor II Advanced Signal Integrity Tools EYE DOCTOR II ADVANCED SIGNAL INTEGRITY TOOLS Key Features Eye Doctor II provides the channel emulation and de-embedding tools Adds precision to signal integrity
Constructing a precision SWR meter and antenna analyzer. Mike Brink HNF, Design Technologist.
Constructing a precision SWR meter and antenna analyzer. Mike Brink HNF, Design Technologist. Abstract. I have been asked to put together a detailed article on a SWR meter. In this article I will deal
Designing the NEWCARD Connector Interface to Extend PCI Express Serial Architecture to the PC Card Modular Form Factor
Designing the NEWCARD Connector Interface to Extend PCI Express Serial Architecture to the PC Card Modular Form Factor Abstract This paper provides information about the NEWCARD connector and board design
An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices
An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices Application Note The number of devices that come with a built-in network interface card has risen steadily and will
Time and Frequency Domain Analysis for Right Angle Corners on Printed Circuit Board Traces
Time and Frequency Domain Analysis for Right Angle Corners on Printed Circuit Board Traces Mark I. Montrose Montrose Compliance Services 2353 Mission Glen Dr. Santa Clara, CA 95051-1214 Abstract: For years,
AVX EMI SOLUTIONS Ron Demcko, Fellow of AVX Corporation Chris Mello, Principal Engineer, AVX Corporation Brian Ward, Business Manager, AVX Corporation
AVX EMI SOLUTIONS Ron Demcko, Fellow of AVX Corporation Chris Mello, Principal Engineer, AVX Corporation Brian Ward, Business Manager, AVX Corporation Abstract EMC compatibility is becoming a key design
Data Transmission. Data Communications Model. CSE 3461 / 5461: Computer Networking & Internet Technologies. Presentation B
CSE 3461 / 5461: Computer Networking & Internet Technologies Data Transmission Presentation B Kannan Srinivasan 08/30/2012 Data Communications Model Figure 1.2 Studying Assignment: 3.1-3.4, 4.1 Presentation
Interfacing Intel 8255x Fast Ethernet Controllers without Magnetics. Application Note (AP-438)
Interfacing Intel 8255x Fast Ethernet Controllers without Magnetics Application Note (AP-438) Revision 1.0 November 2005 Revision History Revision Revision Date Description 1.1 Nov 2005 Initial Release
Multi-Gigabit Interfaces for Communications/Datacomm
Multi-Gigabit Interfaces for Communications/Datacomm Richard Dugan, Drew Plant Hewlett-Packard Integrated Circuit Business Division email: richard_dugan@hp.com, drew_plant@hp.com 802.3 Meeting, Austin
Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs
Application Note Design With the XRT83SL38 T1/E1 SH/LH LIU ICs Revision 1.3 1 REDUNDANCY APPLICATIONS INTRODUCTION Telecommunication system design requires signal integrity and reliability. When a T1/E1
KVPX CONNECTOR SERIES HIGH SPEED SIGNAL INTEGRITY REPORT
KVPX CONNECTOR SERIES HIGH SPEED SIGNAL INTEGRITY REPORT CONTENTS 1 2 3 3 3 3 3 4 4 4 5 6 7 HIGH SPEED DATA TRANSFER Market Drivers for High Speed Signal Integrity Key Characteristics Impedance Matching
Trends In Data Rate And Link Length In Evolving Optical Standards
Trends In Data Rate And Link Length In Evolving Optical Standards David Cunningham 22 nd September 2013 Outline Building and Data Centre link lengths Trends for standards-based electrical interfaces Data
Agilent Technologies N5393B PCI Express 2.0 (Gen2) Electrical Performance Validation and Compliance Software for Infiniium Oscilloscopes
Agilent Technologies N5393B PCI Express 2.0 (Gen2) Electrical Performance Validation and Compliance Software for Infiniium Oscilloscopes Data Sheet Table of Contents Features......................... 3
EECC694 - Shaaban. Transmission Channel
The Physical Layer: Data Transmission Basics Encode data as energy at the data (information) source and transmit the encoded energy using transmitter hardware: Possible Energy Forms: Electrical, light,
Understanding and Characterizing Timing Jitter. Primer
Understanding and Characterizing Timing Jitter Primer Primer Table of Contents Introduction...3 Section 1: The Consequences of Jitter...3 Computer Bus Design...3 Serial Data Link...4 Section 2: Just What
NRZ Bandwidth - HF Cutoff vs. SNR
Application Note: HFAN-09.0. Rev.2; 04/08 NRZ Bandwidth - HF Cutoff vs. SNR Functional Diagrams Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP
100 GBE AND BEYOND. Greg Hankins <ghankins@brocade.com> NANOG52. Diagram courtesy of the CFP MSA. NANOG52 2011/06/14
100 GBE AND BEYOND Greg Hankins NANOG52 Diagram courtesy of the CFP MSA. NANOG52 2011/06/14 Agenda and What s Covered in This Presentation Ethernet interface technology Overview
10/100/1000BASE-T SFP Transceiver
10/100/1000BASE-T SFP Transceiver Features Support 10/100/1000BASE-T operation in host systems with SGMII interface Up to 1.25Gbps bi-direction data links Hot-pluggable SFP footprint Fully metallic enclosure
Gigabit Ethernet on Copper Cabling Infrastructures
Gigabit Ethernet on Copper Cabling Infrastructures Overview of Gigabit Ethernet (1000Base-T) Ethernet was developed by the Xerox Corporation in the early 1970 s and has emerged as the dominant networking
Serial 12.5 Gbaud, 10 km SMF Link with Clock and Data Recovery IC
Serial 12.5 Gbaud, 10 km SMF Link with Clock and Data Recovery IC John Crow,, IBM Watson Research Center, jdcrow@us.ibm.com Dan Kuchta,, IBM Watson Research Center, kuchta@us.ibm.com Mounir Meghelli,,
Antennas & Propagation. CS 6710 Spring 2010 Rajmohan Rajaraman
Antennas & Propagation CS 6710 Spring 2010 Rajmohan Rajaraman Introduction An antenna is an electrical conductor or system of conductors o Transmission - radiates electromagnetic energy into space o Reception
AN952: PCIe Jitter Estimation Using an Oscilloscope
AN952: PCIe Jitter Estimation Using an Oscilloscope Jitter of the reference clock has a direct impact on the efficiency of the data transfer between two PCIe devices. The data recovery process is able
DTSB35(53)12L-CD20 RoHS Compliant 1.25G 1310/1550nm(1550/1310nm) 20KM Transceiver
产 品 规 格 书 Product Specification Sheet DTSB35(53)12L-CD20 RoHS Compliant 1.25G 1310/1550nm(1550/1310nm) 20KM Transceiver PRODUCT FEATURES Up to 1.25Gb/s data links FP laser transmitter for DTSB35(53)12L-CD20
1000BASE-T and 10/100/1000BASE-T Copper SFP Transceiver
1000BASE-T and 10/100/1000BASE-T Copper SFP Transceiver Features Up to 1.25Gb/s bi-directional data links Hot-pluggable SFP footprint TX Disable and RX Los/without Los function Fully metallic enclosure
Transmission of High-Speed Serial Signals Over Common Cable Media
Transmission of High-Speed Serial February 0 Introduction Technical Note TN066 Designers are often faced with moving serial data from one location to another, over moderate distances, and in the most efficient
Clock Recovery Primer, Part 1. Primer
Clock Recovery Primer, Part 1 Primer Primer Table of Contents Abstract...3 Why is Clock Recovery Used?...3 How Does Clock Recovery Work?...3 PLL-Based Clock Recovery...4 Generic Phased Lock Loop Block
Agilent Improved Method for Characterizing and Modeling Gigabit Flex-Circuit Based Interconnects. White Paper
Agilent Improved Method for Characterizing and Modeling Gigabit Flex-Circuit Based Interconnects White Paper Improved Method for Characterizing and Modeling Gigabit Flex-Circuit Based Interconnects Eric
How To Use A Sound Card With A Subsonic Sound Card
!"## $#!%!"# &"#' ( "#' )*! #+ #,# "##!$ -+./0 1" 1! 2"# # -&1!"#" (2345-&1 #$6.7 -&89$## ' 6! #* #!"#" +" 1##6$ "#+# #-& :1# # $ #$#;1)+#1#+
CLOCK AND SYNCHRONIZATION IN SYSTEM 6000
By Christian G. Frandsen Introduction This document will discuss the clock, synchronization and interface design of TC System 6000 and deal with several of the factors that must be considered when using
AC3200 INTELLIGENT BROADBAND AMPLIFIER
Kari Mäki 9.4.2013 1(7) AC3200 INTELLIGENT BROADBAND AMPLIFIER AC3200 is the latest leading-edge addition to AC family with extended frequency and gain ranges and integrated electrical controls in both
Managing High-Speed Clocks
Managing High-Speed s & Greg Steinke Director, Component Applications Managing High-Speed s Higher System Performance Requires Innovative ing Schemes What Are The Possibilities? High-Speed ing Schemes
Introduction to Digital Subscriber s Line (DSL)
Introduction to Digital Subscriber s Line (DSL) Professor Fu Li, Ph.D., P.E. Chapter 3 DSL Fundementals BASIC CONCEPTS maximizes the transmission distance by use of modulation techniques but generally
GSM frequency planning
GSM frequency planning Band : 890-915 and 935-960 MHz Channel spacing: 200 khz (but signal bandwidth = 400 khz) Absolute Radio Frequency Channel Number (ARFCN) lower band: upper band: F l (n) = 890.2 +
With the advent of Gigabit Ethernet
INTERNATIONAL JOURNAL OF NETWORK MANAGEMENT Int. J. Network Mgmt 2001; 11:139 146 (DOI: 10.1002/nem.396) The importance of modal bandwidth in Gigabit Ethernet systems By David N. Koon Ł This article deals
Suppression of Four Wave Mixing in 8 Channel DWDM System Using Hybrid Modulation Technique
International Journal of Electronic and Electrical Engineering. ISSN 0974-2174, Volume 7, Number 2 (2014), pp. 97-108 International Research Publication House http://www.irphouse.com Suppression of Four
How To Counter Noise Noise From A Low Voltage Differential Signaling Circuit
TDK EMC Technology Practice Section EMC Countermeasures of Low Voltage Differential Signaling Circuits TDK Corporation Magnetics Business Group Toshio Tomonari 1 Introduction Low Voltage Differential Signaling
Digital Systems Ribbon Cables I CMPE 650. Ribbon Cables A ribbon cable is any cable having multiple conductors bound together in a flat, wide strip.
Ribbon Cables A ribbon cable is any cable having multiple conductors bound together in a flat, wide strip. Each dielectric configuration has different high-frequency characteristics. All configurations
Twinax Intra Pair Skew Comparison Report Various Lengths and Competitors Tested
Twinax Intra Pair Skew Comparison Report Various Lengths and Competitors Tested 4.5 Average All Lengths Intra-Pair Skew Samtec vs. Competitors 4.0 3.5 Average pico-seconds 3.0 2.5 2.0 1.5 1.0 Competitor
CISCO DWDM XENPAK. Main features of the Cisco DWDM XENPAK include:
DATA SHEET CISCO DWDM XENPAK OVERVIEW The Cisco Dense Wavelength-Division Multiplexing (DWDM) XENPAK pluggable allows enterprise companies and service providers to provide scalable and easy-to-deploy 10
Jitter Budget for 10 Gigabit Ethernet Applications with SiTime SiT9120/1 Oscillators
February 2014 Jitter Budget for 10 Gigabit Ethernet Applications with SiTime SiT9120/1 Oscillators 1 Introduction The 10 Gigabit Ethernet (10GbE) specifications are defined in clauses 44 through 54 of
it4036f 120-ps Wideband Phase Delay Description Features Device Diagram Timing Diagram
Description The it436f is an ultra-wideband phase delay with an ECL topology to ensure high-speed operation that accepts either single-ended or differential data input. Its high output voltage, excellent
Data Receivers. Digital Data Receivers
Data Receivers Digital data receivers Equalization Data detection Timing recovery NRZ data spectra Eye diagrams Transmission line response Think of it as another example for a 247 project EECS 247 Lecture
Designing Fiber Optic Systems David Strachan
Designing Fiber Optic Systems David Strachan Everyone knows that fiber optics can carry a huge amount of data. There are more benefits to using fiber optics in broadcast applications than you might realize.
is the power reference: Specifically, power in db is represented by the following equation, where P0 P db = 10 log 10
RF Basics - Part 1 This is the first article in the multi-part series on RF Basics. We start the series by reviewing some basic RF concepts: Decibels (db), Antenna Gain, Free-space RF Propagation, RF Attenuation,
2. What is the maximum value of each octet in an IP address? A. 128 B. 255 C. 256 D. None of the above
1. How many bits are in an IP address? A. 16 B. 32 C. 64 2. What is the maximum value of each octet in an IP address? A. 128 B. 255 C. 256 3. The network number plays what part in an IP address? A. It
White Paper Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
White Paper Introduction The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2
A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.3, JUNE, 2013 http://dx.doi.org/10.5573/jsts.2013.13.3.185 A 1.62/2.7/5.4 Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO
MEASUREMENT UNCERTAINTY IN VECTOR NETWORK ANALYZER
MEASUREMENT UNCERTAINTY IN VECTOR NETWORK ANALYZER W. Li, J. Vandewege Department of Information Technology (INTEC) University of Gent, St.Pietersnieuwstaat 41, B-9000, Gent, Belgium Abstract: Precision
Shielding Effectiveness Test Method. Harbour s LL, SB, and SS Coaxial Cables. Designs for Improved Shielding Effectiveness
Shielding Effectiveness Test Method Harbour s LL, SB, and SS Coaxial Cables Designs for Improved Shielding Effectiveness Harbour Industries 4744 Shelburne Road Shelburne Vermont 05482 USA 802-985-3311
Product Specification. RoHS-6 Compliant 10Gb/s 850nm Multimode Datacom XFP Optical Transceiver FTLX8512D3BCL
Product Specification RoHS-6 Compliant 10Gb/s 850nm Multimode Datacom XFP Optical Transceiver FTLX8512D3BCL PRODUCT FEATURES Hot-pluggable XFP footprint Supports 8.5Gb/s and 9.95 through 10.5Gb/s* bit