FACULTY OF ENGINEERING LAB SHEET

Transcription

1 FACULTY OF ENGINEERING LAB SHEET DIGITAL COMPUTER DESIGN ECE4116 TRIMESTER 3 (2015/2016) : Introduction to VHDL Design on Quartus II and DE1 Board *Note: On-the-spot evaluation may be carried out during or at the end of the experiment. Students are advised to read through this lab sheet before doing experiment. Your performance, teamwork effort, and learning attitude will count towards the marks.

2 Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE1 Board Objective To learn how to create projects using Quartus II, design circuits and simulate them in the software. To implement the designed circuits on the DE1 Board. Introduction Quartus II is a Computer Aided Design (CAD) system by Altera Corporation which includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. CAD software makes it easy to implement a desired logic circuit by using a programmable logic device, such as a field-programmable gate array (FPGA) chip. The CAD flow involves the following steps: - Design Entry The desired circuit is specified either by means of a schematic diagram, or by using a hardware description language, such as VHDL or Verilog - Synthesis The entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA chip - Functional Simulation The synthesized circuit is tested to verify its functional correctness; this simulation does not take into account any timing issues - Fitting The CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between specific LEs - Timing Analysis Propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit - Timing Simulation The fitted circuit is tested to verify both its functional correctness and timing - Programming and Configuration The designed circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections Page 1 of 12

3 Figure 1 shows a typical FPGA CAD flow. Figure 1 Each logic circuit, or subcircuit, being designed with Quartus II software is called a project. The software works on one project at a time and keeps all information for that project in a single directory in the file system. Once a circuit design is completed, it can be compiled and a compilation report is produced. The Quartus II software provides a means to simulate the behavior of the designed circuit for ascertaining its correctness. This step is crucial, before implementing the circuit on the FPGA. A designed circuit can be simulated in two ways: functional and timing. Functional simulation assumes that logic elements and interconnection wires in the FPGA are perfect, thus causing no delay in propagation of signals through the circuit. Timing simulation takes all propagation delays into account. Typically, functional simulation is used to verify the functional correctness of a circuit as it is being designed. Page 2 of 12

4 The Altera DE1 board features the Cyclone II 2C20 FPGA. All the components on the board are connected to pins of this chip, allowing the user to control all aspects of the board s operation. The specifications: FPGA - Altera Cyclone II EP2C20F484C7 FPGA - EPCS4 serial configuration device I/O Devices - Built-in USB Blaster for FPGA configuration - VGA DAC (4-bit R-2R per channel) with VGA out connector - PS/2 mouse or keyboard connector - 24-bit CD-Quality Audio CODEC with line-in, line-out, and microphone-in jacks - RS-232 Transceiver and 9-pin connector - RS-232 Transceiver and 9-pin connector Memory - 8-MB SDRAM KB SRAM - 4-MB flash memory - SD memory card slot Switches, LEDs, Displays, and Clocks - 4 push-button switches - 10 toggle switches - 10 red LEDs - 8 green LEDs - Four 7-segment displays - 24-MHz, 27-MHz and 50-MHz oscillators, external clock input The DE1 board can be used to implement circuits designed using the Quartus II CAD system. Page 3 of 12

5 Exercises Exercise 1: Getting Started with the Switches The DE1 board provides 10 toggle switches, called SW9 0, that can be used as inputs to a circuit, and 10 red lights, called LEDR9 0, that can be used to display output values. Steps: 1. Start the Quartus II program and create a new project using the New Project. Follow each step of the wizard and select Cyclone II EP2C20F484C7 as the target chip, which is the FPGA chip on the Altera DE1 board (see Figure 2). Figure 2 2. Create a VHDL entity (a new VHDL file) and enter the following code: LIBRARY ieee; USE ieee.std_logic_1164.all; -- Simple module that connects the SW switches to the LEDR lights ENTITY part1 IS Page 4 of 12

6 PORT ( SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); -- red LEDs END part1; ARCHITECTURE Behavior OF part1 IS BEGIN LEDR <= SW; END Behavior; Save the file as part1.vhd in the project directory and include it in the project (see Figure 3). Figure 3 3. Set the pin assignments by importing the file DE1_pin_assignments.csv by selecting Assignments Import Assignments, then selecting the file in the window (see Figures 4) Figure 4 Page 5 of 12

7 4. Compile the project by selecting Processing Start Compilation. 5. Set the current vhdl file as the top level entity by selecting Project Set as Top-level Entity. 6. Download the compiled circuit into the FPGA chip: a) Connect the DE1 board to the computer using the USB cable. Turn the power on. b) Select Tools Programmer to view the Programmer window (see Figure 5). Ensure the hardware selected is USB-Blaster and the mode is JTAG. c) Click Start. Figure 5 6. Test the functionality of the circuit by toggling the switches and observing the LEDs. Specific Task 1: Describe the behaviour of the LEDs when the switches are toggled. Explain how the observed behaviour verifies the functionality of the circuit. Exercise 2: Multiplexers Part (a) of Figure 6 shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. If s = 0 the multiplexer s output m is equal to the input x, and if s = 1 the output is equal to y. Part (b) shows the truth table for this multiplexer, and part (c) its circuit symbol. Page 6 of 12

8 Figure 6 The multiplexer can be described by the following VHDL statement: m <= ( NOT (s) AND x ) OR (s AND y); Figure 7 shows an 4-bit wide 2-to-1 multiplexer. The circuit has two 4-bit inputs X and Y and produces the 4-bit output M. If s = 0 then M = X, while if s = 1 then M = Y. Steps: 1. Create a new Quartus II project for the multiplexer circuit. 2. Include a VHDL file for the 4-bit wide 2-to-1 multiplexer in the project. Use switch SW9 on the DE1 board as the s input, switches SW3 0 as the X input and SW7 4 as the Y input. Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG Import the required pin assignments for the DE1 board as per step 3 of Exercise Compile the project. 5. Download the compiled circuit into the FPGA chip. Test the functionality of the 4-bit wide 2- to-1 multiplexer by toggling the switches and observing the LEDs. Page 7 of 12

9 Specific Task 2: Write the VHDL entity to describe the circuit in Figure 7 and save as a VHDL file to be included into the project as per step 2. Describe the behaviour of the LEDs when the switches are toggled. Explain how the observed behaviour verifies the functionality of the circuit. x 3 y 3 m 3 x 2 y 2 m Figure 7 Exercise 3: Latches and Flip-flops Part A Altera FPGAs include flip-flops that are available for implementing a user s circuit. However, storage elements can be created in an FPGA without using its dedicated flip-flops. Figure 8 depicts a gated RS latch circuit. A style of VHDL code that uses logic expressions to describe this circuit is given is as follows: - - A gated RS latch LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ls_latch IS PORT (Clk, R, S : IN STD_LOGIC; Q : OUT STD_LOGIC); END ls_latch; ARCHITECTURE Structural OF ls_latch IS SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC ; ATTRIBUTE keep : boolean; Page 8 of 12

10 ATTRIBUTE keep of R_g, S_g, Qa, Qb : SIGNAL IS true; BEGIN R_g <= R AND Clk; S_g <= S AND Clk; Qa <= NOT (R_g OR Qb); Qb <= NOT (S_g OR Qa); Q <= Qa; END Structural; Figure 8 To preserve internal signals such as R-g and S_g in the implemented circuit, it is necessary to include a compiler directive in the code. The directive keep is included by using a VHDL ATTRIBUTE statement. It instructs the Quartus II compiler to use separate logic elements for each of the signals R_g, S_g,Qa, and Qb. Compiling the code produces the circuit with four 4- input lookup tables (LUTs) as shown in Figure 9. Figure 9 Page 9 of 12

11 Figure 10 shows the circuit for a gated D latch. Steps: 1. Create a new Quartus II project. Figure Write a VHDL file, using the style of the LS latch code given, for the gated D latch. Use the keep directive to ensure that separate logic elements are used to implement the signals R, S_g,R_g,Qa, and Qb. 3. Select as target chip the Cyclone II EP2C20F484C7 and compile the code. Examine the implemented circuit by selecting Tools Netlist Viewers RTL Viewer. 4. Create another new Quartus II project which will be used for implementation of the gated D latch on the DE1 board. This project should consist of a top-level entity that contains the appropriate input and output ports (pins) for the DE1 board. Instantiate the latch in this toplevel entity. Use switch SW0 to drive the D input of the latch, and use SW1 as the Clk input. Connect the Q output to LEDR0. 5. Recompile the project and download the compiled circuit onto the DE1 board. Test the functionality of your circuit by toggling the D and Clk switches and observing the Q output. Specific Task 3a: Write the VHDL file for the gated D latch in Figure 10 as specified in step 2. Describe the Q output when D and Clk switches are toggled. Explain how the observed behaviour verifies the functionality of the circuit. Page 10 of 12

12 Part B Figure 11 shows the circuit for a master-slave D flip-flop. To simulate the circuit, perform the following steps. Steps: 1. Create a new Quartus II project. Generate a VHDL file that instantiates two copies of your gated D latch entity from Part A to implement the master-slave flip-flop. 2. Include in your project the appropriate input and output ports for the Altera DE1 board. Use switch SW 0 to drive the D input of the flip-flop, and use SW1 as the Clock input. Connect the Q output to LEDR0. 3. Compile your project and use the RTL Viewer to examine the D flip-flop circuit. 4. Download the circuit onto the DE1 board and test its functionality by toggling the D and Clock switches and observing the Q output. Figure 11 Specific Task 3b: Generate the VHDL file for the master-slave flip-flop in Figure 11 as specified in step 1. Describe the Q output when D and Clock switches are toggled. Explain how the observed behaviour verifies the functionality of the circuit. Page 11 of 12

13 Report writing guidelines Your lab report must be typed and must contain the following sections: Report cover page Use the report cover page format in the FOE lab website. Download the template at Brief Introduction Write a short description in your own words about the experiment, including the objectives. Do not reproduce the text / steps in this lab sheet. Results and Discussion Provide the VHDL codes and subsequent observations listed under Specific Task for all the exercises. Discuss and/or analyse the results. Conclusion Conclude your report with a brief summary on the knowledge and skills that you have acquired from this lab. *Exercises are adapted from Altera s support documents for Quartus II and DE1 Boards. Page 12 of 12