Compensating a PFC Stage

Transcription

1 Compensating a PFC Stage

2 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

3 Output Voltage Low Frequency Ripple V out P in (t) + - P in,avg I in (t) V in (t) The load power demand is matched in average only A low frequency ripple is inherent to the PFC function

4 PFC Stages are Slow Systems The output ripple must be filtered to avoid current distortion. In practice, the loop frequency is selected in the range of 0 Hz, which is very low. Even if the bandwidth is low, the loop must be compensated!

5 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

6 A Simple Representation We will consider the PFC stage as a system delivering a power under an input rms voltage and a control signal V in(rms) P out PFC stage V control Details of the power processing are ignored: Operation mode (CrM, CCM, Voltage or Current mode ) 100% efficiency, only the average power contribution of the sinusoidal signals is considered

7 A Simple Large Signal Model Let s represent the PFC stage as a current source delivering the power to the bulk capacitor and the load: I D P ( ) in avg V out Bulk Capacitor r C C bulk R LOAD Load P in(avg) depends on V control (always), on V in(rms) (in the absence of feedforward) and sometimes on V out 3 possible sources of perturbations: V control, V out and V in(rms).

8 NCP1605 Frequency Clamped Critical Conduction Mode (FCCrM) Key features for a master PFC: High voltage current source, Soft-Skip TM during standby mode pfcok signal, dynamic response enhancer Bunch of protections for rugged PFC stages Markets: high power AC adapters, LCD TVs Rbo1 Rout Rout1 Vout Rbo Cbo CVctrl FB OVP HV Rovp1 Rovp CVref L1 D1 Vout STBY control Vcc Ac line Cin Rzcd Ct Vcc pfcok M1 Cbulk LOAD EMI Filter Rocp Cosc 8 9 Rdrv pfcok Icoil Rcs Communication signals

9 NCP1605 Follower Boost Voltage mode operation: the circuit adjusts the power level by modulating the MOSFET conduction time The charge current of the timing capacitor is proportional to the FB square and hence to (V out ) : where : I ch arge t V I out V out, nom V out,nom is the V out regulation voltage I t is a 370-µA current source The on-time is inversely proportional to (V out ) allowing the Follower boost function: Ct Vton Vout, nom ton I t V out

10 NCP Power Expression The control signal is V F offset down and divided by 3 to form V REGUL used in the PWM section FB 0.955*Vref Vref Vout low detect - + Error Amplifier - + pfcok 00 µa +/-0µA Vcontrol OVLflag1 OFF V F R V REGUL V F 3V R Hence due to the follower boost function, the power is inversely dependent on (V out ) : P in( avg ) ( ) t in( rms) Vout, nom control F C V V V L I t V out 3

11 NCP Large Signal Model Let s represent the PFC stage as a current source delivering the power to the bulk capacitor and the load: I I D D Pin( avg ) V out Replacing P in,avg by its expression of slide 10 ( ) Ct V out, nom Vin( rms) Vcontrol V F 6 L I 3 t V out r C R LOAD constants Time varying terms C bulk 3 sources of perturbations: V CONTROL, V out and V in(rms).

12 Small Signal Model A large signal model is nonlinear because I D is formed of the multiplication and division of V control, V in,rms and V out. This model needs to be linearized to assess the AC contribution of each variable The model is perturbed and linearized around a quiescient operating point (DC point)

13 Considering Variations Around the DC Value Let s omit the perturbations of the line magnitude (assumed constant) Let s consider small variations around the DC values for V out and V control : $ ID $ ID $ We then obtain: i v + v V V D CONTROL out control out I D + $ i D I : D $ I where $ i v + D v$ V V D control out control out r C C bulk R LOAD V out nom + v$, out

14 Deriving a Small Signal Model The DC portion can be eliminated The partial derivatives are to be computed at the DC point that is for: V control that is the control signal DC value for the considered working point V out,nom that is the nominal (DC) output voltage Replacing the derivations by their expression, we obtain: $ v out I I D v$ V 1 out out I I D v$ V control control r C R LOAD I 1 computed for V control DC point I computed for V out DC point that is V out,nom C bulk

15 Contribution of the V out Perturbations Depending on the controller scheme P f ( Vin( rms), Vcontrol ) n0 for NCP1607 n1 for NCP1654 (predictive CCM PFC for which Pin, avg ) n for NCP1605 (follower boost see slide 10) At the DC point Finally: in, avg ID where n 0,1 or V n+ 1 out $ ( ) ( ) ( V ) I n+ 1 f V, V n+ 1 P n + 1 I v v v v in( rms) control in( avg ) $ ( ) $ 1 D out out n out out V + out ( Vout ) R ( V, ) LOAD V V out nom out out Pin( avg ) Vout Vout, nom and R out, nom $ ( ) V control ( Vout, nom ) V V out in, rms 1 LOAD

16 Resistors Hence, the small signal model can be simplified as follows: I I D v$ V control control R LOAD n + 1 r C R LOAD $ v out C bulk V out AC contribution Load Noting that: RLOAD R RLOAD n+ 1 n+ LOAD the model can be further simplified

17 Finally The small signal model is: 1 R ( ) LOAD + s rc C Zs bulk n + R 1 LOAD C s bulk + n + I I D v$ V where : control I D P control in, avg V out r C C bulk R LOAD n + $ v out The transfer function is: v$ out RLOAD I D 1+ s rc C bulk $ v n+ V control control R 1 LOAD C s bulk + n +

18 NCP1605 Example The large signal model instructed that: I D Pin avg t out, nom Vin( rms) Vcontrol V F V 6 3 out L It V out ( ) C V ( ) Hence: n ( ) V out n+ 1 term ( ) I Ct Vin( rms D ) V 6 L I V control t out, nom

19 Finally: NCP Small Signal Model $ v out I ( ) Ct Vin( rms) v$ 6 L I V t out, nom CONTROL r C R LOAD 4 C bulk The transfer function is: v$ ( ) v$ RLOAD Ct Vin( rms) 1+ s r out C C bulk 4 L It Vout, nom R 1 LOAD C s bulk + 4 CONTROL

20 Power Stage Characteristic Bode Plots Gain (db) ( ) R ( ( )) LOAD LOAD Ct t V Vin( rms ) in rms 0 log 0 log 4 L I µ L t V K out FB V, nom out -0 db/dec Asymptotic representation Frequency (Hz) 0 0 Phase ( ) -90 f p 0 π R LOAD C bulk f z 0 π r C 1 C bulk Frequency (Hz)

21 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

22 Compensation Phase Boost The zero brought by the bulk capacitor ESR is too high to bring some phase margin. It is ignored. The PFC open loop inherently causes a -360 phase shift: Power stage pole -90 Error amplifier inversion -180 Compensation origin pole -90 The compensation must then provide some phase boost A type- compensation is recommended

23 Type- Compensation The NCP1605 embeds a transconductance error amplifier (OTA) V OUT R 1 C 1 R fbu R fbl V CONTROL C FB V REF I CONTROL OTA to PWM comparator 1 No direct influence of the R fbu impedance on the compensation Only the feedback scale factor interferes C << C f z 1 f p f p 1 R 0 1 π R 1 π R 1 π R C 1 1 C 1 C 0 1 pole at the origin V V out, nom ref G EA V ref is the reference voltage (generally.5 V in ON semi devices) G EA is the OTA (00-µS transconductance gain for NCP1605, NCP1654 and NCP1631)

24 Type- Characteristic - Example Gain (db) db G c 0 db 51 f p and f z1 set the phase boost magnitude and location (frequency) The phase boost peaks at: that is 7 Hz ( fphb fz1 fp ) phase boost (60 ) The phase boost is: tan 1 fphb 1 fphb tan f z f p 180 Phase ( ) m 100m k 10k 100k frequency in hertz f z1 : compensation zero (6 Hz) f f z 1 p f p : high frequency pole (90 Hz) The origin pole f p1 adjusts the gain G c at the phase boost frequency

25 Phase Boost at the Crossover Frequency φ B 1 f 1 tan c f tan c f f z1 p φ B 15 φ B The lower f z1 and/or the higher f p, the higher the phase boost (max. value: 90 ) -70 Assuming the PFC power stage pole is well below the crossover frequency (f c ), the phase boost equates the phase margin (φ m φ B ) 0m k 10k 100 f i h f z1 f z1 f c f p f p Target a phase boost between 45 and 75

26 Gain Considerations 0 db A low frequency attenuates more sharply the line ripple In the red trace, the distance between the zero and the pole frequencies is increased Both characteristics generate the same attenuation at the crossover frequency Lower gain with a low frequency zero f z1 f z1 f p f p f c.f line The lower the f z1 frequency, the lower the gain in the low frequency region The higher f p, the lower the (.f line ) ripple rejection

27 Type- Compensator - Summary The zero should not be placed at a too low frequency (not to penalize the low-frequency gain) The high frequency pole must be placed at a frequency low enough to attenuate the line ripple The phase boost (and phase margin) depends on the zero and high-frequency pole locations The origin pole is set to force the open loop gain to zero at the targeted crossover frequency

28 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

29 Compensating for the Full Range?... The static gain depends on the load and if there is no feedforward, on the line magnitude G static( db) ( ( )) R LOAD t in rms 0 log LOAD I R C V D 0 log n V + control 4 L It Vout, nom (NCP1605) The power stage pole varies as a function of the load: f p0 n + π R C π R C LOAD bulk LOAD bulk (NCP1605) What is the worst case when closing the loop?

30 Load Influence on the Open Loop Plots Let s increase R LOAD ( R α R with α > ) LOAD LOAD1 1 0 log( α ) -0 db/dec Static gain Gain (db) Unchanged Gain and Phase at the targeted crossover frequency Frequency (Hz) R LOAD1 R LOAD Asymptotic representation f p0 f p0 α 1 f c and φ m are not affected! f c f z0 1 π r C C Frequency (Hz) bulk Phase ( )

31 Line Influence on the Open Loop Plots No feedforward (e.g. NCP1607) and ( Vin( rms ) β Vin ( rms )1 with β > 1) -0 db/dec 40 log( β ) Static gain Gain (db) Unchanged Phase but increased gain (multiplied by β*β ) Frequency (Hz) V in(rms)1 V in(rms) Phase ( ) Asymptotic representation f p0 n + π R C LOAD bulk f c f z0 1 π r C C Frequency (Hz) bulk The loop crossover frequency is β increased

32 Load and Line Considerations Compensate at full load Same crossover frequency at lighter loads The zero frequency is set optimally (not at a too low frequency) Compensate at high line High line is the worst case as in the absence of feedforward, the static gain is proportional to V in( rms) ( f HL c) ( ) HL fc LL ( Vin( rms) ) LL Where HL stands for Highest Line and LL for Lowest Line This leads to: ( V ( )) in rms ( ) In universal mains applications, the high-line crossover frequency is 9 times higher than the low-line one: ( f ) ( f ) 9 ( f ) c HL c LL c LL

33 Crossover Frequency Selection In the absence of feedforward, f f is a good option f With feedforward, ( fc ) HL line is rather selected for a better attenuation of the low frequency ripple ( ) c HL line Get sure that on the line range, the PFC boost pole remains lower than the crossover frequency at full load! f p0 ( f ) c LL If not, increase C bulk

34 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

35 Compensation Techniques Several techniques exist: manual placement, k factor (Venable) + Systematic - The PFC boost gain is to be computed at f c - No flexibility in the zero and high pole locations Pole and zero cancellation: f c f k fz1 k p Place the compensation zero so that it cancels the power stage pole: Force the pole at the origin to cancel the PFC boost gain when (f f c ) Adjust the phase margin with the high frequency pole

36 Pole and Zero Cancellation Gain (db) -0 db/dec K 0 Frequency (Hz) Power stage Open Loop -40 db/dec ESR of the bulk capacitor Phase ( ) φ -360 m Frequency (Hz) f f z 1 p 0 f p f f 0 f line z c The higher f p, the larger the phase margin The lower f p, the better the rejection of the low frequency ripple φ 45 if fp fc. m

37 Poles and Zero Placement Design the compensation for full load, high line: R LOAD R LOAD ( min) Place the origin pole to cancel K 0, the static gain at f c : Place the zero so that it cancels the PFC boost pole f f for R R c p0 LOAD LOAD(min) K0 where : ( ) v$ out 1+ s rc C K bulk $ 0 v R CONTROL LOAD(min) Cbulk 1+ s n + f f for R R z1 p0 LOAD LOAD(min) Place f p to obtain the targeted phase margin: f p f c ( φ ) tan 90 m

38 Example A wide mains, 150-W application driven by the NCP1605 V out,nom 390 V (V in(rms) ) LL 90 V (V in(rms) ) HL 65 V L 150 µh C t 4.7 nf C bulk 100 µf r C 500 mω (ESR) f c 50 Hz and Φ m high line (65 V) ( ) v$ 1+ s r LOAD t in( rms) out C C R C V K bulk $ 0 where : K0 v R 4 CONTROL 1 LOAD Cbulk L It V + s out, nom 4 R LOAD ( ) V out, nom 390 ( min) 1 kω P 150 ( ) max out, nom 0 V 6 ref G EA out V 390 R 780 kω ( OTA) K RLOAD(min) Ct V 0(min) in( rms) C1 HL.59µF >. µf π f R π f R 4 L I V π k 4 150µ 370µ 390 c ( n ) C1 ( ) ( φ ) ( ) ( ) c 0 t out, nom R 3 6 LOAD(min) C bulk R kω > 1 kω C tan 90 m tan π f R π c nf > 150 nf f 93mHz f 6Hz f 88Hz p1 z1 z1 π R0 C1 π R1 C1 π R1 C

39 Simulation Validation The simulation circuit is based on the large signal model: Vout B6 Current {Ct*Vbulk*Vbulk*Vrms*Vrms}*V(control)/(6*{L}*370u*V(Vout)*V(Vout)*V(Vout)) R10 50m Vout Rload {Vbulk*Vbulk/Pout} Large signal model of the NCP1605- driven PFC stage C5 100u IC {Vrms*1.414} 1 Vin 6 V4 AC 1 C6 1kF L1 1kH Generation and injection of the ac perturbation EAout control B5 Voltage V(EAout) 4 R1 1k C3.u EAout C1 150nF R B1 Current {gm}*(.5-v(fb)) R3 {Rlower} 5 R4 {Rupper} FB Feedback and regulation circuit (including type- compensation)

40 Open Loop Characteristic Full Load V in(rms) 90 V f c 5 V in(rms) 65 V f c 7 V in(rms) 90 V 0 db Gain (db) V in(rms) 65 V 40 db 6 10 mhz 100 mhz 1 Hz 10 Hz 100 Hz 1 khz 10 khz 100 khz Phase ( ) φ m φ m 87 0

41 Open Loop Characteristic Mid Load V in(rms) 90 V f c 5 V in(rms) 65 V f c 8 V in(rms) 90 V 0 db Gain (db) V in(rms) 65 V 40 db 10 mhz 100 mhz 1 Hz 10 Hz 100 Hz 1 khz 10 khz 100 khz 1 Phase ( ) φ m φ m 69 0

42 Experimental Results at Full Load A 19 V / 7 A loads the PFC stage The downstream converter swings between 6.3 A and 7.7 A (+/-10%) with a A/µs slope Ac line current (5 A/div) V in,rms 90 V Ac line current ( A/div) V in,rms 65 V Bulk Voltage (0 VA/div 380-V offset) Bulk Voltage (0 VA/div 380-V offset) 37 V < V bulk < 396 V 375 V < V bulk < 394 V Load Current (5 A/div) Load Current (5 A/div) The high-line, larger bandwidth reduces the V bulk deviations and speedsup the output voltage recovery

43 Experimental Results at Medium Load A 19 V / 7 A loads the PFC stage The downstream converter swings between 3.1 A and 3.9 A (+/-10%) with a A/µs slope Ac line current ( A/div) V in,rms 90 V Ac line current (1 A/div) V in,rms 65 V Bulk Voltage (0 VA/div 380-V offset) Bulk Voltage (0 VA/div 380-V offset) 376 V < V bulk < 39 V 379 V < V bulk < 390 V Load Current ( A/div) Load Current ( A/div) The circuit still exhibits a first order response

44 Abrupt Load Changes A 19 V / 7 A loads the PFC stage The downstream converter swings from 7.0 A to 3.5 A ( A/µs slope) Ac line current ( A/div) V in,rms 90 V Ac line current ( A/div) V in,rms 30 V 365 V < V bulk < 411 V OVP 365 V < V bulk < 404 V Bulk Voltage (0 VA/div 380-V offset) V control ( V/div) Bulk Voltage (0 VA/div 385-V offset) V control (1 V/div) Load Current (5 A/div) Load Current (5 A/div) The dynamic response enhancer speeds-up the loop reaction in case of a large undershoot Implemented in NCP1605 (FCCrM), NCP1654 (CCM) and NCP1631 (Interleaved) The dynamic response enhancer reduces the undershoot at low line

45 Agenda Introduction Deriving a small-signal model General method Practical example: NCP1605-driven PFC stages Compensating the loop Type- compensation Influence of the line and power level Computing the compensation Practical example Conclusion

46 Conclusion General considerations were illustrated by the case of NCP1605-driven PFC stages A small signal model of PFC boosts can be easily derived The proposed method is independent of the operating mode A type- compensation is recommended If no feed-forward is implemented, the loop bandwidth and phase margin vary as a function of the line magnitude The crossover frequency does not vary as a function of the load A resistive load can be used for the computation even if the PFC stage feeds a power supply (negative impedance) See back-up

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