Computer Organization I. Lecture 3: von Neumann Architecture (Part II) von Neumann Architecture

Transcription

1 Computer Organization I Lecture 3: von Neumann Architecture (Part II) von Neumann Architecture

2 Overview Last Lecture (Part I of von Neumann Computer) Basic Principle of von Neumann computer Structure and Operation of Memory Subsystem This Lecture (Part II of von Neumann Computer) Machine Language Instruction Instruction Processing

3 Objectives Familiar with von Neumann instruction set Familiar with von Neumann instruction processing Be able to write a simple program using von Neumann machine language instruction set

4 Machine Language Instructions (cont.) A machine language instruction = Opcode + Operands For Example: ADD X, Y, in which ADD is Opcode, X and Y is Operands Opcode ADD tell the ALU to execute the add function X and Y is the address of memory cell So, execute ADD X,Y means ADD content of memory locations X and Y, and store back in memory location Y.

5 Machine Language Instructions (cont.) suppose X=4 and Y=6, con(x) = 6 and con (Y) =2 After execute the instruction ADD X,Y before execute instruction after execute instruction X Y Content of address X is 6 Content of address Y is 2

6 Instruction Set Design von Neumann Architecture Reduced Instruction Set Computers (RISC) Instruction set as small and simple as possible. Minimizes amount of circuitry --> faster computers Complex Instruction Set Computers (CISC) More instructions, many very complex Each instruction can do more work, but require more circuitry.

7 Typical Machine Instructions Notation: von Neumann Architecture We use X, Y, Z to denote address of RAM cells Assume only one register R (for simplicity) Use English-like descriptions (should be binary) Data Transfer Instructions LOAD X Read content of memory location X to R STORE X Write content of R to memory location X MOVE X, Y Copy content of memory location X to location Y

8 Typical Machine Instructions (cont.) For example: LOAD X means read the content of memory location X to register R Suppose X=2, and memory with address 4 is assigned as R X memory space after execute instruction register R

9 Typical Machine Instructions (cont.) Arithmetic ADD X, Y, Z CON(Z) = CON(X) + CON(Y) ADD X, Y CON(Y) = CON(X) + CON(Y) ADD X R = CON(X) + R similar instructions for other operators, e.g. SUBTR,OR,... Compare COMPARE X, Y Compare the content of memory cell X to the content of memory cell Y and set the condition codes (CCR) accordingly.

10 Typical Machine Instructions (cont.) For example: Compare X, Y means compare the content of memory cell X to the content of memory cell Y and then set the condition codes (CCR) accordingly. Suppose X=2, Y=4, and address 5 is assigned as CCR CCR X Y memory space after execute instruction con(x)=8,con(y)=0,and the logic result of compare instruction is true, the second bit in CCR is the flag of greater than, it set to 1 if greater than is true

11 Typical Machine Instructions (cont.) Branch JUMP X Load next instruction from memory location X JUMPGT X Load next instruction from memory location X only if GT flag in CCR is set, otherwise load statement from next sequence location as usual JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ Control HALT Stop program execution.

12 An Example using Machine Instruction Pseudo-code: Set A to B + C Assuming variable: register R A stored in memory cell 1, B stored in memory cell 2, C stored in memory cell 3, and address 4 is assigned to register R 000 How to use machine language instruction 001 A to implement set A 010 B to B + C? 011 C LOAD ADD STORE 1

13 An Example using Machine Instruction (cont.) A 001 A 010 B 010 B register R 011 C LOAD C 100 B

14 An Example using Machine Instruction (cont.) A 001 A 010 B 010 B register R 011 C 100 B ADD C 100 B + C

15 An Example using Machine Instruction (cont.) A 001 B + C 010 B 010 B register R 011 C 100 B + C STORE C 100 B + C STORE X Load content of R to memory location X

16 - what is structure of control unit subsystem? PC (Program Counter): stores the address of next instruction to fetch IR (Instruction Register): stores the instruction fetched from memory Instruction Decoder: Decodes instruction and activates necessary circuitry PC IR +1 Instruction Decoder

17 - what is structure of control unit subsystem? An Example about PC Register and IR register Suppose address 4 is assigned to PC register and address 5 is assigned to IR register PC Register IR Register Binary code of instruction e.g. LOAD X means instruction LOAD X

18 Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Execute operation Store result

19 Example: Instruction Processing of ADD X,Y ADD X,Y means add content of memory locations X and Y, and store back in memory location Y. Instruction ADD X,Y stored in memory as: ADD X Y

20 suppose address 4 is assigned to MAR (memory address register), address 5 is assigned to MDR (memory data register), address 6 is assigned to IR (instruction register) and address 63 is assigned to PC (program counter) register MA R MD R IR PC Location of instruction program ADD X,Y

21 Instruction Processing: FETCH MA R MD R IR PC von Neumann Architecture Load next instruction ADD (at address stored in PC) from memory into Instruction Register (IR) Load contents of PC into MAR. 2. Copy the content of memory cell with specified address into MDR 3. Read the content of MDR to IR 4. increment PC to PC+1 to point the next instruction in sequence.

22 Instruction Processing: DECODE First identify the opcode in IR, e.g. the first 8 bits means ADD under the defined instruction set ADD X Y Depending on opcode, identify other opreands from the remaining bits, e.g. the address of X is 0011 the address of Y is 0100 F D EA OP EX S

23 Instruction Processing: Evaluate Address For instructions that require memory access, compute address used for access no address evaluation (calculation) for ADD since we know the result will be stored in Y F D EA Y OP EX S

24 Instruction Processing: FETCH OPERANDS Obtain source operands needed to perform ADD operation e.g. read the content of X and Y to MDR X Y MD R F D EA OP EX S

25 Instruction Processing: EXECUTE Perform the operation using the source operands e.g. Obtain the content of MDR and then send them to ALU for calculation F D EA OP EX S

26 Instruction Processing: STORE Write results to destination (register or memory) e.g. result of ADD X,Y will be placed in destination Y F D EA X Y OP EX S

27 von Neumann Architecture

28 - instruction set of von Neumann machine? Opcode Operation Meaning 0000 LOAD X CON(X) --> R 0001 STORE X R --> CON(X) 0010 CLEAR X 0 --> CON(X) 0011 ADD X R + CON(X) --> R 0100 INCREMENT X CON(X) > CON(X) 0101 SUBTRACT X R - CON(X) --> R 0101 DECREMENT X CON(X) > CON(X) 0111 COMPARE X If CON(X) > R then GT = 1 else 0 If CON(X) = R then EQ = 1 else 0 If CON(X) < R then LT = 1 else JUMP X Get next instruction from memory location X 1001 JUMPGT X Get next instruction from memory loc. X if GT=1... JUMPxx X xx = LT / EQ / NEQ 1101 IN X Input an integer value and store in X 1110 OUT X Output, in decimal notation, content of mem. loc. X 1111 HALT Stop program execution

29 Summary Principle of von Neumann Computer Basics of Machine Language Instruction Set Instruction Processing of von Neumann Computer

30 Thank you Q & A