SPICE circuit simulations are a powerful design

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1 Evaluating TVS Protection Circuits with SPICE A transient-voltage-suppression diode macromodel offers greater accuracy than a standard diode SPICE model. By Jim Lepkowski, Senior Applications Engineer, ON Semiconductor, Phoenix, and William Lepkowski, University of Arizona, Tucson, Ariz. SPICE circuit simulations are a powerful design tool to analyze a system s immunity against conducted EMI surge voltages. SPICE can serve as a valuable tool to validate and optimize the performance of surge-protection circuits using transient-voltage-suppression (TVS) avalanche diodes. The small size, fast response time, low clamping voltage and low cost of TVS diodes provides for an effective solution to solve surge problems. A comparison of SPICE simulations with bench tests demonstrates the ability of TVS avalanche diodes to clamp the surge voltages caused by noise sources such as inductive devices and load switching. I Versus V Characteristics Zener and TVS avalanche diodes have similar electrical characteristics; however, there are significant differences between the two devices. A zener is designed to regulate a steady-state voltage, while a TVS diode is designed to clamp a transient-surge voltage. In addition, TVS diodes typically have a larger junction area than a standard zener, Breakdown Region V C V BR V RWM Leakage Region Current Fig.. A TVS avalanche diode s I versus V characteristics. I F I R IT I PP V F Forward Region Voltage Anode + 7 ID V D - Cathode I F D Anode 7 L I D 2 I L R L Cathode EV EV- 8 Fig. 2. The TVS avalanche diode SPICE macro-model is constructed by combining standard Spice devices. which provides the ability to absorb high peak energy. The current versus voltage relationship of a TVS diode is shown in Fig.. The graph in Fig. depicts various diode parameters. I F is the forward current and V F is the associated forward voltage at that current. I R is the reverse leakage current and V RWM is the reverse-working voltage at I R. Typically, V RWM (typ.).8 V BR. Other parameters include I T, the test current; V BR, the breakdown voltage at I T ; and I PP, the maximum reverse peak pulse current. I PP is typically specified with either the 8 2-µs or -µs surge pulse. In addition, V C is the clamping voltage at I PP. TVS Diode SPICE Models The majority of the TVS avalanche diode SPICE models available are created with the SPICE D diode statement. There are several restrictions that limit the accuracy of using the diode D statement to model a TVS avalanche diode. First, the diode statement does not have a provision for defining a separate series resistance for the forward- and 3 4 R Z I R D2 I BV EV=[I BV x R BV )-V D3 ] R BV D3 I T 44

2 D B D A GND D D D C I/O I/O 2 Fig. 3. The houses dual line bidirectional TVS diodes in a SOT-23 package. reverse-bias breakdown regions. The resistances in the two regions are not equal; thus, it is not possible to accurately model the slope of the current versus voltage characteristic in both regions. Next, the D statement does not have a variable to model the variance of the breakdown voltage with temperature. Table provides the variables available with the PSPICE D diode model. Macro-Model Subcircuit A TVS diode macro-model offers several advantages over the standard diode model available in SPICE, including a more accurate representation of the breakdown characteristic. TVS macro-models are created by combining standard SPICE devices into a subcircuit. Fig. 2 shows a schematic for a macro-model of a TVS avalanche diode. A PSPICE netlist for this model appears below. This particular netlist models the, a dual, bidirectional voltage suppressor from Phoenix-based ON Semiconductor (Fig. 3). ** * PSPICE macro-model *Bidirectional TVS avalanche diode, SOT-23, V BR = 26.4 V *Model simulates of the 2 bidirectional TVS devices *D A Cathode =, D B Cathode = 2, D A,B Common Anode = 3.SUBCKT 2 3 *Bidirectional devices are formed from two unidirectional *devices X 3 HALF X2 3 2 HALF.ENDS *Model HALF represents one bidirectional pair *of a dual device *Anode = 7, Cathode =.SUBCKT HALF 7 *Forward Region *D s CJO term models the capacitance D 2 MDD Variable Parameter SPICE Default Value Units IS Saturation Current E-4 A RS Resistance Ω BV Reverse Breakdown Voltage V IBV Current at Reverse Breakdown Voltage E-3 A N Emission Coeffi cient (η) - XT Saturation Current Temp. Coeffi cient 3 - TT Transit Time ns CJO Zero Bias Junction Capacitance pf VJ Junction Potential V M Grading Coeffi cient.5 - EG Activation Energy. ev KF Flicker Noise Coeffi cient - AF Flicker Noise Exponent - FC Depletion Capacitance Forward Bias Coeffi cient.5 - TNOM Nominal Temperature 27 C Table. Default values of the PSPICE diode statement D variables..model MDD D IS=.8378e-4 N= XTI= RS=.2 + CJO=26.4e-2 TT=e-8 45

3 RZ D2 4 3 MDD2 RS LS C S.MODEL MDD2 D IS=2.5e-5 N=.5 *Breakdown Voltage (VBR) = IBV x RBV EV R S=.28 Ω IBV 6. L S= 2.48 nh RBV 6 MDRBV C S= 26.4 pf Measured Data *MDRBV temp. coef. model VBR/ T Small Signal Model.MODEL MDRBV RES TC=.96 D3 8 MDD2 fr = fr =66 MHz (@ O VDC bias) IT 8. 2π LS C S *************************************** fr *L models the lead-to-silicon connection Frequency (MHz) *package inductance *L is distributed between two diodes for Fig. 4. The impedance of a TVS diode can be modeled as a capacitor at relatively low *bidirectional diodes frequencies; however, the inductance of the IC package must be included as the frequency L e-9 approaches the resonant frequency. * *Leakage Region.ENDS HALF *RL models leakage current (IL) ** *MDR temp. coef. model IL / T RL 2 MDR e+8 The TVS macro-model is based on the zener diode model.model MDR RES TC= TC2= provided in references 3 and 4. References and 2 provide additional information on modeling TVS devices. *Reverse Breakdown Region Forward bias region: Diode D is the key component when *RZ models the I / V slope voltage VD is greater than zero. The TVS diode s forward-bias characteristics are controlled by D s saturation current (IS), emission coefficient (N) and series resistance (RS) variables. The forward-bias current equations are as follows: Impedance (Ω) ID = IF + IL + IR VD + IS _ D2, RL where IL and IR << IF. = IF _ D + Therefore, IF _ Ê hvvd ˆ Ê hvvd ˆ T IS _ D Á e IS _ D Á e T, where Ë Ë VT = 26 mv at 25 C q Leakage region: The leakage or reverse bias before breakdown region is defined when voltage VD is between V and the breakdown voltage (VBR). Currents IF and IR are small in comparison to IL because diodes D and D2 are reverse biased; thus, the leakage current is approximated by VD/RL: ID = IF + IL + IR VD - IS _ D2, where RL IF and IR << IL = IS _ D + Therefore, 46 VD RL

4 (a) A (b) 5A 8 x 2 µs Current Waveform 8A 4.8 V 5 V 8A 5 µs/div. VC(max.) = x 2 µs Current Waveform Time (µs) Fig. 5. Comparing bench measurements (a) on a surge-tested TVS device with Spice simulation (b). SPICE predicts a maximum clamping voltage of 4.7 V, which matches the 4.8 V bench test measurement. the product of current source IBV and resistor RBV, minus the voltage of D3. D3 is used to compensate for the voltage drop of D2. The clamping voltage (VC), specified at current IPP,is equal to the sum of the voltages of EV, RZ and D2: Breakdown region: The breakdown region is modeled by EV, D2 and RZ. Current flows through this path when the voltage exceeds EV plus the forward voltage of D2. The breakdown voltage (VBR), represented by EV, is equal to 47

5 (a) (b) A x µs Current Waveform A A 35 V 35.6 V VC(max.) = 28.9 V RZ =.28 Ω x µs Current Waveform A V 4 V VC(max.) = 35.4 V RZ = 8 Ω 2 µs/div. V.5. Time (ms).5 2. Fig. 6. Bench tests (a) versus SPICE (b) for a x - s surge pulse. SPICE predicts a maximum clamping voltage of 28.9 V with the nominal device resistance (RZ =.28 )) versus 35.6 V for the actual measurement. The simulated results match the bench test if RZ is increased to 8. Ê VD ˆ IS Á e hvt ; therefore, Ë È Ê I ˆ hvt Ín Á D Î Ë IS VC at IPP = VBR + VD2 + VRZ = È Ê IT ˆ Í(IBV R BV ) - h3 VT n Á + Ë IS3 Î ÊI ˆ h2 VT n Á PP + (IPP R Z ) Ë IS2 AC Model influences the transient performance of the clamping response. The impedance plot of a TVS avalanche diode is shown in Fig. 4. The measured impedance can be modeled by an equivalent circuit that consists of resistor (RS), inductor (LS) and capacitor (CS) connected in series. RS is equal to the real portion of the complex impedance and is measured at the resonant frequency (fr). At fr, the impedance is purely resistive because the impedance of the LS and CS are equal in magnitude but opposite in polarity. CS is obtained by measuring the capacitance at MHz. LS is obtained from the resonant frequency, which co r re s p o n d s to t h e m i n i mu m impedance. Table 2 provides a correlation of the small signal model to the SPICE macro-model. Modeling the inductance ensures the magnitude of the overshoot pulse due to the inductance (V = L ( I/ t)) Equivalent Macro- Comments Impedance Component Model Component characteristics: The RZ clamping voltage VC transient response RS RZ + D2RS RZ / power rating of the macro-model is simulated by LS L L produces a short overshoot pulse due to V = L ( I/ t) including the TVS DCJ is specified at a V and decreases as the CS DCJ device s impedance reverse-bias voltage increases versus frequency Table 2. Correlation of the ac and macro-model components. characteristics. It is necessary Region Key Design Parameter Limitation to model the VF is typically specified as a maximum value at a single impedance current point in the data sheet. Forward Forward voltage (V ) F because the The accuracy is enhanced if two typical test points are used. fast rise time IL is modeled as a linear function of the bias voltage. and high peak Leakage Leakage current (IL) IL actually varies as an exponential function of the bias current of the voltage. surge pulse VC due to self-heating is not modeled. creates highbreakdown Clamping voltage (VC) Overcurrent failures are not modeled. frequency information that Table 3. Simulation limits of TVS diode macro-models. 48

6 of the IC package is simulated. Matching the capacitance helps in predicting the shape of the clamped waveform, while including an accurate resistance term is important in predicting the power capability of the device. Simulation Test Results The ability of the SPICE macromodel to predict the performance of a TVS device is shown by comparing simulation and bench data for the 8 2-µs and -µs surge tests. These waveforms are often used to specify the power rating of a TVS device, in addition to representing the surge pulses produced by common noise sources. The surge pulses are defined by their rise time (t R ), measured at % to 9% of the pulse amplitude, and their pulse duration, measured at 5%. The voltage and current waveforms represent the open- and short-circuit that is, R = 2 Ω conditions, respectively. F i g. 5 s h ow s t h e c l a m p i n g performance of a TVS diode for the 8 2-µs surge test. The 8 2-µs surge pulse represents the positive voltage transient created by the sudden interruption of current in a load that is connected in parallel with an electronic module. Low-side drivers that are used to turn on electronic modules, motors and relays are examples of systems that can produce this surge pulse. The clamping performance of a TVS diode for the -µs surge test is shown in Fig. 6. The -µs surge pulse occurs when power is removed from an inductive load and the device under test (DUT) simultaneously. The DUT remains connected in parallel with the inductance, which produces a negative surge voltage. DC motors, solenoids and relays are common examples of inductive loads that can produce this surge pulse. The discrepancy between the measured and simulated - µs clamping voltage is due to the self-heating of the device by the surge current. In addition, the macro-model was calibrated to the 8 2-µs pulse instead of the -µs pulse. The accuracy of the predicted clamping voltage for high-energy, long-duration surges can be improved by calibrating the model with the -µs pulse. Future enhancements of the macro-model will include integrating a thermal model to simulate the increase in the TVS device s junction temperature due to self-heating. Macro-models provide an accurate SPICE representation of the TVS avalanche diode s current and voltage characteristics for most applications. The macro-models solve several of the limitations associated with the SPICE diode D statement and the curvefit models. Macro-models provide a powerful design tool to analyze surge suppression circuits; however, they are not a replacement for hardware development tests. A summary of the limitations of the macro-models is shown in Table 3. Enhancing System Reliability System designers are being challenged to meet stringent surgesuppression requirements. In order to produce competitive products, they must increase the reliability and reduce the size and cost of their circuits. TVS avalanche diodes can be used to increase the surge immunity without significantly adding to the cost, size and complexity of power circuits. The ability of TVS diodes to dissipate surge voltages that contribute to the early failure of semiconductors can be evaluated using SPICE macromodels. PETech References. Bley, M., Filho, M. and Raizer, A. Modeling Transient Discharge Suppressors, IEEE Potentials, August/ September Hageman, S. Model Transient Voltage Suppression Diodes, MicroSim Application Notes, Lepkowski, J. AND825 Zener Macro-Models Provide Accurate SPICE Simulations, ON Semiconductor, Wong, S., Hu, C. and Chan, S., SPICE Macro Model for the Simulation of Zener Diode Current-Voltage Characteristics, International Journal of Electronics, Vol. 7, No. 24, August