Implementing MATLAB and Simulink Algorithms on FPGAs

Transcription

1 Implementing MATLAB and Simulink Algorithms on FPGAs Stefano Olivieri Senior Application Engineer MathWorks Marco Visintini Sales Account Manager MathWorks Daniele Bagni DSP Specialist EMEA Xilinx 2011 The MathWorks, Inc. 1 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 2 1

2 Introducing The Speakers Xilinx: Daniele Bagni DSP Specialist EMEA MathWorks: Stefano Olvieri Senior Application Engineer Signal Processing and Communication Marco Visintini Sales Account Manager 3 MathWorks and Xilinx Goals MathWorks: accelerate the pace of engineering and science by providing best in class Software for: Development elopment and verification of algorithms and control logic Embedded Systems implementation Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms : Offers FPGAs and Zynq an Extensible Processing Platform Partner with MathWorks to provide an integrated t workflow Purpose of the joint seminar: to demonstrate a Model-Based Design workflow for FPGAs - from first idea down to the Hardware. 4 2

3 MathWorks at a Glance Headquarters: Natick, Massachusetts US Other US Locations: California, Michigan, Texas, Washington DC Europe: France, Germany, Italy, Spain, the Netherlands, Sweden, Switzerland, UK Asia-Pacific: Australia, China, India, Japan, Korea Earth s topography on an equidistant cylindrical projection, created with MATLAB and Mapping Toolbox. Worldwide training and consulting Distributors in 25 countries 5 MathWorks Today Revenues ~$600M in 2010 Privately held More than 2000 employees worldwide Worldwide revenue balance: 45% North America, 55% international More than 1 million users in 175+ countries

4 Key Industries Aerospace and Defense Automotive Biotech and Pharmaceutical Communications Education Electronics and Semiconductors Energy Production Financial Services Industrial Automation and Machinery 7 Who is Who??? Who is a System Engineer? Who is an FPGA designers? Who is using MATLAB? Who is using Simulink? 10 4

5 Your Expectations Beyond the Agenda Corner Detection in Video Mosaicking (A Brief Example) 13 5

6 Things to remember. Algorithm Development DESIGN MATLAB Simulink Stateflow Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 14 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 15 6

7 Why do we use FPGAs? Customized interfaces to peripherals High-speed communication interfaces to other processors Bridge Memory Memory Memory We are going to focus on this use case today Finite state machines, digital logic, timing and memory control Analog I/O Digital I/O FPGA ARM High speed, highly parallel DSP Algorithms or Control Algorithms DSP DSP Algorithms 16 Separate Views of DSP Implementation System Designer FPGA Designer Algorithm Design System Test Bench RTL Design Verification Fixed-Point Environment Models IP Interfaces Behavioral Simulation Timing / Control Logic Analog Models HW Architecture Functional Simulation Architecture Exploration Digital Models Static Timing Analysis Algorithms / IP Algorithms / IP Timing Simulation Implement Design Back Annotation FPGA Requirements Hardware Specification Test Stimulus Synthesis Map Place & Route FPGA Hardware 17 7

8 Where do you spend most of your time? System Designer Algorithm Design System Test Bench Fixed-Point Environment Models Timing / Control Logic Analog Models Architecture Exploration Digital Models Algorithms / IP Algorithms / IP FPGA Requirements Hardware Specification Test Stimulus Simulating designs? Creating designs and test benches? Analyzing and combining results from multiple tools? Exploring implementation ideas and architectures? Floating point to fixed-point? Writing HW specifications? Iterating over designs with the FPGA designer? Blaming the FPGA designer? 18 Where do you spend most of your time? Simulating designs and validating against HW specs? Creating designs and writing test benches? Hardware architecture design? Writing interfaces to existing IP? Synthesis, Map, PAR cycles? Iterating over designs with the system designer? Blaming the system designer? FPGA Designer RTL Design Verification IP Interfaces Behavioral Simulation Hardware Architecture Functional Simulation Static Timing Analysis Timing Simulation Back Annotation Implement Design Synthesis Map Place & Route FPGA Hardware 19 8

9 A Few Ways to Reduce Development Time 1. Increase simulation speed 2. Simplify design entry, system test harness creation, and exploration 3. Shorter iteration cycles required for RTL design & verification 4. Integrate the separate workflows to facilitate collaboration, re-use, and prototyping 20 Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Algorithm Design System Test Bench RTL Design Verification Fixed-Point Environment Models IP Interfaces Behavioral Simulation Timing / Control Logic Analog Models Hardware Architecture Functional Simulation Architecture Exploration Digital Models Static Timing Analysis Algorithms / IP Algorithms / IP Timing Simulation Implement Design Back Annotation FPGA Requirements Hardware Specification Test Stimulus Synthesis Map Place & Route FPGA Hardware 21 9

10 Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation RTL Design IP Interfaces Hardware Architecture Implement Design Verification Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation Back Annotation Synthesis Map Place & Route FPGA Hardware 22 Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Verification Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Functional Simulation Static Timing Analysis Behavioral Simulation Timing Simulation Implement Design Back Annotation Synthesis Map Place & Route FPGA Hardware 23 10

11 Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Verification Automatic HDL Code Generation HDL Co-Simulation Functional Simulation Static Timing Analysis Behavioral Simulation Timing Simulation Back Annotation Implement Design Back Annotation Synthesis Map Implement Design Verification Place & Route FPGA Hardware Synthesis Functional Simulation Map Static Timing Analysis Place & Route Timing Simulation 24 Model-Based Design for Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA Hardware FPGA-in-the-Loop 25 11

12 Why Model-Based Design? MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Use Model-Based Design to provide an integrated workflow Automatic HDL Code Generation Behavioral Simulation HDL Co-Simulation Speed up algorithm development with a unified design environment Implement Design Synthesis Map Place & Route Back Annotation Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 27 AT4 wireless Increases Internal Test Coverage to Over 90% for LTE Physical Layer Test Equipment Designs Challenge Develop test systems for LTE wireless equipment Solution Use MATLAB and Simulink to design and simulate the LTE physical layer, verify the FPGA implementation, and analyze test results Results Internal test coverage increased to over 90% Test harness reused throughout the project life cycle Development effort reduced by 25 30% AT4 wireless LTE layer 1 tester. MATLAB is a universal language that makes it easy to exchange algorithms and test results across our team. Our physical layer model in MATLAB and Simulink enabled us to better understand the LTE specifications, and Model-Based Design enabled us to verify that our FPGA implementation conformed to those specifications. Francisco Javier Campos AT4 wireless Link to user story 29 12

13 Semtech Speeds Development of Digital Receiver FPGAs and ASICs Challenge Accelerate the development of optimized digital receiver chains for wireless RF devices Solution Use MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation Results Prototypes created 50% faster Verification time reduced from weeks to days Optimized, better-performing design delivered Link to user story The Semtech SX1231 wireless transceiver. Writing VHDL is tedious, and the handwritten code still needs to be verified. With Simulink and Simulink HDL Coder, once we have simulated the model we can generate VHDL directly and prototype an FPGA. It saves a lot of time, and the generated code contains some optimizations we hadn t thought of. Frantz Prianon Semtech 30 Case Study: Corner Detection Algorithm 2011 The MathWorks, Inc

14 Harris-Stephens Corner Detection Corner detection is used in many Image Processing applications Image mosaicking Tracking Object recognition 32 Harris-Stephens Corner Detection Horizontal Gradient Corner Metric M c Sobel Edge Filter Vertical Gradient Calculate Corner Metrics Threshold & Find Local Maxima 33 14

15 From Algorithm to Synthesizable RTL MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 34 Flexible Design Environment Design, Simulation and Implementation Choice of best modeling methods (Simulink, MATLAB and Stateflow) Integrate with MATLAB Algorithm Design 35 15

16 Fixed Point Analysis Corner Detection Convert floating point to optimized fixed point models Automatic tracking of signal range (also intermediate quantities) Word / Fraction lengths recommendation Bit-true models in the same environment Automatically identify and solve fixed point issues 36 Automatic HDL Code Generation Corner Detection Automatically generate bit true, cycle accurate HDL code from Simulink, MATLAB and Stateflow Full bi-directional traceability!! Requirements 37 16

17 Simulink Library Support for HDL HDL Supported Blocks 170 blocks supported Core Simulink Blocks Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs Signal Processing Blocks NCOs, FFTs, Digital Filters (FIR, IIR, Multirate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max) Communications Blocks Psuedo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders 38 MATLAB & Stateflow for HDL HDL Supported Blocks MATLAB Relevant subset of the MATLAB language for modeling and generating HDL implementations eml_hdl_design_patterns: Useful MATLAB Function Block Design Patterns for HDL Stateflow Graphical tool for modeling Mealy and Moore Finite State Machines 39 17

18 Integrating Legacy HDL Code HDL Supported Blocks Integrate legacy HDL code in Simulink using black boxes Configure the interface to legacy HDL code EDA Simulator Link is a special black box 40 Summary: Modeling and Code Generation Model-Based Design provides an integrated workflow Optimized design on a System Level Speed up algorithm development with a unified design environment Collaborate with other engineers Use Simulink blocks, Stateflow or MATLAB for modeling and implementation Shorter iteration cycles Assisted Fixed-Point Conversion Automatic HDL Code Generation 41 18

19 Break 42 Things to remember. Algorithm Development DESIGN MATLAB Simulink Stateflow Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 43 19

20 What would you like to get from automatic code generation? 44 Hardware Design Challenges: Optimizing for Speed, Area or Power DESIGN Algorithm Development MATLAB Simulink Stateflow Optimize HDL code Verify optimized HDL Place & Route Analyze result 45 20

21 IIR Low Pass Filter Direct-Form II Transposed SOS 46 From Algorithm to Optimized RTL MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 47 21

22 Hardware Design Challenges: Speed Optimization Finding the critical path in your model can be challenging 48 Demo: HDL Workflow Advisor >> Choose target workflow: FPGA-in-the-Loop FPGA Turnkey Design exploration: Generic ASIC/FPGA Choose FPGA target 49 22

23 Demo: HDL Workflow Advisor Perform relevant checks for HDL code generation 50 Demo: HDL Workflow Advisor Set options and generate automatically HDL code 51 23

24 Demo: HDL Workflow Advisor Create FPGA project Run P&R -and- Annotate timing information Automated workflow from model to FPGA Analysis & Implementation 52 Identifying the critical path Speed Optimization Critical Path highlighting: Visual representation of critical path in your model Easier to identify bottlenecks of your model 53 24

25 Balancing pipeline registers Speed Optimization parallel paths critical path Multiple parallel paths through your model High risk to have unmatched latencies 54 Demo: Configuring Pipelining Options Speed Optimization 55 25

26 Distributed Pipelining Speed Optimization Distributed pipelining (model retiming) Automatic balancing of pipeline registers (focus on critical path only) You are in full control of your pipelining strategy Bottom-up and top-down 56 Distributed Pipelining Speed Optimization Minimum period: ns Maximum Frequency: MHz Section 1 Section 3 Section 2 Device,package,speed: xc5vsx50t,ff1136,

27 Distributed Pipelining Speed Optimization Minimum period: 9.379ns Maximum Frequency: MHz 62MHz Section 3 Device,package,speed: xc5vsx50t,ff1136,-1 Section 2 58 Hardware Design Challenges: Area Optimization X X X X X MUX X SCHEDULING DEMUX X 59 27

28 IIR Low Pass Filter Direct-Form II Transposed SOS Challenges: Data dependent resources to be shared Feedback loops Vectorized inputs 60 Demo: Configuring Sharing Options Area Optimization 61 28

29 Resource Sharing and Streaming Area Optimization Easy to explore different sharing options Direct feedback through resource utilization report Prove correctness through validation models 62 Hardware Design Challenges: Power Optimization Power Dissipation = Static Power + Dynamic Power Static Power = Due to transistor leakage current Significant in smaller silicon geometries Dynamic Power = CV 2 f Function of load capacitance, operating frequency, and voltage swing 63 29

30 Better Algorithm Design Power Optimization Steps To Reduce Power Smaller/Efficient Designs Reduce Clock Frequency Control Subsystem Execution (enabled/triggered subsystems) Low Power Design Libraries/FPGA Devices 64 Multi-rate Models to Reduce Clock Frequency Power Optimization Cycle accurate simulation and implementation Multiple or single clock implementation clk_enable clk clk_enable Timing Controller enb_1_2_1 enb_1_2_

31 Control Subsystem Execution Power Optimization Enabled Subsystems Modules can be enabled and disabled 66 Control Subsystem Execution Power Optimization Triggered Subsystems Modules can be triggered: rising / falling / either edge 67 31

32 Harris-Stephens Corner Detection How do these techniques work with our Corner Detection algorithm?? 68 Summary: Corner Detection Demo Multipliers 154 Adders/Subtractors 90 Registers 852 RAMs 0 Multiplexers 2 Multipliers 6 Adders/Subtractors 46 Registers 679 RAMs 4 Multiplexers 302 Easy approach to explore different implementations No costly mistakes 69 32

33 Summary: Code Generation Optimizations Shorter iteration cycles Automatic HDL code generation Flexible automatic HDL Code generation Speed Optimization Area Optimization Make the right design choices to save power Analyze implementation results, resource utilization report Validation models to prove that implementation is correct 71 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 72 33

34 Things to remember. Algorithm Development DESIGN MATLAB Simulink Stateflow Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 73 HDL Verification How do you do HDL verification today? 74 34

35 Verification Challenges: HDL Verification Design the Test Bench twice 10 to 1 ratio of Test bench LOC to Design LOC Many stimuli-files from MATLAB These are ideal references which require pre- and postprocessing How to analyze results? 75 Verification Challenges: HDL Verification Demo: Re-Use System Level Test Bench 76 35

36 Digital Down Converter DDC accepts A high sample-rate passband signal (may be 50 to 100 Msps) DDC produces A low sample-rate baseband signal ready for demodulation ~70 MSPS ~270 KSPS RF Section A/D Conv Digital Down Converter Demod 77 Integrated HDL Verification MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware Automatic HDL Code Generation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation FPGA Hardware FPGA-in-the-Loop 78 36

37 Verify Handwritten HDL Vector-Based Digital Down Converter What is the impact of these differences? Difficult to analyze simulation results 79 Co-Simulation with HDL simulators Digital Down Converter Re-use system level test bench Flexible testbench creation in Simulink Direct simulation link to HDL Simulators Automatically generated HDL co-simulation models Difference is small and in the stopband of the filter 80 37

38 Additional Methods for Verification HDL Verification Techniques Co-simulation with MATLAB Test Bench Component Generate vector based test benches for standalone verification FPGA-in-the-Loop 81 Integrate MATLAB Algorithm Development Co-Simulation with MATLAB Test Bench Verify HDL against high-level MATLAB design MATLAB HDL Simulator Component Replace a Broken or un-finished i block in a full HDL test bench with a working high level component Test alternate algorithms for system trade-off without developing HDL 82 38

39 Harris Accelerates Verification of Signal Processing FPGAs Challenge Streamline a time-consuming manual process for testing signal processing FPGA implementation Solution Use EDA Simulator Link to verify the HDL design from within MATLAB Results Functional verification time cut by more than 85% 100% of planned test cases completed Design implemented defect-free Link to user story Harris FPGA-based system. EDA Simulator Link enabled us to greatly reduce functional verification development time by providing a direct cosimulation interface between our MATLAB model and our logic simulator. As a result, we verified our design earlier, identified problems faster, completed more tests, and compressed our entire development cycle. Jason Plew Harris Corporation 83 Collaborate with Other Design Teams Test Benches for Standalone Verification Compile and simulation scripts are provided Automatically generate self-checking test benches Can be used in any HDL Simulator 84 39

40 Challenges: Testing algorithms on real hardware Motivation: building confidence But interfaces with peripherals p & rest of the system needed Difficult to construct testbenches in real hardware Demo: Re-Use System Level test bench 86 FPGA-in-the-Loop verification Digital Down Converter Integration with FPGA development boards Automatic creation of FPGA-in-the-Loop verification models 87 40

41 FPGA-in-the-Loop verification Digital Down Converter Flexible testbench creation in Simulink Re-use system level test bench for FPGA verification Building confidence that the design works on real hardware 88 Summary: Verification Integration of FPGA development tools enhances verification Improved analysis, flexible testbench creation (multi domain, feedback loops) Integration with HDL verification Integration with FPGA verification Automation gives shorter iteration cyclescles Automatically generated verification models for: HDL Co-Simulation FPGA-in-the-Loop Wizards for legacy HDL code 89 41

42 From Algorithm to FPGA Implementation MATLAB and Simulink Algorithm and System Design Model Refinement for Hardware EDA Simulator Link Simulink HDL Coder ModelSim RTL Creation HDL Co-Simulation Behavioral Simulation Back Annotation Implement Design Synthesis Map Place & Route Verification Functional Simulation Static Timing Analysis Timing Simulation EDA Simulator Link FPGA-in-the-Loop 90 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 91 42

43 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 92 Agenda 9:45 Welcome 10:00 Reduce FPGA Development Time with Model-Based Design 11:00 Break 11:15 Integrated HDL Verification 12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink 13:15 Lunch 14:15 FPGA Design Optimization Techniques 15:45 Q&A, Summary and Wrap-up 93 43

44 Things to remember. Algorithm Development DESIGN MATLAB Simulink Stateflow Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 94 ROI: Customer Adoption Of Model-Based Design Time spent on FPGA/ASIC implementation Shorter implementation time by 48% (total project 33%) Reduced FPGA prototype development schedule by 47% Shorter design iteration cycle by 80% 1 st FPGA Prototype 2 nd FPGA Prototype 1 st FPGA Prototype 95 44

45 How to adopt MathWorks technologies? MathWorks tools provide a technology to speed up development MathWorks services provide the support to roll out this technology in your organization 96 Example MathWorks Services MathWorks Training Private training Simulink HDL Coder Public training Signal Processing with MATLAB/Simulink Fundamental trainings for uniform knowledge, quick ramp up MathWorks Consulting Jumpstart service to get you up and running quickly with Simulink HDL Coder Advisory service for ongoing expert advice during technology adoption Based on industry experience, assistance with tailoring workflow On site expert customization / optimization of your workflow Technical Support Comprehensive, product-specific Web support resources 70% cases solved within 24 hours Included in Software Maintenance Service 97 45

46 Were Your Expectations Met? Please complete and return seminar survey forms Your comments and feedback are very important to us 99 Next Steps 1. Visit for more information 2. Visit for more information 3. Watch our FPGA webinars: / t / 4. Contact your local sales reps for a trial of our FPGA tools Questions?