Design and Analysis of a Dual Loop CDR using Maneatis Delay Cell VCO

Transcription

1 Design and Analysis of a Dual Loo CDR using Maneatis Delay Cell VCO Khalil Ibrahim Mahmoud, J. Dhurga Devi, and P.V. Ramakrishna Deartment of Electronics and Communication Engineering College of Engineering, Anna University, Chennai, INDIA [email protected], [email protected], [email protected] Abstract Clock and Data Recovery (CDR) circuits have been used extensively in the receivers of otical communication systems, and a variety of alications of inter and intra chi communications. The rimary design/erformance metrics of CDR circuits are clock jitter, lock range, acquisition time, ower consumtion, silicon area, and noise immunity. The main source of jitter is the ower suly noise. The resent aer investigates the effects of ower suly noise on the jitter erformance of the well known dual loo architecture of CDR system. In order to imrove the jitter erformance of the dual loo CDR system, the VCO alone is relaced by the selfbiased Maneatis VCO which is well known for its immunity to ower suly noise and rocess variations. The Maneatis VCO is widely used for microrocessors PLL systems but it is rarely used in CDR systems. The combination of the dual loo architecture and self-biased Maneatis VCO together rovides the benefits of both schemes. Simulations were then carried out systematically to determine the caability of the roosed CDR circuit to tolerate ower suly noise. The results resented in this aer show that while the conventional dual loo architecture cannot tolerate more than 20mV@10MHz noise on ower suly terminal, the roosed CDR architecture can tolerate u to 200mV@10MHz noise on the ower suly without degradations in jitter erformance. Keywords- CDR, PLL, VCO, Jitter, Power Suly Noise. I. INTRODUCTION During the ast few decades, the CDR circuits have layed an imortant role in a wide range of alications such as Gigabit Passive Otical Network (GPON), Gigabit Ethernet Passive Otical Network (GEPON), Synchronous Otical Network (SONET), otical transmission receiver, chi-chi interconnections, DDR, System on Chi (SOC), serial link communications, and PCI. The CDR circuits are normally used to extract the clock embedded in the received data and used to re-time and re-samle the received (distorted) data for further synchronous rocessing. The most imortant metric of CDR system erformance is the jitter on the recovered clock, and it reresents the deviations of the clock transitions from the ideal one. The state of the art CDR circuit architectures, and the trade-offs and techniques for reducing the jitter are discussed in recent tutorials [3]-[6]. Of late, with the increased integration of analog and digital functions on the same chi, immunity to ower suly noise has emerged as a very imortant design constraint. Several studies on the mitigation of ower suly noise on PLLs have been reorted in [7]-[10]. In addition to using differential toologies, some of these studies suggest the use of regulators as common techniques used to mitigate the ower suly noise. The design of PLLs considering immunity to ower suly noise as a design constraint is resented in [9] and considers variants of the Maneatis VCO [11, 12] in the context of PLLs and their sensitivities to ower suly noise. A fast Matlab simulation rocedure for evaluating the imact of ower suly noise on CDR system has been described in [10]. Very few studies on the mitigation of ower suly noise for CDRs have been reorted in the literature. The resent work addresses this articular asect of CDR circuits, secifically in the context of dual loo delay interolating architectures. Although there are many architectural choices, the dual loo delay interolating CDR described in [1]-[3] is chosen for the resent study since this is considered as one of the imortant architectures for realizing CDR circuits with a wide oerating frequency range while at the same time roviding low jitter. The symmetric load, self-biased Maneatis VCO roosed by [11, 12], is well known for its ability to mitigate ower suly noise and for this reason and is widely used in many of the state of the art of microrocessor PLLs. The resent study investigates the ossibilities of using this VCO in CDR circuits. It was observed that the Maneatis VCO as roosed in [11, 12] could not be used as such in the original dual loo CDR architecture since the former had only one control voltage inut while the latter required a VCO with a coarse as well as fine control voltage inuts. Hence, in the resent study, the bias generator of the self-biased Maneatis VCO from [11, 12] was suitably modified and then was incororated into the CDR circuit. It is demonstrated in this aer that the modified Maneatis VCO is caable of roviding imroved erformance with resect to ower suly noise. Secifically, simulation results show that the roosed scheme tolerates u to seven times the ower suly noise than in the conventional dual loo CDR for similar jitter erformance. The resent aer is organized as follows. Section 2 resents a brief descrition and design details of the wellknown dual loo delay interolation CDR. Section 3 discusses the roosed modification of the Maneatis VCO for incororation into the dual loo CDR design. Section 4 gives the simulation results of noise erformance for the delay interolation dual loo CDR as well as for the roosed modified Maneatis dual loo CDR and in Section 5, the conclusions are resented. 6

2 II. THE DUAL LOOP CDR SYSTEM DESIGN The block diagram of the dual loo delay interolating CDR is shown in Fig. 1 and is the same as the one resented in [1, 2]. This system will be considered as a reference system against which the erformance of the roosed modifications will be comared. The system shown in Fig. 1 consists of a coarse FLL and a fine PLL which oerate together on the inut data sequence and recover the clock which could be subsequently used for retiming the data. D D FD PD Figure 1. The Comlete CDR System Block Diagram The FLL rovides a coarse acquisition of the clock and oerates over a wide frequency range. It comrises of the Frequency Detector (FD), the Charge Pum (CP), the Low Pass Filter (LPF), Common Mode Feedback (CMFB), and a delay interolating VCO. The FD is realized using a digital quadricorrelator and detects the frequency difference between the inut data rate and the internally generated clock by the VCO. The oututs of the FD are the UP and DOWN ulses that have constant ulse durations and the number of ulses generated in a given time interval deends on the frequency difference. These ulses are fed to the charge um, where they are converted into roortional charging and discharging currents for the LPF. The details of circuit design for individual blocks of the FD are given in [1, 2] and the same rocedure has been adoted for the resent work. The design equations given below are from [1, 2, 13] and are used to determine the LPF arameters of the FLL. Ic. KVCO. k c 2. c 1 z 5 R.C (1) (2) C CP VtoI C s 5. c (3) C. Cs. R 1 1 Cs. R (4) C The symbols ω c, ω z, ω, ζ, and K VCO in the above equations reresent the crossover frequency, ole frequency, LPF LPF CMFB CMFB V coarse VCO V fine CKQ CKI zero frequency, daming ratio, and VCO gain, resectively. The symbols R, C, and C s reresent the shunt resistor, caacitor and arallel smoothing caacitor, resectively. The PLL in Fig. 1 has a much smaller cature range and oerates after the FLL has acquired lock and this combination of FLL lock followed by PLL lock reduces the jitter in the recovered clock considerably. The PLL loo consists of a Phase Detector (PD), a Voltage-to-Current converter (V/I), and the LPF. The PD is an analog samle and holds system which consists of a two samle and hold circuits and a multilexer. The outut of the PD is a differential voltage roortional to the inut hase difference. These voltages are converted to roortional currents by the V/I converter and are used as the charging and discharging currents of the LPF of the PLL block. The VCO is a ring oscillator which is common to both FLL and PLL is realized with four delay cells and uses the delay interolation concet with two aths, the fast ath and the slow ath. Fig. 2 shows the delay interolation concet realized in the delay cell. The fast ath consists of a differential stage, while the slow ath consists of a constant delay stage and a differential stage. The two aths share the same outut load. The outut current is the sum of the slow and fast currents and is constant. The slow and fast currents are steered differentially deending on the control voltages to maintain constant sum. V in Figure 2. Shows the Delay Interolation Concet As in the case of the LPF of the FLL, the design rocedure for determining the PLL loo filter arameters are adoted from [1, 2, 13] and the design equations are listed below: 2. 2 (5) n K K d. K VCO. 4 (6) K n 1 (7) 2 Rf 1 Rf 2C. (8) 1 Delay Fast Path Slow Path Delay Control + V out 7

3 R f.c (9) 2 2 Where the symbols τ 1, τ 2, R f1, R f2, and c are reresent the time constants, series resistor, shunt resistor and caacitor, resectively, of LPF of the PLL. The symbols ω n, ζ, K, K PD, K VCO are the natural frequency, daming ratio, oen loo gain, hase detector gain, and VCO gain, resectively and these values can all be determined once the oerating frequency, bias currents and technology node of the CMOS rocess are chosen. Detailed simulations have been carried to determine the erformance of the dual loo delay interolation CDR with resect to ower suly noise. Though the details and quantitative results of these simulations are resented subsequently in Section 4, the conclusion that clearly emerged from these simulations was that the erformance of the dual loo delay interolation CDR was very sensitive to ower suly noise, and that one cannot ossibly use this CDR without dedicated regulators roviding clean ower suly to the whole system. III. THE MANEATIS DELAY CELL-BASED VCO AND ITS MODIFICATION It is well known from the PLL literature that the major contribution to jitter (or hase noise) due to ower suly noise comes from the VCO block of the PLL, and this was true in the resent CDR case as well (quantitative results given in the next section). Since the Maneatis Delay Cellbased VCO is well known for its immunity to ower suly noise, the adatation of this VCO to the dual loo CDR is described next. The block diagram of the original Maneatis VCO and its associated bias generator are shown in Fig. 3 and Fig. 4, resectively. The Maneatis VCO shown in Fig. 3 basically comrises of four symmetric load delay cells for which the control voltages come from the bias generator circuit in Fig. 4. The Maneatis Delay cell-based VCO osses two salient features, first is its high suly immunity, and the second is its symmetric load resistance based delay element. The latter enables the VCO to have a wide oerating frequency range. The symmetric load resistance can also reject the suly noise (dynamic suly noise rejection) and is obtained by having the lower limit of the voltage swing to be equal to the control voltage itself. Further, for static suly noise rejection, it is required that V control track the suly voltage variations and hence it is referenced to (V DD ) in [11, 12]. From this V control, one has to generate two bias voltages and to be fed to the VCO of Fig. 3. Of these, tracks the suly voltage changes to kee the load resistance of the delay cell and hence, the outut frequency constant. On the other hand, is ket indeendent of suly voltage changes in order to kee the tail current constant. It can be seen that the conventional bias generator shown in Fig. 4 can accet only one control voltage V control, and hence cannot be directly incororated directly into the dual loo CDR of Fig. 1. To rovide an otion for acceting coarse and fine control voltages, the bias generator of the Maneatis VCO has been modified and is shown in Fig. 5. In this modified circuit, the coarse and fine control voltages are rovided as gate voltages to two NMOS transistors which act as voltage controlled current sources (tail sources). These currents are summed u to form the drain current of a single PMOS transistor. Since the source of this diode connected PMOS transistor is connected directly to the suly rail, its gate voltage tracks the changes in suly voltage while maintaining the current set by the bottom tail transistors. This gate voltage of the PMOS is then used as art of a feedback loo containing the half relica delay cell to generate the bias voltages and which are used finally by the delay elements of the VCO. The final block diagram of modified Maneatis delay cell VCO is shown in Fig. 6. The voltage,, roduced by the bias generator tracks the suly voltage and sets the lower limit of the oscillation swing (and the load resistance) to fix the outut frequency. On the other hand, since the course (-coarse ) and fine control voltages (-fine ) are referenced to the ground terminal, the final voltage, which determines the tail current in the delay element, kees the tail current constant. V control V control _coarse Bias Gen _fine Figure 3. The original Maneatis VCO Half Relica Figure 4. Original Bias Generator _in Inut Stage V DD Outut Buffer Half Relica V DD Outut Buffer Figure 5. Modified Bias Generator 8

4 V fine Bias Gen V coarse Figure 6. The roosed modified VCO The simle modification roosed above for the bias generator rovides a method for combining the coarse and fine control voltages while retaining the robustness of the original Maneatis VCO. The sensitivity of this VCO to ower suly voltage variations were first assessed and then the VCO was incororated into the original dual loo CDR scheme of Fig. 1. Using the same system secifications and design equations described earlier in Section 2, the arameters of the LPFs for the FLL and PLL have been determined and are listed in Table I. These arameters are different from those of the delay interolation VCO because the coarse and fine gains of the modified Maneatis VCO are different from that of delay interolation VCO. IV. SIMULATION RESULTS AND DISCUSSION In this section, first, quantitative results related to the suly noise erformance of the delay interolating VCO based CDR are resented. Next, simulations results are resented to validate the modification carried out on the Maneatis VCO and also to demonstrate that it can indeed relace the delay interolation VCO in the original dual loo CDR. Finally, for the modified dual loo CDR, simulation results related to its erformance with resect to ower suly noise are resented. All simulations have been carried out using the Cadence Sectre tool. The devices chosen for the simulations are from the 0.35μm CMOS technology libraries from Austriamicrosystems and the various over-drive voltages and bias currents are chosen accordingly. For the resent work, a nominal data rate of 833 Mbs is chosen for the CDR, the FLL cross over frequency is chosen as 30MHz, and the charge um current of the FLL is found to be 125μA. The PLL loo natural frequency ω n, and daming ratio ζ are chosen to be 0.5 MHz and 4, resectively. The FLL and PLL LPF arameters have been determined for the above system secifications and given in Table I. For clock recovery simulations, PRBS data of length 2 14 were used as inut data to the CDR system. First, the delay interolation VCO characteristics are given in Fig. 7 where the outut frequency deendence on coarse and fine control voltages is shown. The coarse and fine gains are found to be 506MHz/V and 65.9MHz/V, resectively. Similarly, the modified Maneatis VCO circuit was simulated and Fig. 8 shows the corresonding VCO gains lots. The coarse and fine gains were found to be 3GHz/V and 230MHz/V, resectively. Figure 7. Coarse and Fine Gains of the Delay Interolation VCO Figure 8. Coarse and Fine Gains of the Modified Maneatis VCO Figure 9. The Delay Interolation VCO Sensitivity to Power Suly Noise The static suly sensitivity of the delay interolation VCO is shown in Fig. 9. For a nominal control voltage (Vc=0.74V, Vf=0.74V), it is found to be 185MHz/V and reresents 6.6% frequency change for 10% change in the suly. The corresonding static suly sensitivity of the modified Maneatis VCO is shown Fig. 10. Figure 10. The Modified Maneatis VCO Sensitivity to Power Suly Noise 9

5 Figure 11. Variations of Vbn and Vb versus Power Suly Voltage For a nominal control voltage (Vc=0.95V, Vf=1.05V), it is found to be 67MHz/V and reresents 2.4% frequency change for 10% ower suly change. The reduction in sensitivity of the modified Maneatis VCO is to be exected and is due to the ability of the bias generator to track the variations of the ower suly voltage and is demonstrated in Fig. 11. The variations of and with resect to V DD are lotted in Fig. 11 while maintaining the coarse and fine voltages constant and it can be seen is indeendent of V DD while tracks V DD for static ower suly variations. Incidentally, the modified Maneatis VCO also has better ower suly sensitivity of 67MHz/V as comared to the value 158MHz/V reorted recently in [14], though the latter is for a PLL and for a somewhat higher frequency. Next, with PRBS data inut, clock recovery was carried using two the CDR schemes using clean ower sulies. The cature transient showing the evolution of coarse and fine control voltages of the dual loo delay interolation CDR and the dual loo modified Maneatis CDR are deicted in Fig. 12 and Fig. 13, resectively. For the dual loo delay interolation CDR, the lock time, the steady state rile on the fine control voltage, and the recovered clock jitter are 1μsec, 50mV and 4.3sec (0.4%UI), resectively. The corresonding quantities are for the dual loo modified Maneatis CDR are 0.6 μsec, 10mV, and 8.4 sec (0.7%UI), resectively. Figure 13. CDR Control Voltages with Clean Power Suly for Modified Maneatis VCO Immunity of the two CDR schemes to ower suly noise is characterized by adoting the rocedure followed in [11, 12]. Noise sources in the form of sinusoidal signals of different frequencies and amlitudes were suerosed on the VDD suly node. The effects of this noise source on the CDR system are measured by two ways. First by measuring the rile on the differential fine control voltage and the second one is measuring the rms jitter on the recovered clock. Table II rovides the jitter erformance of the dual loo delay interolation CDR with noise injected individually into the ower suly node of the different blocks of the CDR. Each column of the table indicates the rile on the control voltage (after lock) of the dual loo CDR and the jitter on the recovered clock for a secific noise amlitude. It can be seen that the VCO is the most sensitive block and causes maximum degradation of erformance. It was also found that the system fails to lock if the noise amlitude is increased beyond 30mV. Fig. 14 shows the differential fine control voltages of the dual loo delay interolation CDR with noise of 20mV@10MHz on ower suly terminal. For comarison, the same arameters are lotted for the dual loo modified Maneatis CDR in Fig. 15 but with a ower suly noise of 200mV@10MHz. Figure 12. CDR Coarse and Fine Control Voltages with Clean Power Suly for Delay Interolation VCO Figure 14. CDR Control Voltages with 20mV@10MHz Power Suly Noise for Delay Interolation VCO 10

6 TABLE I. THE PLL AND FLL LPF PARAMETERS CDR in Ref. [5] CDR with roosed VCO PLL FLL PLL FLL R1 (kω) 996 R (kω) 3 R1 (MΩ) 4 R (Ω) 503 R2 (kω) 107 C (F) 9 R2 (kω) 107 C (F) 53 C (F) 150 Cs (ff) 371 C (F) 150 Cs (F) 2 TABLE II. JITTER ON RECOVERED CLOCK OF THE CDR WITH VCO OF REF. [5] Figure 15. CDR Control Voltages with 200mV@10MHz Power Suly Noise for Modified Maneatis VCO Finally the jitter erformance of the integrated dual loo delay interolation CDR and the roosed dual loo modified Maneatis CDR are given in Table III. It can be seen that the erformance of the latter with 200mv noise is comarable to that of the former with a 30 mv noise on the suly line. The rile voltage on the control voltage is not listed for the roosed CDR since this tracks the noise on the suly voltage as it is suosed to. Since the Maneatis VCO and the delay interolation VCO of the original dual loo scheme are both differential delay cell-based ring oscillators, their ower consumtion is nearly the same. Since the loo arameters for the roosed scheme have been chosen to be the same as that of the original dual loo scheme, the acquisition time is also nearly the same. Maneatis VCO is inherently known to have a wide range of oerating frequencies. V. CONCLUSIONS While it is noted in the literature that the dual loo CDR architecture has certain imortant desirable features not available in other architectures (see [15] for examle), there are no studies reorting its jitter erformance with resect to ower suly noise. While this might not have been an issue in the older technologies where dedicated external regulators roviding clean sulies to the CDR can be assumed, in the context increased integration and System on Chi (SOC) schemes, on chi ower suly noise often becomes a serious issue. The results resented in this aer rovide three imortant conclusions. The first is that the original dual loo CDR as roosed in [1] is very sensitive to ower suly noise and may require dedicated ower suly regulators. The second conclusion is that the original Maneatis delay VCO can indeed be easily modified for incororation into the dual loo CDR. The third conclusion is that the resulting modified dual loo CDR is caable tolerating nearly 200 mv noise on the suly line without degradation in erformance. This in turn indicates that it can be easily integrated onto (SOC) architectures without requiring dedicated suly regulators. TABLE III. Parameters Noise amlitude at 10MHz (mv) with Noisy Power Suly Jitter on Recovered clock 25, (2) 52, (4) 63, (5) s, (%UI) Rile on Vfine (mv) BLOCKWISE NOISE PERFORMANCE OF THE CDR WITH VCO OF REF. [5] Parameters With Noisy Power Suly Only On Noise of 20mV at 10MHz VCO FD PD CP VtoI Jitter on Recovered clock 50, (4) 11, (1) 11, (1) 8, (1) 16, (1) s, (%UI) Rile on Vfine (mv) TABLE IV. JITTER ON RECOVERED CLOCK OF THE CDR WITH PROPOSED VCO Parameters with Noisy Power Suly Noise amlitude (mv) at MHz Jitter, s (%UI) on 23, (2) 34, (3) 57, (5) Recovered clock ACKNOWLEDGMENT The author would like to acknowledge Iraq-India governments for extending facilities and financial suort of the Scholarshi through Indian Counsel for Cultural Relations (ICCR) and Ministry of Science and Technology of Iraq. REFERENCES [1] Seema Butala Anand and Behzad Razavi, A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data, (2001), IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, [2] Yi-Ju Chen and Monuko du Plessis, An integrated 0.35 µm CMOS otical receiver with clock and data recovery circuit, (2006), Microelectronics Journal, [3] Ming-ta Hsieh and Gerald E. Sobelman, Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery, (2008), IEEE Circuit & System Magazine,

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