10 Gigabit Ethernet Test and Measurement Challenges

Transcription

1 10 Gigabit Ethernet Test and Measurement Challenges August 1, 2002 presented by: Brian Scott Geoff Waters

2 10 Gigabit Ethernet Standard 10 Gigabit Ethernet standard is IEEE 802.3ae Draft P802.3aeD5.0 was ratified on June 14, 2002 Original intention: Scale 1 Gigabit Ethernet (802.3z) to 10 Gb/s Some tests proved to be extremely difficult to execute at 10 Gb/s 10 GbE Serial Optics Test: Stressed-eye receiver sensitivity Building in the calibrated levels of deterministic and random jitter Transmitter jitter through bathtub curve analysis Page 2

3 Agenda Standard specifies test and measurement requirements at all layers Today s topics: Clause 52: Physical Medium Dependent sublayer Clause 47: 10 Gigabit Attachment Unit Interface (XAUI) Page 3

4 The Evolution of IEEE 802.3ae The Evolution of IEEE 802.3ae Clause 52: 10 GbE PMD Sublayer Serial Optics Tests: New Stressed Receiver Conformance Test Simplified and changed stressed eye Transmitter and Dispersion Penalty Test Replaces bathtub curve analysis XAUI Test: New 10 Gigabit Ethernet Attachment Unit Interface (XAUI) between MAC and PCS with 4 lanes of Gb/s Allows the elimination of the 74 signal-wide interface (XGMII) and associated skew problems New 64b/66b line coding (translates 8b/10b) Page 4

5 IEEE 802.3ae Clause 52 Test Setup GHz Source Stressed Receiver Conformance Test Transmitter and Dispersion Penalty Test >40 MHz Jitter 40 MHz Source Laser 1310 Modulator Optical Atten. Rx DUT Tx Golden Test Fiber Pattern Generator LPF 1-2 GHz Source 10 db Coupler Optical Atten. O/E Error Detector Stressed Conditioner CDR Reference Receiver Page 5

6 Stressed Receiver Conformance Test Apply the worst case compliant transmitter signal to the receiver Verify a BER of better than 1x10-12 is achieved 0 to 40 MHz GHz Clock Pattern Generator Sinusoidal jitter modulates the clock timing of the pattern generator Sinusoidal interference signal summed with jittered data pattern Summed signal low-pass filtered ~1-2 GHz sine 7.5 GHz LPF Laser Atten. Page 6

7 The Stressed Eye Eye impairments include: Sinusoidal jitter Horizontal eye closure Inter-symbol interference (ISI)/ Vertical Eye Closure Penalty (VECP) Attenuation Page 7

8 Stressed Eye Example Stressed Eye Example While the concept is straightforward, construction of the stressed eye requires a careful, systematic approach Insufficient stress allows weak parts to appear compliant Excessive stress makes possibly good receivers appear noncompliant Page 8

9 Building the Stressed Eye Stress receiver conformance test The standard defines the test equipment and the procedure Page 9

10 Receiver Test Block Diagram 71501D 33250A 40 MHz 70820A Jitter Calibration E4422B 1-2 GHz Switch Attenuation DUT Rx 83732B GHz N1015A Jitter Testset Stressed eye construction process PRBS >= Set transmitter extinction ratio Measure Optical Modulation Amplitude (OMA) Add ISI induced VECP relative to OMA <67% due to filtering Add remaining VECP through sinusoidal interferer and sinusoidal jitter 71612C PG N1016A Stressed Eye Testset Page B 81560A 81591A DCA 86100B 86107A 86106B Iterate (all) to achieve correct VECP Attenuate signal to required OMA Step through complete sinusoidal jitter template

11 Building the Stressed Eye 71612C PG N1016A Stressed Eye Testset PRBS >= Set transmitter extinction ratio Page 11

12 Building the Stressed Eye Measure Optical Modulation Amplitude (OMA) Set nominal Vertical Eye Closure Nominal 1 level Nominal 0 level Page 12

13 Building the Stressed Eye 71612C PG N1016A Stressed Eye Testset Add ISI induced VECP relative to OMA <67% due to filtering Page 13

14 Building the Stressed Eye 33250A 40 MHz 70820A Jitter Calibration 83732B GHz N1015A Jitter Testset N1016A Stressed Eye Testset Add VECP through sinusoidal jitter Page 14

15 Building the Stressed Eye E4422B 1-2 GHz N1016A Stressed Eye Testset Add remaining VECP through sinusoidal interferer Page 15

16 Building the Stressed Eye 71501D 33250A 40 MHz 70820A Jitter Calibration E4422B 1-2 GHz optical Switch Attenuation DUT Rx 83732B GHz N1015A Jitter Testset 71612C PG Stressed eye construction process Iterate (all) to achieve correct VECP Attenuate signal to required OMA Step through complete sinusoidal jitter template Monitor BER at the receiver N1016A Stressed Eye Testset 8163B 81560A 81591A DCA 86100B 86107A 86106B Page 16

17 Transmitter and Dispersion Penalty Test 1 Gigabit Ethernet tested with the jitter bathtub curve Initial attempts to do 10 Gb/s bathtubs were unsuccessful as most devices failed! Some test system error detectors had jitter problems which masked the true performance of transmitters While error detectors existed that generated accurate bathtubs, the clause 52 standards committee chose an alternative test methodology for characterizing optical 10 Gb/s transmitters Overall transmitter performance (including jitter) characterized through the Transmitter and Dispersion Penalty test or TDP Page 17

18 Transmitter and Dispersion Penalty Test Transmitter and Dispersion Penalty Measurement The standard defines the test equipment and the procedure Page 18

19 Transmitter and Dispersion Penalty Test DUT Tx Golden Test Fiber N1016A Reference Transmitter 8163B 81591A optical Switch +/- 5 ps X X 10 db Coupler 8163B 81560A Optical Atten. Page A O/E 83434A CDR Amp C Error Detector A test bed including a reference transmitter and reference receiver is characterized for BER with a known level of signal attenuation The transmitter under test is substituted for the reference transmitter. The TDP figure is the sensitivity level that the system attenuation must be reduced to in order to return to the test bed BER level.

20 Clause 52 PMD Measurement Summary N1016A Stressed Eye Test Set Stressed Receiver Conformance Test: Difficult to construct Solution is available that is compliant, calibrated, repeatable and adjustable. Transmitter and Dispersion Penalty Test: Test Solution can be constructed to successfully complete the test Stressed Eye Reference Transmitter Eye Page 20

21 Where XAUI Fits Page 21

22 Benefits of Using XAUI Self-clocked XAUI eliminate clock-to-data and data skew issues Robust CML differential, un-clocked interface allows trace lengths of 18 on FR4 Commonality with emerging Fibre Channel, Infiniband and SONET standards Bi-directional interface requires only 16 point-to-point connections Page 22

23 XENPAK Module Block Diagram Page 23

24 XAUI - A Self-Managed Interface Supports robust 8B/10B transmission code Extra code groups are used for control signaling Control words used during IPG and idle periods for word and lane alignment This happens without upper layer support Therefore XAUI functions as a self-managed interface Page 24

25 XGXS Deskew Skewed data at receiver input. Skew - 18 bits Deskew lanes by lining up Align code-groups Taken from IEEE 802.3ae task force XAUI/XGXS proposal Page 25

26 Clock Tolerance Compensation XAUI allows for independent clock domains on each side of the link Clocks will be at different rates within specified tolerance limits Clock Tolerance Compensation (CTC) adds or deletes R code/word to equalize the data rates Page 26

27 Challenges of XAUI BER Testing XENPAK Clock tolerance compensation (CTC) mechanism can make the output nondeterministic Scrambler/de-scrambler complicates testing from 3G XAUI to 10G serial optical Turning scrambler off results in long runs of zeros with inadequate timing information De-skew pattern must be transmitted before required data BER is not measured during the transmission of the de-skew pattern Page 27

28 XENPAK BER Testing - Solutions CTC frozen by synchronizing test equipment to MHz reference oscillator in XENPAK Generation of four Gb/s outputs Required de-skew pattern may be transmitted Data capture and post processing allows direct input to output testing Page 28

29 802.3ae Loopback & Embedded Testing Loopback at PCS, WIS and PMA proposed Internal pattern generator and error detector Range of test patterns including PRBS Identical patterns may be stored in test equipment custom pattern memory XAUI i/o and serial optical i/o may be tested Vendor-specific implementation of these features offers more testing flexibility Many vendors loop-back at 10G Page 29

30 Serial vs. Parallel BERT 71612C Serial BERT: Up to 12.5 Gb/s General purpose/simple Differential serial output One single-ended error detector input Four single-ended outputs up to Gb/s Custom pattern memory Flexible interfacing Bathtub jitter (XAUI) CJPAT/CRPAT etc 10G Stressed Eye (802.3ae) Parallel BERT: Up to 10.8 Gb/s Modular/expandable/complex Multiplex to higher rates (PRWS) Differential inputs and outputs Adjustable skew between outputs Variable timing & levels for all channels Custom pattern memory Data capture/post processing DITO (3G->10G) CJPAT/CRPAT etc Bathtub jitter (XAUI) Page 30

31 71612C BERT XAUI Test Applications Sub-rate outputs: Four outputs at 1/4 of the main serial output rate (max 12.5 Gb/s) are available Alternate pattern mode synchronous selection of two different custom transmit patterns Enables de-skewing of the XAUI lanes before BER measurement is performed on the required data pattern Page 31

32 XAUI BER using XENPAK Clock Input 71612C Pattern Generator 70843C Error Detector 12.5 GHz clock Gb/s clock Pattern C from 71612C Patterns A & B 10MHz Reference E8241A RF Source 2.5 GHz/ MHz Electrical Reference clock in 10Gb/s Tx XAUI-in XENPAK Optical DUT 10Gb/s Rx XAUI-out 86100B DCA (optional) 1 of 4 Page 32

33 XAUI BER using CDR & Multiplier 71612C Pattern Generator 70843C Error Detector 12.5 GHz clock Gb/s clock Pattern C from 71612C Patterns A & B X4 Clock multiplier Clock Data Gb/s CDR Electrical 10Gb/s Tx XAUI-in XENPAK Optical DUT 10Gb/s Rx XAUI-out 86100B DCA (optional) 1 of 4 Page 33

34 XAUI BER using XENPAK Clock Input ParBERT Color Key to Modules Patterns A & B Firewire interface E4808A Clock Module E4866A 10.8Gb/s ParBERT E4861/62B 3.35Gb/s ParBERT MHz Electrical XAUI-out XAUI-in XENPAK DUT Reference clock in 10Gb/s Tx Optical 10Gb/s Rx Page B DCA (optional)

35 10 Gb/s BER using CDR 71612C Pattern Generator 70843C Error Detector GHz clock Gb/s clock from 71612C Data Input 83433A E/O 83434A O/E 10Gb/s Tx Internal Optical loop-back 10Gb/s Rx 86100B DCA (optional) XENPAK DUT Page 35

36 Serial BERT Sub-rate Programming Low Frequency Test Pattern (802.3ae) Pattern consists of alternating groups of five ones and zeros BERT programmed with appropriate 12.5 Gb/s serial pattern such that required Gb/s patterns appears at sub-rate outputs Sub-rate Sub-rate Etc. Page 36

37 Creation of Deskew Pattern Pattern Bp Gb/s outputs would output every fourth bit K28.5 +K28.5 -K28.5 This is the required repeating K28.5 sync or K word taking into account running disparity rules The alignment word (A word) and start-of-data word are similarly programmed according to the pattern structure defined in 802.3ae Page 37

38 Deskew Pattern (continued) Alternate de-skew pattern is run once before the main data pattern Both de-skew and main data alternate patterns must be of equal length Follow pattern structure rules and fill the end of de-skew pattern out with data characters - not more special control characters The characters chosen must end with negative disparity because rules require data to start with negative disparity Page 38

39 81250 ParBERT Sequence Editor Select appropriate pre-defined test patterns Page 39

40 Post-processing with ParBERT Results: # of frames # of CRC Errors # of Frame Bits # of Idle Bits Errors per Lane Error Rate per Lane Data used from Ethernet Frame Editor XAUI and Serial Analysis Page 40

41 Summary 10 GbE Specifications require new test procedures 10 GbE Measurement Resources & Solutions Specific Product Information: Page 41

42 Additional Information Page 42

43 Clock Multiplication and Division ParBERT can change an external clock input frequency by ratio m/n; m and n = XENPAK internal clock 3.125GHz +/-100ppm, 1 Hz resolution (RefClk) XAUI/RefClk: m/n = 20 Serial/RefClk: m/n = 66 Serial/XAUI: m/n = 33/10 Page 43

44 XAUI BER using CDR ParBERT Color Key to Modules Clock Input Data Input Firewire interface E4808A Clock Module E4866A 10.8Gb/s E4861/62B 3.35Gb/s 83434A O/E XAUI-out Electrical XAUI-in XENPAK DUT 10Gb/s Tx Optical 10Gb/s Rx Page B DCA (optional)

45 10Gb/s BER using XENPAK Clock Input 71612C Pattern Generator 70843C Error Detector 83433A E/O GHz clock Clock Input 10MHz Reference MHz Data Input 83434A O/E E8241A RF Source 2.5 GHz/16 Reference clock in 10Gb/s Tx Internal Optical loop-back 10Gb/s Rx 86100B DCA (optional) XENPAK DUT Page 45

46 10Gb/s BER using XENPAK Clock Input ParBERT Color Key to Modules Clock Input Data Input Firewire interface E4808A Clock Module E4866A 10.8Gb/s E4861/62B 3.35Gb/s 83434A O/E MHz 83433A E/O Reference clock in 10Gb/s Tx Internal Optical loop-back 10Gb/s Rx XENPAK DUT Page B DCA (optional)

47 10Gb/s BER using CDR ParBERT Firewire interface 0 E4808A Clock Module E4866A 10.8G ParBERT E4808A Clock Module E4861/62B 3.35Gb ParBERT E4861/62B 3.35Gb ParBERT E4808A Clock Module E4861/63B 3.35Gb ParBERT E4861/63B 3.35Gb ParBERT Patterns A & B E4808A Clock Module E4867A 10.8G ParBERT Clock Input Data Input 83434A O/E 83433A E/O 10Gb/s Tx Internal Optical loop-back 10Gb/s Rx XENPAK DUT 86100B DCA (optional) Page 47