Memory Trends and Implications for Lithography and DSA Technology

Transcription

1 Memory Trends and Implications for Lithography and DSA Technology Linda K. Somerville, Ardavan Niroomand, Pierre Fazan 1

2 Agenda About Micron & Memory Market Trends and Challenges in Memory Innovation Patterning with DSA: Challenges and Opportunities 2

3 $M 20-years of Growth $18,000 and we believe strongly in the future $16,000 $14,000 Micron acquires Elpida and Rexchip Inotera JV restructure $12,000 Micron acquires Lexar Media Micron acquires Numonyx IMFT & IMFS restructuring $10,000 $8,000 Micron acquires TI s memory operations Micron acquires Toshiba s commodity DRAM operations Micron and Intel form IMFT Micron and Nanya form DRAM Joint venture $6,000 $4,000 $2,000 Micron and Intel form IMFS $0 FY-95 FY-96 FY-97 FY-98 FY-99 FY-00 FY-01 FY-02 FY-03 FY-04 FY-05 FY-06 FY-07 FY-08 FY-09 FY-10 FY-11 FY-12 FY-13 FY-14 Micron s Historical Performance and Revenue 3

4 Micron Around the World Manufacturing 34% FAB 2 Lehi FAB 6 66% Virginia FAB 15 Japan FAB 11 Taiwan FAB 16 Taiwan DRAM NAND NOR FAB 10 Singapore 19% FAB 13 4

5 R&D Around the World One R&D Team United States Japan Singapore Milpitas & Folsom, CA: Emerging memory design, product engineering Boise, ID: NAND, emerging memory, DRAM, package R&D, mask technology Hiroshima: DRAM Hashimoto: Emerging memory design, product engineering, package R&D, NAND device Akita: Package R&D Italy India Belgium Singapore: NAND, STTRAM, package R&D Vimercate: Emerging memory, NAND Bangalore: Live die and test structure design/ layout, device analysis Leuven: IMEC core partner program 5

6 Semiconductor Revenue ($B) Memory Revenue ($B) Micron s Markets Continue to Grow Inflation Adjusted Market TAMs (2014 Dollars) $400 $80 $300 $60 Real Semi Revenue $200 $40 Real DRAM Revenue $100 $20 Real NAND Revenue $ $0 Revenues adjusted for inflation, shown in 2014 dollar equivalents. Inflationary adjustments calculated using GDP Implicit Price Deflator. Source: Micron and Industry Analysts 6

7 Growing and Diversifying Memory Demand DRAM Industry Bit Demand (B Gb EU) NAND Industry Bit Demand (B GB EU) Source: Micron and Industry Analysts Handset Tablet AIMM Consumer & Graphics Server/Storage/ Networking PC Other Removable Storage Consumer Handset Tablet Client SSD Datacenter SSD Enterprise SSD Tablets contain a mix of mobile DRAM, standard DRAM, and reduced-power solutions. Upgrade modules included with PC. 7

8 Driving Business to High Value Segments Other Mobile Other Storage SSD Storage Micron acquires Toshiba s commodity DRAM operations Other Embedded AIMM Compute Graphics Server Networking FY H FY15 8

9 Long Term Memory Market Conditions Consolidated Suppliers Suppliers with sufficient scale Return-focused investment and supply environment Low Supply Growth Limited new wafer capacity Slowing technology migrations Diversifying Demand Differentiated products System solutions Diversified customers Broadening applications 9

10 Trends and Challenges in Memory Innovation 10

11 Micron s Portfolio of Innovative Firsts DRAM 6F 2 architecture Leading DRAM capacitor technology Copper metallization Packaging (3Di) Hybrid memory cube, Through Silicon Via (TSV) 0.8mm four-layer LPDRAM package NAND Pitch multiplication patterning Award-winning, industry-leading planar NAND cell technology New Memory Productization of phase change memory Demonstration of 16Gb resistive RAM Development of 3D XPoint memory 11

12 Challenges Faced in Technology Development DRAM NAND New Memory Package Edge yield improvements continuous yield improvement Ramp execution new tool installs and matching, cost of transition Process equipment maturity improvement: uniformity, capability Defect detection and reduction Development of new in-line characterization techniques to prevent excursion, improve quality and yield Development of baseline 3Di technology Development of first 3Di products Continuous innovation in core process technology capability 12

13 DRAM Roadmap Scaling % YoY Bit Growth Continued technology scaling to increase Gb/cm 2 Past scaling has been dominated by array Increasing challenges with array patterning Parasitics not scaling Pitch cells are also hitting barriers Result: Continuous reduction in bit growth improvements from technology scaling Need significant innovation to enable continuous scaling and improve bit growth 13

14 DRAM Scaling Challenges ARRAY Capacitor structure Paradigm shift may be needed for cost effective scaling Bit line and Word line Materials innovation required Advanced device engineering To address materials/process limitations Overlay and patterning demands May drive EUV adoption Gap fill of narrow structures Need low T solutions Advanced characterization HAR measurements, OCD (bottom of containers) Cell Contact Wtotal 6~7nm Materials development required to improve array efficiency and word line/bit line resistance Technology Node 14

15 NAND Roadmap Scaling Planar NAND scaling Cost/GB Planar NAND can still be scaled below 16nm, but performance & cost are not competitive with 3D 3D NAND scaling 3D NAND cost improvement over planar expands with subsequent nodes 3D cell architecture enables significant performance improvement relative to planar technology GB/cm 2 34nm Future Technology Projection 48-tier TLC 32-tier TLC 64-tier TLC 96-tier TLC 25nm 20nm 16nm 1Znm 1Z'nm 25nm Technology Node Future Cost Projection 20nm MU 32-tier MLC 32-tier TLC Technology Node 3D NAND PLANAR TLC PLANAR TLC 16nm 1Znm 1Z'nm 3D NAND 48-tier TLC 64-tier TLC 96-tier TLC 15

16 Vertical NAND Scaling Challenges Tier Stack Scaling High aspect ratio etch capability Thin film deposition in high AR structures Uniformity WIW, WIF, WID, but also within localized high aspect ratio structures Advanced characterization HAR measurements, OCD, embedded defects and measurements Staircase Contact Scaling Advanced gap fill requirements for range of dimensions Low temperature films deposition and treatment Demanding Planarization Thick film removal, new films, tighter uniformity specifications 16

17 Packaging Technology Challenges Development and deployment of baseline 3Di manufacturing processes Transition from discrete-packaged memory to inpackage memory Thermal management of memory which shares a thermal solution with the ASIC or is inside the ASIC package Control of warpage/coplanarity for ultra-thin dice used in ultra-thin packages Accelerating development cycles, especially for market segments with short product life cycles 17

18 Recent Technology Announcements Floating Gate 3D NAND March D XPoint Non-Volatile Memory July X higher capacity than existing NAND technologies due to smallest cell size Enables >10TB in a standard 2.5 SSD 1000X faster than NAND 1000X endurance of NAND 10X denser than conventional memory 18

19 Future Memory Technology CAPACITY/LATENCY LOW CPU RAM Class SSD DISK CACHE FAST SLOW Storage Memory MEMORY STORAGE HIGH DRAM Emerging Memory NAND Balancing Value: Latency, Endurance, Volatility, Cost DRAM Memory Mapped Storage Mapped NAND Latency 1x 2x 10x 1000x 19 Endurance ~10 15 ~10 13 ~10 7 ~10 3 Non-volatile No No Yes Yes Cost DRAM ~DRAM ~0.2x DRAM NAND

20 The Search for Successful New Memory Technology RRAM +V -V Cu/Ta Top lead STT MRAM Cu, Ag etc,. CoFeB MgO CoFeB Free layer Barrier Fixed Layer MTJ PtMn Antiferromagnet W, TiN etc,. Cu/Ta MTJ Bottom lead PCM FeRAM + Polymers Nanotubes Nanowires Magnetics It s a great time to be a materials engineer! Explosion of new memory concepts Investigation focused on unique material systems and product development 20

21 Patterning with DSA: Challenges and Opportunities 21

22 Impacts of Process Complexity Large increase in number of process steps to enable shrink Conversion capex scales with the number of steps Significant reduction in wafer output per existing cleanroom area Complexity comparison for enablement of ~100% bits/wafer increase 50nm 30nm 30nm 20nm Number of Process Steps +14% +39% Number of non-litho Steps per Critical Mask Level +40% +114% Cleanroom Space per Wafer Out +14% +81% 50nm 30nm 20nm 50nm 30nm 20nm 50nm 30nm 20nm 22

23 Typical 6f 2 DRAM Array Layout DRAM Patterning Challenges Active Area Active area: Smallest pitch, discrete structures Word Line and Digit Line: L/S suitable for SADP or SAQP Periphery: Tight pitch 2D patterning Word Line Digit Line 23

24 Active Area Patterning Dense lines are initially formed by SADP or SAQP Lines are then chopped to create islands DSA has an opportunity to replace SAQP for dense line patterning, when ready and cost competitive Contact chop pattern 1Ynm 1Znm LELE Beyond 1Znm, EUV Option (1Znm and beyond) High NA, EUV, single print 24

25 Storage Node Patterning Storage Node DRAM Patterning Challenges Active Area Active area: Smallest pitch, discrete structures Digit Line Word Line Word Line and Digit Line: L/S suitable for SADP or SAQP Periphery: Tight pitch 2D patterning Storage Node: Dense CH, needs low LCDU 25

26 Storage Node Patterning ArF Immersion EUV DSA CHIPS Flow Main challenge is local CD uniformity CD uniformity needs improvement for single patterning Potential path but need to address LCDU, defects, placement error 26

27 Normalized Cost per step Cost of Ownership and Performance SAQP LiNe SMART EUV Relative COO is a reliable way to judge viability of new technology in industry. These studies assumed maturity. Why we need SIS: Method LER (nm) LiNe 3.2 SMART Study A Study B LiNe + SIS 2.4 SMART + SIS

28 DSA Adoption Challenges Defectivity Needs to improve by a few orders of magnitude Pattern roughness Needs to be comparable or better than SAQP SIS and other post processing may help, but add cost, complexity and potentially defectivity Process/Integration complexity Pattern placement error and overlay issues need to be further studied Cost Integration issues such as termination, edge of array, etch, alignment and overlay marks Cost advantage over SAQP needs to be significant 28

29 Highlights Exciting time for memory: diversifying markets, new applications Trend is 3D and materials innovation Lots of challenges ahead in both silicon processing and package development Winning patterning technologies have to win for performance and cost 29

30 Thank You 30

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