University of Minnesota Department of Electrical and Computer Engineering Spring 2009 EE 5545 Digital Signal Processing Design

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1 University of Minnesota Department of Electrical and Computer Engineering Spring 2009 EE 5545 Digital Signal Processing Design Introduction: Since the late 1980s, DSP education has been positively impacted by the introduction of software and hardware tools that allowed instructors to help students develop more thorough understanding of DSP algorithms while working with real-world data. MATLAB allowed both instructors and students to invest their creative abilities in the analysis, design and verification of algorithms while minimizing tedious programming tasks. Since the early 1990s, MATLAB has become an integral part of DSP education from junior-level undergraduate to advanced graduate-level courses. In addition, the introduction of low-cost development systems based on single-chip DSP processors allowed numerous universities to introduce real-time DSP laboratory courses that allowed students to see and hear the result of the DSP theory taught in lecture. It is possible to package DSP laboratories in a way that allows students to implement real-time DSP algorithms with high degree of abstraction thus allowing a larger cross section of students to have hands-on experience in this area. However, an understanding of the fundamentals of DSP processors, in terms of their architectures and special features, is essential for future designers and educated users of this technology. This calls for lecture/laboratory courses for real-time DSP design experience covering relevant software and hardware design and verification tools. DSP Design Platform: This is a 3-credit hour lecture/laboratory course employing the Spartan 3E FPGA platform from Xilinx for real-time DSP Design. The course will employ MATLAB and Simulink for analysis and design of DSP algorithm. In addition, Xilinx System Generator Blockset will be used (in conjunction with Simulink) allowing seamless transition from MATLAB-based algorithm design to VHDL code generation and co-simulation for design verification. The laboratory experiments will employ these software design tools, along with ISE Foundation, for implementation of real-time DSP algorithms (e.g. FIR filtering) with high level of abstraction in the first few laboratory sessions. Later experiments will address implementation issues and hardware cost in greater detail by examining the chip resources used for a variety of possible design alternatives (e.g. coefficient wordlengths, truncation vs. rounding, saturation vs. overflow, etc.) 1

2 Rationale: Prerequisites: Objectives: Catalog Description: Description: FPGA-based DSP platforms offer a great deal of flexibility and longevity for teaching purposes, especially for project oriented classes. The recent integration of DSP and hardware design tools for these platforms (e.g. MATLAB/Simulink and ISE Foundation) allow us to gradually bring the students to understand the performance of their designs at any level of detail starting from a high level of abstraction. In addition, students will have the opportunity to examine a variety of design alternatives and compare them in terms of used chip resources, speed, power consumption, etc. The main reason behind choosing the Spartan 3E platform for this laboratory is the obvious commitment of Xilinx to their university program. In addition, FPGAs in general offer a great vehicle to illustrate the fundamental ideas of real-time DSP design better than any single-chip DSP processor. EE 4541 Digital Signal Processing Design and implementation of real-time digital signal processing algorithms using modern DSP platforms. Real-time implementation of digital signal processing algorithms, including filtering, sample-rate conversion, and FFT-based spectral analysis; implementation on a modern DSP Platform; processor architecture; arithmetic operations; real-time processing issues; processor limitations. Lecture: Architectural features of DSP processors: arithmetic, memory organization, and the use of specialized on-chip hardware, e.g. multipliers. DSP Design Tools and Methodologies. Numeric Implementation and Arithmetic; scaling and overflow. Memory Architecture and Special Addressing: MAC FIR; Radix-2 FFT; Adaptive FIR. Execution Control. Peripherals and I/O handling. Laboratory: Using the Xilinx System Generator in MATLAB s Simulink. Design and Implementation of FIR filters on Xilinx FPGAs (e.g Spartan 3). Design Verification Using Co-simulation. Hardware cost: the cost of abstraction. Address Generation Control Logic. Design of MAC-based FIR filter. Design and Implementation of IIR filters. Special Implementation Issues: Overflow, scaling, finite wordlength effects. Implementation of real-time Radix-2 FFT. Implementation of adaptive FIR filters. Grading: Structured Lab 30% On-line Assessments 15% Exam 25% Final Project 30% 2

3 Structured Lab: As- On-line sessments: Exam: Computer Facilities: Nine structured weekly experiments are given starting the first week of the semester. After a tutorial introduction to the ISE foundation, these experiments start by introducing the students to Simulink with DSP and Xilinx System Generator Blockset and conclude with the implementation of advanced DSP algorithms such as adaptive filtering. Students will perform these experiments in groups of two or three (two is preferred). Students will have unlimited access to the laboratory throughout the semester. However, they are expected to show up during regular lab hours. One report on each experiment is required from each group of students. Quizzes covering pre-lab material as well as previous experiments will be given from time to time. Three WebVista-based assessments will be given on February 12, March 11, and April 15. These 50-minute long assessments will contain problems relating to the lecture material. In addition, some problems will address the integration between lecture and laboratory material. One exam covering the fundamental theory and applications of real-time DSP algorithms will be given upon completion of the structured laboratory. The exam will be open books and notes and will be held at the regular lecture time on April 15, MATLAB (including Simulink with the DSP and Xilinx blocksets) and ISE Foundation are available on all PCs in the DSP laboratory. Final Project: Final Report: Text: A list of suggested projects will be offered the 4th week. Students are also encouraged to come up with their own ideas on real-time DSP algorithms. Groups of 3-4 students are preferred, but individual circumstances and nature of selected project will be the determining factor as to the size of the group. One report from each group will be due at the end of the semester (actual due date to be determined later). The report should contain (at least) an abstract, an introduction, a theory section, a results section, a discussion section, a conclusion section, and a recommendation for future work section. A complete bibliography must be included and sources should be properly cited in the text of your report. Reporting requirements may be different for students wishing to use this course to satisfy the MSEE Plan C requirements. A standard DSP textbook such as Proakis and Manolakis is recommended, but not required. Instructor notes will be handed out or posted on the web site as needed. 3

4 References: P. Lapsley, J. Bier, A. Shoham, E.A. Lee, DSP Processor Fundamentals, IEEE Press, J. Proakis and D. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th Edition, Prentice Hall, C.H. Chen, Ed., Signal processing Handbook, Dekker, A.V. Oppenheim and R.W. Schafer, Discrete-Time Signal Processing, Prentice-Hall, 2nd Edition, M. El-Sharkawy, Digital Signal Processing Applications with Motorola s DSP56002 Processor, Prentice Hall, S. K. Mitra, Digital Signal Processing: A Computer-Based Approach, 3rd Edition, McGraw-Hill, Selected recent articles from IEEE Transactions on Signal Processing and the IEEE Signal Processing Magazine. 4

5 COURSE OUTLINE Week of Topic Labortory Jan 19 DSP Processor Architecture: Von Neumann and Harvard Processors; Memory Organization; Single-Chip DSPs vs. ASICs vs. FPGAs. Xilinx Virtex II and Spartan 3 Platforms. Introduction to the Lab: Tutorial overview of the ISE design tools. HDL design flow and incircuit verification on the Spartan 3E Starter Kit Board. Jan 26 Arithmetic: Multiply and accumulate (MAC); Fixed- Point and Floating-Point Numbers; Fractional Arithmetics; Quantization; Overflow; Accuracy; Dynamic Range. MAC Design using VHDL and Core Generator. Design Verification using simulation. Onchip verification using Chip- Scope. Feb 2 Digital Filtering: FIR Filtering; Overflow and Scaling; Realtime Implementation Issues. MAC Design using Simulink and Xilinx System Generator Blockset. Feb 9 Digital Filtering: IIR Filtering; Stability; Overflow and Scaling; Direct Form and Cascade Realizations. On-line Assessment # 1 February 11. Design and Implementation of FIR Filters. Design Verification Using Co-Simulation. Feb 16 Feb 23 March 2 Digital Filtering: Direct Form II Transpose and other filter structures. Overflow and scaling. Digital Filtering: Adaptive FIR Filter Implementation; The Least Mean Squares Algorithm; Convergence; Real-time Implementation Issues. IIR Filter structures: 2nd order sections and cascade implementations. MAC-based FIR filters. Hardware Cost for DSP operations. Address Generation Control Logic. March 9 Fast Fourier Transform: Radix-2 DIT Algorithm; Bitreversed Addressing. On-line Assessment # 2 March 11. March 23 Fast Fourier Transform: Scaling and Overflow; Real-time Implementation and Memory Requirements. March 30 Multirate DSP: Decimation and Interpolation; Implementation issues. April 6 Filter Structures Revisited: Transposed FIR filters and other structures; Retiming. Advanced FPGA chips: Virtex- 4 and the DSP48 slice. Real-time Adaptive FIR Filter Implementation. Real-time radix-2 FFT Implementation. Project. Project. April 13 Example Single-Chip DSP Processors: VLIW architectures; DSP/MCU hybrids. On-line Assessment # 3 April 15. Project 5

6 April 20 Example Single-Chip DSP Processors: DSPs for multimedia applications. Project. April 27 Review. Exam April 29 Project. May 4 Design Review Meetings Project Design Demonstration. 6