A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number


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1 A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number 1 Tomohiro KAMIMURA, 2 Akinori KANASUGI 1 Department of Electronics, Tokyo Denki University, 2 Graduate School of Engineering, Tokyo Denki University, Abstract Genetic algorithm (GA) is one of optimization algorithm based on an idea for evolution of life. GA can be applied various combination optimization problem. This paper proposes a parallel processor for distributed genetic algorithm (DGA) with redundant binary number. Since a redundant binary number has redundancy, solution expression becomes variegated. For this reason, it is expected the algorithm easily find the optimized solution, and the error rates decrease. Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. The effectiveness of the proposed processor was confirmed by some simulations and experiments using FPGA circuit board. 1. Introduction Keywords: Parallel Processor, Distributed GA, Redundant Binary Number Genetic algorithm (GA) is one of optimization algorithm based on an idea for evolution of life [1]. GA can be applied various problems such as combination optimization problem, machine learning and so on. A distributed genetic algorithm (DGA) divides a solution group into some solution groups island, and performs genetic operation in each island [2]. In DGA, in order to exchange the solution among each island, migration operation is performed. Since DGA has few numbers of individuals per island, premature convergence takes place easily. However, since diversity is also maintainable by migration, compared with conventional GA, effective solution search is expectable. This paper proposes a novel DGA with redundant binary number, while conventional DGA expresses chromosomes in binary number. Since a redundant binary number has redundancy, solution expression becomes variegated. For this reason, it is expected the algorithm easily find the optimized solution, and the error rates decrease. In the proposed algorithm, different numerical systems are used on each island. Therefore, since diversity is further maintainable, the further improvement in performance is expectable. Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. The effectiveness of the proposed processor was confirmed by some simulations and experiments using FPGA circuit board. 2. Distributed genetic algorithm A Genetic algorithm (GA) is proposed in 1975 by Prof. John Holland. The algorithm is based on Darwin's evolutionary theory and likens solution to gene. The flow chart of GA is shown in figure 1. The procedure of GA is as follows. (1) Initialization: The first process decides initial genotype, namely value and genetic length. For example, if we assume values are 0 and 1, and length is 8, a chromosome is shown in figure 2. (2) Evaluation: The second process calculates the fitness for each individual with the target function. The evaluation depends on each problem. (3) Termination Judgment: If the process satisfies the termination condition, the operation finishes and output the individual with the best fitness as the optimized solution. (4) Selection: To generate the children, this process chooses parents from individuals. For example, if we assume parents the first generation, children become the second generation. The children International Journal of Information Processing and Management(IJIPM) Volume 4, Number 1, January 2013 doi: /ijipm.vol4.issue
2 generate the next children again. The children inherited the characteristic of the parents are generated in this way. (5) Crossover: This process crosses individuals chosen by selection operation and generates the individuals of the next generation. Example of crossover operation is shown in figure 3. (6) Mutation: This process mutates the chromosome of new generation. The mutation is effective to escape from a local optimum solution. Example of crossover operation is shown in figure 4. Figure 1. Flow chart of GA Figure 2. An example of chromosome Figure 3. Example of crossover operation 2.1. Distributed genetic algorithm Figure 4. Example of mutation operation A distributed genetic algorithm (DGA) divides a solution group into some solution groups island, and performs genetic operation in each island. In DGA, in order to exchange the solution among each island, migration operation is performed (figure 5). Since DGA has few numbers of individuals per island, premature convergence takes place easily. However, since diversity is also maintainable by migration, compared with conventional GA, effective solution search is expectable. Figure 5. Concept of distributed genetic algorithm (DGA) 99
3 2.2. Redundant binary number In this paper, redundant binary number system is utilized [3]. The advantage of GA with redundant binary number is increase of total expression number of optimized solution. From this advantage, we can expect that improvement in the searching speed and decrease of the error rate. The redundant binary number uses values 0, 1 and 1. However, because hardware cannot deal the value 1, we express each genetic information in two bits. We assume that 0 sets 00 or 11, 1 sets 01, 1 sets 10. These correspondences are summarized in table 1. For example, we express decimal number seven in binary number of the four bits precision and redundant binary number, as shown in figure 6. As shown in figure 6, chromosomes of the redundant binary number become longer in comparison with the normal binary number. However, there are many expression way. For example, there are nine ways in the case of figure 6. The GA based on redundant binary number is almost the same as conventional GA. However, decoding from redundant binary number to binary number is required. In this paper, we separate chromosomes into odd number bit and even number bit. Then we subtract even number bit from odd number bit. An example is shown in figure 7. Table 1. Bit strings of genetic information Bit String 00, Figure 6. A comparison between binary number and redundant binary number 3. Proposed DGA Figure 7. Decoding method from redundant binary number to binary number The concept of DGA proposed in this paper is shown in figure 8. In this figure, GA_B, GA_G, and GA_RB express GA using binary number, GA using Gray code, and GA using redundant binary number, respectively. Figure 9 shows the selection method of a migration place. As shown in Fig. 9, one migration operation is performed in a ring shape. The number of the chromosomes which emigrate is one. The random number r chooses the island where a chromosome moves. A part of solutions are exchanged through the migration unit. Of course in the case of migration, code conversions are performed. Although search results depend on type of solution code, stable good results are expected to many problems by the proposed DGA. In Fig. 8, although there are two sets of GA with binary number, one set of GA with Gray code, and one set of GA with redundant binary number, this is only an example. Of course, various combinations are possible. In order to suppress the circuit scale, the composition of figure 8 was illustrated. Namely, since the scale is small, two sets of circuits treating a binary number are used, and since the scale is large, as for the circuit treating a gray code or a redundant binary number, only one set is used. 100
4 Figure 8. Concept of proposed DGA 4. Simulation Figure 9. The selection method of a migration place The evaluation by simulation was performed in four GA (binary number, Gray code, redundant binary and proposed DGA). The performance of each GA was evaluated by solving following three functions. f ( x) x (Solution: x 141) (1) f ( x) x (Solution: x 44721) (2) 2 f ( x) ( x 100)( x 40000) (Solution: x ) (3) The simulation program was implemented in C language. The error rates of three functions are summarized in figure 10. Each result is the average of 500 times of trial. The parameters are summarized in table 2. In addition, although the solution is denoted by 16 bits in GA with binary number and Gray code, the solution is denoted by 32 bits in GA with redundant binary number. In calculation of error rate, only the case where a solution is completely same as the optimal solution is judged as a correct answer. Therefore, if a solution is not in agreement with the optimal solution, even if very close to the optimal solution, it has judged as an error. Figure 10 shows that good results were obtained by the proposed DGA in various problems. 101
5 5. Design of processor Figure 10. Error rate Table 2. GA Parameters Parameter Value Generation 100 Population 32 (8 x 4) Selection Crossover Ranking One point Crossover rate 1 Mutation rate Since DGA is a parallel algorithm, the performance can be improved by using a specified parallel processor. Then, the processor which specialized in proposed DGA was designed. The block diagram is shown in Fig. 11. Figure 11. Block diagram The processor consists of four islands and one migration unit. Each island consists of a memory, a crossover unit, mutation units and an evaluation unit. Two islands are assigned to GA with usual binary number, one island is assigned to GA with gray code and one island is assigned to GA with redundant binary number. By using microprocessors for evaluation units, the proposed processor is applicable to many problems. However, in this paper, the specified evaluation unit for solving the abovementioned equation 2 was designed for simplification. The processor was described by VHDL. The integrated design environment ISE 11.1 of Xilinx Corporation was used for logic simulation and implementation. The target FPGA is Virtex4 (xc4vlx25) of Xilinx Corporation. Figure 12 shows the result of logic simulation. This simulation result shows that the suitable solution is obtained. The situation of experiment is shown in figure 13. The FPGA evaluation 102
6 board is connected to a display monitor, and the result is displayed. The result is displayed by the hexadecimal number. Since AEB1 of a hexadecimal number is of a decimal number, it is the right result. Figure 12. Logic simulation results 6. Conclusion Figure 13. Experiment with FPGA board In this paper, a parallel processor for distributed genetic algorithm with redundant binary number was presented. It was confirmed that the proposed processor was effective for improvement of error rate by simulation and experimental results. The future works are evaluation for practical problems. 7. Acknowledgement This work was supported by Tokyo Denki University Science Promotion Fund (Q12J03) 8. References [1] L. Davis, Handbook of Genetic Algorithms. Van Nostrand Reinhold, [2] R. Tanese, Distributed Genetic Algorithms, Proceeding of the 3rd International Conference on Genetic Algorithms, pp , [3] M. Aoshima, A. Kanasugi, A Processor for Genetic Algorithm based on Redundant Binary Number, Proceeding of AICIT International Conference on Convergence and Hybrid Information Technology, Vol.1, pp ,
7 [4] A. Murayama, A. Kanasugi, A novel coding method for genetic algorithms based on redundant binary number, Proceeding of International Symposium on Artificial Life and Robotics, pp , [5] P. Graham, B. Nelson, A hardware genetic algorithm for the traveling salesman problem on SPLASH2, Proceeding of International Workshop on Field Lecture Notes In Computer Science, Vol. 975, pp , [6] S. Seto, A. Kanasugi, A Novel Distributed Genetic Algorithm with Redundant Binary Number, Proceeding of AICIT International Conference on Information Science and Digital Content Technology, pp , [7] M. Aoshima, A. Kanasugi, A Processor for Genetic Algorithm based on Redundant Binary Number, Journal of AICIT Next Generation Information Technology, Vol. 1, No. 3, pp , [8] M. Murayama, A. Kanasugi, A Processor for GA based on Redundant Binary Number using FPGA, Journal of Next Generation Information Technology, Vol. 3, No. 3, pp. 19,
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