CONSUMER COMPUTER MEMORY COMMUNICATIONS. Slide No.1 2/22/00

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1 COMPUTER CONSUMER MEMORY COMMUNICATIONS Slide No.1

2 Agenda General Information Asynchronous SRAM Synchronous SRAM Flowthrough Pipelined NoBL SRAM Slide No.2

3 General Information 1 bit can have 2 combinations : 0 and 1 2 bits can have 4 combinations : 00, 01, 10 and 11 3 bits <=> 8 combinations 4 bits <=> 16 combinations bits <=> 1024 combinations Since any bit can have 2 combinations(0 or a 1), the total no. of combinations, k bits can have is 2 k. Slide No.3

4 General Information In Digital world, 1024 is termed as 1K. (1024 x 2) or (1K x 2) = 2048 is termed as 2K. 256K bits mean 262,144 bits (256 x 1024). 1M(Meg.) bits mean 1,048,576 bits (1K x 1K). No. of bits in a 32K x 8 SRAM is 32 x 1024 x 8 = 262,144. A group of 8 bits is called a Byte. SRAM s are always addressed in terms of bits. Slide No.4

5 SRAM Configuration What exactly do we mean by a 32K x 8 SRAM? 32K represents the depth of the SRAM x 8 represents the width of the SRAM Size of the SRAM = Depth * Width Size = 32 x 1024 x 8 = bits Depth means the no. of word locations Width means the size of each word So, a 32K x 8 SRAM has 32K(or more precisely 32,768) locations each capable of storing a byte(or 8 bits). A 4M SRAM could be a 128K x 32 or 256K x 16 or 512K x 8 or 1M x 4, etc. Slide No.5

6 256K x 36 SRAM Some SRAM s have parity bits in addition to the data bits. Parity bits are always associated with bytes. A 256K x 36 SRAM has 4 bits of parity associated with each byte. Often, the parity bits are ignored when talking about the size. A 256K x 36 SRAM is referred as an 8M SRAM. 256K locations need 18 lines to access them. These are address lines. 36 bits of data may need 72 data lines when the inputs and outputs are unidirectional and 32 data lines when they are bi-directional. Slide No.6

7 Memory Array combinations <=> 6 binary bits to select each of them uniquely = = = 2 Let the 6 bits be represented by bits A0-A = = = = 63 Slide No.7

8 A5 A4 A3 Memory Array(Contd.) Accessing these horizontal lines(or rows) need 3 bits A2, A1, A Accessing these vertical lines(or columns) need 3 bits A5, A4, A3. A2 A1 A0 Slide No.8

9 SRAM Memory array A0 A1 A2 A3 A4 A5 Row Decoder Column Decoder Data I/O Slide No.9 Configuration is 64 x 1. This assumes that each location contains one bit. What if each location(0-63) has multiple no. of bits, say 16? The result =>

10 SRAM(Contd.) Address bus A0 A1 A2 A3 A4 A5 Row Decoder Memory array Column Decoder D0 D1 D2 D3 D4 D5 D6 D13 D14 D15 Data bus Configuration is 64 x 16. Assumes that each memory location has 16 bits. Slide No.10

11 SRAM(Contd.) A0 A1 A2 A3 A4 A5 Row Decoder Memory array Column Decoder D0 D1 D2 D3 D4 D5 D6 D13 D14 D15 Addressing produces data (D0-D15) from location 2. Addressing produces data (D0-D15) from location 45. How do you write or read data into this SRAM? Slide No.11

12 SRAM(Contd.) A simple SRAM is controlled using a Chip enable signal(/ce), a Write Enable signal(/we) and an output enable signal(/oe). /CE signal is used to activate or deactivate the SRAM as a whole. This signal makes the other signals inactive when deselected. /WE signal is used to select between a READ or a WRITE operation. A low on /WE signal signifies a write and read otherwise. /OE signal is used to drive the data onto the data bus from the memory array of the SRAM in the READ mode. In Control Buffer Out Control = 1 => Out = In; Control = 0 => Out = High Z(or High Impedance) Slide No.12

13 SRAM(Contd.) Read Logic Address /OE /CE /WE Logic Row Decoder Memory Array Column Decoder Data I/O Write Logic What is this? Answer : Simple Asynchronous SRAM. Slide No.13

14 Operation of an Asynchronous SRAM Read Operation /CE /WE /OE Address Data t AA Slide No.14

15 Operation of an Asynchronous SRAM Write Operation /CE /WE Address Data /OE is a don t care during a write operation. Slide No.15

16 Summary of Asynchronous SRAM Responds to any change in the inputs as long as the /CE signal is asserted. Timing specifications become stringent as we enter into high speeds which is difficult to handle. Some older SRAM s used to have separate inputs and outputs which used to consume more no. of pins. Some SRAM s with separate inputs and outputs used to have a transparent write, i.e. data could be seen at the outputs while writing into the SRAM. Applications PC cache DSP interface As a buffer to store the data temporarily Wireless Devices Slide No.16

17 Register A Register is an element which is capable of storing binary data. A clock is a stream of positive and negative pulses occurring at regular intervals. Positive pulse is always preceded or succeeded by a negative pulse. A register can be activated only at the edges of the clock. Data In Data Out Clock Positive pulse Negative pulse Rising edge Falling edge clock Register Data In Data Out A combinatorial signal doesn t pass through registers. A combinatorial logic responds to any change in the inputs. It is not controlled by a clock. Slide No.17

18 Asynchronous SRAM + Clock = Synchronous SRAM Synchronous SRAM Address Read Logic /OE /WE clock Logic Row Decoder Memory Array Registered Data I/O /CE Column Decoder Asynchronous SRAM Synchronous SRAM Write Logic Synchronous SRAM s are subdivided into Flow-through and Pipelined SRAM s depending on the output data being registered or not. Slide No.18

19 Flow-through(F/T) Synchronous SRAM If the outputs are not registered(or combinatorial), then the synchronous SRAM is a flow-through SRAM. Address Read Logic /OE /WE clock Logic Row Decoder Memory Array Data I/O clock /CE Column Decoder Asynchronous SRAM Synchronous SRAM Write Logic Slide No.19

20 Pipelined(P/L) Synchronous SRAM If the outputs are registered, then the synchronous SRAM is a Pipelined SRAM. Address Read Logic /OE /WE clock Logic Row Decoder Memory Array Data I/O clock /CE Column Decoder Asynchronous SRAM Synchronous SRAM Write Logic Slide No.20

21 Write Operation Clock /CE Operation of F/T and P/L SRAM s A and B are 2 address locations into which X A and X B are written into for the Flow-through and Y A and Y B for the Pipelined SRAM. Write operations are the same for both the P/L and F/T operations. Why? /WE Write operations ignore the state of the /OE signal. Address A B A single signal F/T Data I/O X A X B A group of signals or a bus. P/L Data I/O Y A Y B Don t care Slide No.21

22 Read Operation Clock Operation of F/T and P/L SRAM s /CE /WE Address A B /OE t cdv F/T Data I/O X A X B P/L Data I/O t co Latency of 1 clock cycle Y A Y B Slide No.22

23 Burst Read Operation Burst Cycles Clock /CE /WE ADV/LD Address A /OE F/T Data I/O t cdv A0 A1 A2 A3 Slide No.23

24 Burst Operation Can read/write 4 pieces of data from/into 4 different address locations by taking a single address. Accomplished by generating the addresses internally after latching in an initial address. Modifies the last 2 significant bits of the address(at each rising edge of the clock) thereby generating four combinations. The other bits are the same for all the other 3 addresses generated. Example: Assume the address to an SRAM on which burst is performed be : 01 is the least 2 significant bits which would be modified. The other combinations that would be produced are 00, 10 and 11. These combinations coupled with the 6 most significant bits produces 3 addresses , and into which the respective data would be written into or read from. Slide No.24

25 Types of Burst Sequences In what order does the SRAM generates the combinations? Two types of Burst sequences Linear Burst Motorola Interleaved Burst Intel Linear Burst Pure binary increment : 00 -> 01 -> 10 -> 11 -> 00 -> 01 ->.. If the starting sequence is 01 for instance, the subsequent combinations are 10, 11 and 00, then loops back to 01 and continues on and on. Doesn t depend on the starting address sequence. Interleaved Burst Depends on the starting address sequence. Burst is initiated on the SRAM s using an ADV/LD signal. Slide No.25

26 Wanted to show how data is latched on the next rising edge by the peripheral Controls Processor /CE /WE /OE Address Data I/O Synchronous SRAM Clock Pieces of data Slide No.26

27 Wait states in Synchronous SRAM Read/Write operation(f/t) Clock /CE Read Read What if a Write is needed? A write is possible. As data to the write need to be presented at the same rising edge, it is not possible to do a write when the read data is being latched by the peripheral device. As a result, there will be contention and ultimately a cycle is eaten up. /WE How many cycles are wasted for a Pipelined SRAM between a conse -cutive read and write cycles? Address A B C How is this problem solved? /OE F/T Data I/O t cdv X A X B X c Slide No.27

28 Summary of Synchronous SRAM A F/T SRAM is used where the latency is a critical issue and a P/L SRAM is used where the speed is a critical issue. Write operations take a single clock cycle to complete for both F/T and P/L SRAM s. Read operations take 2 clock cycles in a F/T SRAM wherein the second clock cycle cannot be utilized for a new operation. Read operations take 3 clock cycles in a P/L SRAM wherein the second and third clock cycles cannot be utilized for a new operation. Due to these disadvantages, Synchronous SRAM s are not used for Networking applications where frequent read/writes are very common. Most of the synchronous SRAMs can be accessed at byte levels by providing extra control signals. Slide No.28

29 Eliminating Wait states Wait states arise because of the write and read cycles being irregular. Wait states in Synchronous SRAMs can be eliminated by pushing each write cycle ahead rather than providing data in the same clock cycle. Write cycle should be pushed ahead by 1 clock cycle for a F/T SRAM and 2 clock cycles for a P/L SRAM to realize consecutive reads and writes. Clock Now a write is possible here Write Read Write Write Data I/O This is for a F/T SRAM. Slide No.29

30 NOBL(No Bus Latency) SRAM Address Read Logic /OE /WE Clock /CE Logic Row Decoder Memory Array Column Decoder Data I/O clock Asynchronous SRAM Synchronous SRAM Write Logic NoBL Logic NoBL SRAM This is the block diagram of a F/T NoBL SRAM. A P/L SRAM would have registered outputs. Slide No.30

31 NoBL Operation Clock Write Read Write Write Read /WE /CE Address A B C D E P/L Data I/O Data in A B C D Data in Data out Data in Data out Slide No.31

32 NoBL Operation Clock Write Read Write Write Read /WE /CE Address A B C D E F/T Data I/O A B C D Data in Data out Data in Data out Slide No.32

33 Performance Improvement 13.5 Gb/s Input Ports ASIC/ Data Control Output Ports 6.75 Gb/s Memory Throughput Std. Sync. NoBL Memory Block All Reads/ All Writes Memory Interface - 90 bits wide/ Operating at 150 Mhz 50% Reads 50% Writes Slide No.33