Chapter 8: Memory Management 籃玉如

Transcription

1 Chapter 8: Memory Management 籃玉如 Part Four: Memory Management Chap 8 Memory-Management Strategies Chap 9 Virtual-Memory Management 2 1

2 Chapter 8: Memory Management 8.1 Background 8.2 Swapping 8.3 Contiguous Memory Allocation 8.4 Paging 8.5 Structure of the Page Table 8.6 Segmentation 8.7 Example: The Intel Pentium (X) 3 Background 電腦系統中, 記憶體是系統的重心 記憶體本身是一個大型的字組或位元組陣列, 各字組和位元組都各有其位址,CPU 是根據程式計數器的數值到記憶體的位址擷取指令 這些指令可能會造成對於特殊記憶體位址的額外載入或儲存動作 4 2

3 8.1.1 Basic Hardware 主記憶體和建立在處理器內的暫存器是 CPU 唯一可以直接存取的儲存體 Machine instructions 使用記憶體位址做為參數, 沒有使用磁碟位址做為參數 因此, 任何執行的指令, 和任何被這些指令使用的資料必須放在這些直接存取儲存裝置之內 如果資料不在記憶體內, 則必須在 CPU 操作它們之前移到記憶體之中 OS process process base process limit Fig. 8.1 A base and a limit register define a logical address space. Fig. 8.2 Hardware address protection with base and limit registers Address Binding Binding of Instructions and Data to Memory: Address binding of instructions and data to memory addresses can happen at three different stages Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers). 6 3

4 Fig. 8.3 Multistep Processing of a User Program Logical vs. Physical Address Space Logical address An address generated by the CPU; also referred to as virtual address Physical address an address seen by the memory unit, that is, the address loaded into the memory-address register of the memory. Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme 8 4

5 Memory-Management Management Unit (MMU( MMU) Hardware device that maps virtual to physical address In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory The user program deals with logical addresses; it never sees the real physical addresses 9 Fig. 8.4 Dynamic relocation using a relocation register 10 5

6 8.1.4 Dynamic Loading 行程大小受限於實體記憶體大小 要得到較佳之記憶體空間使用效率, 可採行動態載入 (dynamic loading) 主程式儲存在主記憶體並執行, 當需要呼叫其它程式時, 首先看看此程式是不是已經存在記憶體內, 如果不是, 便呼叫重定位鏈結載入程式 (relocatable linking loading), 將所需要的程式載入主記憶體內, 並更新行程位址表的內容 然後控制就轉移給新的載入程式 Dynamic Linking and Shared Libraries 採用動態鏈結, 在程式參用程式庫副程式處便做一記號 (stub), 該記號為一小段程式來指示如何去找尋適當的記憶體常駐程式庫副程式, 或是如何載入程式庫副程式 ( 如果不在記憶體中時 ) 當執行到記號處時, 首先檢查所需要的副程式是否已經存在記憶體中 如果該副程式不在記憶體中, 程式會將它載入到記憶體中 12 6

7 Swapping A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution Backing store fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images Roll out, roll in swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped 13 Schematic View of Swapping Fig. 8.5 Swapping of two processes using a disk as a backing store. 14 7

8 Context-Switch time in Swapping System Contiguous Allocation Main memory usually into two partitions: Resident operating system, usually held in low memory with interrupt vector User processes then held in high memory Memory allocation 的兩個基方式 : Contiguous allocation: each process is contained in a single contiguous section of memory. Non-contiguous allocation: 利用 linked 的方式 16 8

9 8.3.1 Memory Mapping and Protection Fig. 8.6 HW support for relocation and limit registers Memory Allocation How to satisfy a request of size n from a list of free holes (available memory) First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization 18 9

10 8.3.3 Fragmentation External Fragmentation total memory space exists where there is enough total memory space to satisfy a request, but it is not contiguous storage is fragmented into a large numbers of small holes. Depending on the total amount of memory storage and the average process size, external fragmentation may be a minor or a major problem. 例如,first fit 的統計分析顯示縱使具有某些最佳條件, 在給予 N allocated blocks, 由於 fragmentation 也將遺失其它的 0.5N, 那麼三分之一的記憶體可能沒有利用到, 這就是著名的百分之五十規則 (50-percent rule) Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Fragmentation External Fragmentation total memory space exists where there is enough total memory space to satisfy a request, but it is not contiguous storage is fragmented into a large numbers of small holes. Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used 20 10

11 8.3.3 Fragmentation The solutions to the problem of external fragmentation: Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time Permit the logical address space of the processes to be noncontiguous Paging (8.4) Segmentation (8.6) Paging Paging is memory-management scheme that permits the physical address space of a process to be noncontiguous Basic Method 將 memory 實際區分成固定大小 blocks, 稱為 frames, 而程式欲執行時經由 OS 形成 logical memory 也分成等長的 blocks, 稱為 pages 執行前程式之 pages 必須載入於 available 之 frames, 而且有一個 page table 用來紀錄這些 mapping 的情形 22 11

12 Fig. 8.7 Paging hardware. 23 Fig. 8.8 Paging Model of logical and physical memory 24 12

13 The page size (like the frame size) is defined by the hardware. Page 的大小通常是 a power of 2, 從 512 bytes 到 16MB 之間 利用 a power of 2 作為一個 page 的大小的好處為 : 讓 logical address 容易轉換為 a page number & page offset page number p m-n page offset d n 25 Logical address 0 map Physical address Fig. 8.9 Paging example for a 32-byte memory with 4-byte pages

14 Before allocation After allocation Fig Free frames (a) before allocation and (b) after allocation Hardware Support Translation look-aside buffer (TLB) A fast-lookup hardware cache The TLB contains only a few of the page-table entries. When a logical address is generated by the CPU, its page number is presented to the TLB. If the page number is found, its frame number is immediately available and is used to access memory. If the page number is not in the TLB (known as TLB miss), a memory reference to the page table must be made. When the frame number is obtained, we can use it to access memory. We add the page number and frame number to the TLB, so that they will be found quickly on the next reference

15 Fig Paging hardware with TLB. 29 Effective Access Time Hit ratio: percentage of times that a page number is found in the TLB Assume TLB Lookup time = 20 nanoseconds Assume memory cycle time (access memory)= 100 nanoseconds Hit ratio = 80 Effective Access Time (EAT) =? 30 15

16 8.4.3 Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: valid indicates that the associated page is in the process logical address space, and is thus a legal page invalid indicates that the page is not in the process logical address space 31 Fig Valid (v) or invalid (i) bit in a page table 32 16

17 8.4.4 Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes Private code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space 33 Fig Sharing of code in a paging environment 34 17

18 8.5 Structure of Page Table Hierarchical Paging Hashed Page Tables Inverted Page Tables Hierarchical Page Tables Most modern computer systems support a large logical address space The page table itself becomes excessively large We would not want to allocate the page table contiguously in main memory. Solution: Break up the logical address space into multiple page tables A simple technique is a two-level page table 36 18

19 Fig A two-way page-table scheme. 37 Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into: a 10-bit page number a 10-bit page offset Thus, a logical address is as follows: page number page offset p i p 2 d where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table 38 19

20 Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture Fig Hashed Page Tables Common in address spaces > 32 bits The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted

21 Fig Hashed page table Inverted Page Table One entry for each real page of memory Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one or at most a few page-table entries 42 21

22 Fig Inverted page table Segmentation A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, stack, arrays Fig User s view of a program 44 22

23 8.6.1 Basic Method Segmentation: is a memory-management scheme that supports user view of memory A logical address space is a collection of segments Each segment has a name and a length Implementation: segments are numbered and are referred to by a segment number. A logical address consists of a two tuple: <segment-number, offset> Hardware Logical address consists of a two tuple: <segment-number, offset>, Segment table each table entry has: base contains the starting physical address where the segments reside in memory limit specifies the length of the segment 46 23

24 Fig Segmentation hardware. 47 Fig Example of segmentation