Protel DXP 2004 Schematic 開 始 所 有 程 式 Altium DXP 2004

Transcription

1 Protel DXP 2004 Schematic 開 始 所 有 程 式 Altium DXP

2 File New PCB Project 2

3 Save Project As Right click Project 儲 存 路 徑 不 可 以 有 中 文 3

4 D:\Exercise Project 儲 存 路 徑 不 可 以 有 中 文 4

5 Add New to Project Schematic 新 增 一 個 電 路 圖 檔 Right click 5

6 Save As 建 議 電 路 圖 檔 儲 存 至 Project 相 同 路 徑 底 下, 儲 存 路 徑 不 可 以 有 中 文 Right click 6

7 D:\Exercise 建 議 電 路 圖 檔 儲 存 至 Project 相 同 路 徑 底 下 7

8 View Workspace Panels System Libraries 打 開 零 件 庫 8

9 Libraries 零 件 庫 顯 示 視 窗 可 以 調 整 Top view 9

10 Libraries (Cont.) 10

11 Miscellaneous Devices.IntLib 可 指 定 不 同 的 零 件 庫 Miscellaneous Devices 內 有 各 式 常 用 零 件 11

12 Miscellaneous Connectors.IntLib Miscellaneous connectors 內 有 各 式 常 用 連 接 頭 12

13 Find Register 關 鍵 字 母 與 萬 用 字 元 尋 找 零 件 但 只 在 指 定 的 零 件 庫 中 尋 找 R* 13

14 Place component and edit properties R? Res1 1K Press and don t relax Double click 零 件 序 號 零 件 標 註 零 件 值 14

15 Miscellaneous Devices.IntLib Component Properties Q? 2N C E Q? B 2N Double click Q? 2N3904 C B E 2 3 C E Q? B 2N

16 View Toolbars Wiring Place Wire GND Power Port VCC Power Port Place No ERC 16

17 Wire Placement Modes SHIFT+SPACEBAR 17

18 Cut or Copy component 3 3 Click Click 1 Or 4 2 Selected object Click Delete 18

19 Cut wire and rotate component 1 Click Q? 2N Selected object Q? 2N3904 Q? 2N3904 Press + Space Q? 2N3904 Q? 2N Click Or Delete 19

20 Zoom in Zoom out & Accesskey 放 大 顯 示 比 例 按 鍵 或 按 住 鍵, 再 將 滑 鼠 上 的 滾 輪 往 前 推 將 滑 鼠 上 的 滾 輪 往 前 推 縮 小 顯 示 比 例 按 鍵 或 按 住 鍵, 再 將 滑 鼠 上 的 滾 輪 往 前 推 將 滑 鼠 上 全 圖 顯 示 比 例 按 鍵 或 鈕 指 定 區 塊 顯 示 比 例 按 鍵, 或 鈕, 然 後 在 工 作 區 裡 指 定 所 要 放 大 的 區 塊 : 放 大 顯 示 比 例 : 縮 小 顯 示 比 例 : 將 零 件 左 右 翻 轉 : 將 零 件 上 下 翻 轉 ( 空 白 鍵 ): 逆 時 鐘 旋 轉 90 度 : 放 置 該 零 件 : 取 消 取 用 該 零 件 : 開 啟 此 零 件 之 屬 性 對 話 盒 20

21 R1 1K C1 0.1F Q1 2N3904 R2 47K VCC R3 47K Exercise C2 0.1uF R4 1K Q2 2N3904 J1 COAX-F VCC JP Header 4 Description Designator Library Name LibRef Quantity Value Polarized Capacitor (Axial) C1 Miscellaneous Devices.IntLib Cap Pol uF Polarized Capacitor (Axial) C2 Miscellaneous Devices.IntLib Cap Pol uF Coax-F Connector J1 Miscellaneous Connectors.IntLib COAX-F 1 Header, 4-Pin JP1 Miscellaneous Connectors.IntLib Header 4 1 NPN General Purpose Amplifier Q1 Miscellaneous Devices.IntLib 2N NPN General Purpose Amplifier Q2 Miscellaneous Devices.IntLib 2N Resistor R1 Miscellaneous Devices.IntLib Res1 1 1K Resistor R2 Miscellaneous Devices.IntLib Res1 1 47K Resistor R3 Miscellaneous Devices.IntLib Res1 1 47K Resistor R4 Miscellaneous Devices.IntLib Res1 1 1K 21

22 R1 1K C1 0.1F Q1 2N3904 R2 47K VCC R3 47K Double Click Footprint C2 0.1uF R4 1K Q2 2N3904 J1 COAX-F VCC JP Header 4 Double Click 22

23 PCB Model Browse CAPPR2-5X6.8 C1 0.1F 23

24 Libraries Search protel 內 建 的 library 路 徑 關 鍵 字 母 與 萬 用 字 元 尋 找 零 件 Find 2N2222 Available Libraries: 從 已 掛 載 的 零 件 庫 中 尋 找 Libraries on Path: 從 Path 裡 的 零 件 庫 中 尋 找 Path: C:\Program Files\Altium2004\Library 24

25 Search result Q? 2N

26 Search LM311N 26

27 Libraries Add Library 增 加 可 供 選 用 的 零 件 庫 Install 掛 載 可 供 選 用 的 零 件 庫 預 設 路 徑 C:\Program Files\Altium2004\Library 27

28 Install 89c51.IntLib 28

29 29 Tools Auto Annotate 1K R? 1K R? 0.1F C? 0.1uF C? 47K R? 47K R? VCC VCC J? COAX-F JP? Header 4 Q? 2N2222 Q? 2N2222 1K R4 1K R1 0.1F C1 0.1uF C2 47K R2 47K R3 VCC VCC J1 COAX-F JP1 Header 4 Q1 2N2222 Q2 2N2222

30 Annotate Update Changes List OK Accept Changes [Create ECO]

31 Engineering Change Order Validate Changes Execute Changes Close Close

32 32 After Annotate 1K R4 1K R1 0.1F C1 0.1uF C2 47K R2 47K R3 VCC VCC J1 COAX-F JP1 Header 4 Q1 2N2222 Q2 2N U1 LM311N 200 R4 Res1 2K R1 Res1 10K R2 Res1 VCC VCC D1 10K R3 Res1 VCC 1 2 JP1 Header 2 VCC VCC 1K Rphoto Res1

33 PCB Printed circuit board 1

34 Project Add New to Project PCB Right Click 2

35 PCB1.PcbDoc Save As Right Click 建 議 電 路 圖 檔 儲 存 至 Project 相 同 路 徑 底 下, 儲 存 路 徑 不 可 以 有 中 文 3

36 Keep-Out Layer Select Keep-Out Layer 4

37 Place Line 畫 出 ㄧ 塊 夠 大 的 區 塊 即 可 5

38 Design Import Changes From PCB_PROJECT1.PRJPCB Validate Changes 4 Execute Changes 5 Close 6

39 Move 由 Schematic 轉 到 PCB 的 零 件 會 被 放 在 一 個 Sheet1 裡 面, 移 動 Sheet1 即 移 動 所 有 的 零 件 將 所 有 零 件 移 到 所 劃 的 框 內 若 無 法 順 利 轉 檔, 可 能 是 因 零 件 未 指 定 封 裝 (Footprint) 或 編 號 當 試 多 次 仍 未 成 功, 建 議 關 掉 並 刪 除 此 PCB 檔, 再 重 開 新 PCB 檔 7

40 Edit Cut 2 1 Click 清 除 Sheet1, 以 便 個 別 移 動 所 有 的 零 件 3 4 滑 鼠 變 為 十 字 游 標 8

41 Cut line Line 已 不 需 用 到, 可 刪 除 Layout VCC VCC JP1 1 Q1 B P2N2222A C E R1 Res1 C1 1K Cap Pol uF 2 R2 Res1 47K R3 Res1 47K R4 C2 Res1 J1 1K Cap Pol uF 2 1 C E Q2 B P2N2222A COAX-F Header

42 Alignment Tools 10

43 Auto Route All Routing Rules Close Route All 2 1 雙 層 板

44 Routing finished 12

45 PCB layers Top overlay Top layer Bottom layer 13

46 PCB operation = 2.54 mm Double click 14

47 PCB operation (Cont.) Double click 15

48 PCB operation (Cont.) 16

49 PCB operation (Cont.) 17

50 Rules Tools Un-Route All 1

51 Design Rules 2

52 PCB Rules and Constraints Editor Routing Width Width mil 千 分 之 一 英 寸 3

53 View Toggle Units mil mm mm millimeter 4

54 PCB Rules and Constraints Editor Routing Width Width Min With=0.6mm Preferred With=1mm Max With=3mm 5

55 PCB Rules and Constraints Editor Routing Width Width New Rules Right Click 6

56 Name Width_GND Net GND 7

57 PCB Rules and Constraints Editor Design Rules Routing Routing Via Style RoutingVias 2.5mm 0.8mm 8

58 Board Layer Top layer Insulator Bottom layer Place Via 9

59 AXIAL-0.3 Pad setting Resister & capacitor RAD-0.2 Connector HDR1X4 DIP-8 DIP IC & BJT 10

60 PCB Rules and Constraints Editor Design Rules Electrical Clearance Clearance 11

61 PCB Rules and Constraints Editor Design Rules Routing Routing Layers Routing Layers 12

62 Auto Route All Routing All Failed to complete 0 connect 13

63 PCB Layout rules Tracks Restricted Area to mount screws These holes are usually used to secure the PCB to a casing or to secure it in a fixed place. Tracks should not be located on the areas that can caused them to be peeled off easily. 14

64 PCB Layout rules (Cont.) Conductor Thickness and Width PCB conductor thickness and width will determine the current carrying capacity of the track. Track Width for 1 oz cooper PCB and temperature rise solder To solder a thick cooper conductor on the PCB track to increase the current carrying capacity of the track. 15

65 PCB Layout rules (Cont.) Transmission Line Discontinuities Open Step Bend 90º Via Effect of Discontinuities 16

66 PCB Layout rules (Cont.) Reducing the Effects of Discontinuity Mitering of Step Chamfering of bend Connector Discontinuity Others Effect x x 1 17

67 Basic Grounding Line Neutral Ground VCC I/O to other hardware Ground Signal Ground 18

68 Single-Point Ground Series Ground Parallel Ground Series Ground System -Easy to implement. -Suffers from common-impedance coupling. Parallel Ground System -Less common-impedance coupling. -Mutual coupling (inductive and capacitive) between ground leads should be minimised. 19

69 Multi-point Ground Uses large ground plane as common ground conductor. Circuits that require ground connection are connected to the nearest available ground plane. Also suffer from common impedance coupling but it can be reduced by lowering the ground-impedance. Typically used in multilayer PCB. 20

70 Ground Scheme 1 Power Distribution and Ground on Same Layer Not Encouraged Good Practice The power and ground wires can be considered as a signal-ground combination. Therefore based on previous discussion on current return path, these must be near each other. 21

71 Ground Scheme 2 Using Ground Grid Reduce ground path impedance Allow shorter return path. 22

72 Ground Scheme 3 Using Ground Ring GND trace Using similar scheme for the power distribution, the VCC bus on another layer. Bear in mind to keep the traces as close as possible. 23

73 Ground Scheme 4 Using Ground Grid/Ring with Circuit Function Segmentation 24

74 Ground Plane To reduce common impedance coupling and promote return current to flow as near as source current, ground plane should be used wherever possible. Ground plane has much lower partial self inductance and resistance as compared to ground trace. Thus common impedance effect is vastly reduced. Source and return current near each other results in small loop area, this in turn reduces mutual inductance between different current loop. 25

75 Ground Scheme 5 Combination of Power Grid and Ground Plane for Hybrid System This is the best scheme as it allows return current to flow directly beneath the power lines. 26

76 Show them the way to home and the path can t cross. PCB layout 27

77 Interactive routing connection 28

78 Interactive routing connection (Cont) Ctrl + click Double click Ctrl + click 29

79 Net connection 30

80 Check broken 31

81 Place Component Double click 32

82 Top layer layout recommend Hard solder Easy solder 33

83 Add pad Place Pad 34

84 Bottom layer layout recommend Reduce top layer track Bottom Solder in bottom layer Top 35

85 Board Shape Sheet Select and move Board X:0mm Y:0mm 36

86 1 Move Board Shape Move Board Shape 2 3 Select and move 4 37

87 Redefine Board Shape 1 Redefine Board Shape

88 Top layer & Bottom layer 39

89 Homework All track must in bottom layer Area limits in 3 cm x 3 cm Upload the PCB image file 40

90 Schematic Library File New Schematic Library Save As Right click D:\My Library\Photoresistor.SchLib 1

91 Photoresistor.SchLib 2

92 Place Ellipse Rectangle Polygon 3

93 4 Place Pin VCC 40 VSS 20 EA/VP 31 XTAL1 19 XTAL2 18 RESET 9 P3.2(INT0) 12 P3.3(INT1) 13 P3.4(T0) 14 P3.5(T1) 15 P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 P0.0(AD0) 39 P0.1(AD1) 38 P0.2(AD2) 37 P0.3(AD3) 36 P0.4(AD4) 35 P0.5(AD5) 34 P0.6(AD6) 33 P0.7(AD7) 32 P2.0(A8) 21 P2.1(A9) 22 P2.2(A10) 23 P2.3(A11) 24 P2.4(A12) 25 P2.5(A13) 26 P2.6(A14) 27 P2.7(A15) 28 P3.7(RD) 17 P3.6(WR) 16 PSEN 29 ALE/P 30 P3.1(TXD) 11 P3.0(RXD) 10 U1 89C51-DIP JP5 Header 8 Connect to components

94 Photoresistor pin P 1 2 N 5

95 Photoresistor.SchLib 圖 要 畫 在 正 中 間 6

96 Schematic Library

97 Library Component Properties Photoresistor 8

98 Libraries 2 1 Open new file Sheet1.SchDoc 9

99 Available Libraries Installed Install

100 Select Photoresistor.SchLib

101 Select Photoresistor.SchLib Double click 12

102 Component Properties Add New Model

103 PCB Model Browse

104 PCB Model Name: AXIAL

105 Model for R1-Photoresistor 1 P N R1 2 16

106 PCB Library File New PCB Library Save As Right click D:\My Library\Photoresistor.PcbLib 1

107 Photoresistor.PcbLib 2 X:0mm Y:0mm Select Top Overlay 1 2

108 Place Pad Round Rectangle Octagonal Hole Size 1mm Size and Shape 2mm 3

109 Place Line Arc Top Overlay Top Layer Bottom Layer 元 件 的 外 觀 上 層 的 銅 線 下 層 的 銅 線 4

110 Photoresistor.PcbLib Designator setting 1 2 5

111 Photoresistor.SchLib & Photoresistor.PcbLib P 1 2 N 6

112 PCB Library Double click 4 6 Photoresistor 7

113 PCB Library (Cont.) 1 P N R1 2 8

114 Select Photoresistor.SchLib Double click 9

115 Component Properties Add New Model

116 PCB Model Browse

117 Available Libraries Installed Install

118 Browse Libraries PCB Model

119 Model for R1-Photoresistor 1 P N R1 2 14

120 Copy and Past 2 Schematic 3 PCB Schematic 4 Copy and Past Select Keep-Out Layer 1 15

121 Copy and Past (Cont.) 1 Edit Copy 2 Edit Past 16

122 Align at origin Lower left corner of the component must align at origin. X:0mm Y:0mm 17

123 1 Pin description Q? 2SA Q? 2SC Q? TIP

124 Pad and Via Pad 和 Via 最 大 的 不 同, 在 於 Via 沒 有 designator, 在 繪 製 零 件 Footprint 時, 無 法 成 為 Pin 腳 所 連 接 的 Pad 19

125 1 3 Transformer 某 些 零 件 Footprint 必 須 在 PCB 板 上 鑽 固 定 用 的 孔, 固 定 孔 並 無 與 Pin 腳 連 接, 此 時 固 定 孔 須 以 Via 表 示 20

126 Homework Track in both layer Area limits in 2 cm x 2 cm Upload the PCB image file Q1 Q2SC1840 RC1 1k D2 D1N4001 R2 2.2k C u RB2 47k RB1 47k C u R1 2.2k D1 D1N4001 RC2 1k V Q2 Q2SC1815 VCC 12Vdc 0 R1 200 R2 800 R3 470 Q1 Q2SC1840 RC1 1k C u RB2 47k RB1 47k C u RC2 1k V Q2 Q2SC1815 VCC 12Vdc 0 21

127 Output Photo file Top Layer Bottom Layer Mirror Top Overlay 1

128 Keep-Out Layer and Via Place Via Place Line in Keep-Out Layer 2

129 File Page Setup Scale Mode Advanced

130 PCB Printout Properties Double click Bottom Layer Keep Out Layer Top Overlay Top Layer 4

131 Printout Properties Top Layer Keep Out Layer 5

132 Printout Properties (Cont.) Top Layer Keep Out Layer 6

133 PCB Printout Properties 7

134 Print Top Layer File Print Preview Print

135 Print Bottom Layer File Page Setup Scale Mode Advanced

136 PCB Printout Properties Bottom Layer Keep Out Layer 10

137 Print Bottom Layer File Print Preview Print

138 Print Top overlay File Page Setup Scale Mode Advanced

139 PCB Printout Properties Top Overlay Top Solder Keep Out Layer 13

140 Print Top overlay File Print Preview Print

141 PCB fabrication Top overlay Fix top layer with components Designator Q1 Q2 Board BOM LibRef P2N2222A P2N2222A Value R1 R2 R3 R4 C1 C2 JP1 Res1 Res1 Res1 Res1 Cap Pol2 Cap Pol2 Header 4 1K 47K 47K 1K 0.022uF 0.022uF J1 COAX-F 15