A Novel Architecture for the Computation of 2D-DWT and its Implementation on Virtex-II Pro FPGA

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1 A Novel Architecture for the Computation of 2DDWT and its Implementation on VirtexII Pro FPGA Mrs. Kaleem Fatima S. Vijay Gopal N. Zeeshan Nadeem Associate Professor Programmer Analyst Trainee Master of Science in Engineering ECE Dept, MJCET Cognizant Technology Solutions Arizona State University Hyderabad, India Chennai, India. Tempe, Arizona, USA. Abstract This paper proposes a new approach for the design of hardware architecture for the computation of 2DDWT for an 8 x 8 image. The key feature of this design is to directly apply 2DDWT on alternate pixels of an image, called as the NonSeparable method, and implement it on an FPGA. The resulting design was implemented using only 6 adders and 10 multipliers, thus optimizing the number of multipliers and adders required for the computation of 2DDWT. Thus our approach provides a cost effective solution as compared to the conventional 2D nonseparable methods without compromising on speed performance. The design is implemented on Xilinx Virtex II Pro FPGA development kit and synthesized using Xilinx XST (VHDL/Verilog) synthesis tool. Key terms: 2DDWT, Signal Processing, VLSI, FPGA, filter coefficients, IDWT. 1. Introduction. The unique timefrequency localization properties of wavelet transforms have allowed them to be successfully used for the multiresolution representation of one dimensional and multidimensional signal. The new image compression standards such as MPEG4 VTC[1] and JPEG 2000[2] use the wavelet transform. In addition to data compression, wavelet transforms have been used in many different areas, such as data analysis, numerical analysis, signal processing and image processing[3,4]. The DWT has been introduced as a highly efficient and flexible method for Subband decomposition [5] of signals. This led to intensive research efforts for improving the implementation aspects of the transform. Many VLSI architectures for 1DDWT have been proposed and implemented [67]. Although 2DDWT can be a direct extension of 1D DWT, the development of a design specifically for the 2DDWT can provide an efficient architecture with a low hardware cost and high throughput. A considerable effort is being made to implement the 2DDWT for an n x n image using special purpose hardware for faster processing. In this paper we have made an effort to design & implement hardware architecture for the computation of 2DDWT using NonSeparable method on a Virtex II Pro FPGA using the device 2vp100ff For the purpose we have considered an 8 x 8 image in grayscale. Conventionally the 2DDWT can be realized by application of 1DDWT alternatively on rows and columns. This is the called the Separable method. In contrast, the NonSeparable method allows the 2Ddata to be processed directly and is the best adapted to a hardware implementation and has better timing performance. The proposed architecture has relatively simple hardware to compute DWT at all the resolution levels. It is modular and scalable in its totality. The rest of the paper is organized as follows: A brief review of the 2DDWT is given in Section 2. Section 3.1 presents the proposed algorithm. The architecture for 2DDWT and the description is given in 3.2. Finally, Section 4 gives the simulation results and the future scope for the work. 2. Review of 2DDWT. The 2DDWT has received considerable attention in the field of image processing because of its flexibility in representing nonstationary image signals and its ability in adapting to human visual characteristics. This transform method was developed by Mallat [8] and offers orthogonality and leads to a multigrid representation. The onelevel 2DDWT computation is shown in Figure1. Two filters are used, one low pass filter (h (n)) and one high pass filter (g (n)). As the input signal is an image, the filtering is obtained by first filtering the signal vertically then refiltering the output horizontally by the same set of filters. This leads to 4 different subbands HH, HL, LH and LL obtained by a

2 combination of High and Low filtering at each level. Then LL is filtered again to get the next level of representation. Figure 3 Figure 1 In contrast to the above Separable filters approach, the NonSeparable filters approach directly decomposes an image into four resultant subimages without column and row DWTs. Figure 2 illustrates the architecture of a nonseparable 2DDWT with oneresolution levels. Note that each block in this architecture is a 2D filter downsampled by Proposed algorithm for implementation of 2DDWT. The LL, HL, LH, HH coefficients (which are represented by CC, DC, CD, DD respectively in our work) of a level k are obtained from the LL (approximation) coefficients of level k1 using lowpass and highpass filter coefficients. The relation between the highpass (g(n)) and low pass filter (h(n)) coefficients is given by g(n)=(1) n h(n1n) (3.1) The following is the block diagram for obtaining the 2DDWT coefficients using filterbank approach. Figure 2 In Figure 3, LL, the upper left quadrant consists of all the coefficients, which are filtered by the analysis lowpass filter h along the rows and then filtered along the corresponding columns with the analysis lowpass filter h again. It represents the approximated version of the original at half the resolution. HL/ LH: The lower left and the upper right blocks were filtered along the rows and columns with h and g alternatively. The LH block contains vertical edges, mostly. In contrast, the HL block shows horizontal edges very clearly. HH: The lower right quadrant was derived analogously to the upper left quadrant but with the use of analysis highpass filter g that belongs to the given wavelet. We can interpret this block as the area, where we find edges of the original image in the diagonal direction. The 2DDWT can be applied to the coarser version at half the resolution, recursively in order to further decorrelate neighboring pixels of the input image. Figure 4 For a fourtap filter we have the following relationships between g and h. g (0) = h (3). g (1) = h (2). g (2) = h (1). g (3) = h(0). (3.2)

3 The LL, HL, LH, HH coefficients in terms of lowpass filter coefficients (using the above equation) are as given below. If a ij represents the pixel of i th row and j th column of an n x n image then the 1DDWT coefficients can be expressed as C ij =a ij h 0 + a ij1 h 1 + a ij2 h 2 + a ij3 h 3 (3.3) D ij =a ij g 0 + a ij1 g 1 + a ij2 g 2 + a ij3 g 3 (3.4) Using the equation (3.2) and rewriting D ij interms of h 0, h 1,h 2, h 3 we have, 3.2 Proposed Architecture. The proposed VLSI architecture, shown in Figure 6, is very regular, can be easily extended for larger size images. For the purpose of hardware realization, we have considered an image of size 8 x 8, which has 8 rows and 8 columns, of 8 pixels. Down sampling is achieved by applying 2DDWT on those pixels that belong to even rows & even columns (refer to Figure 5). This is based on the assumption that adjacent pixels will not have much information change like in the image of sky; pixels corresponding to clouds will be similar. D ij =a ij h 3 a ij1 h 2 + a ij2 h 1 a ij3 h 0 (3.5) where C ij and D ij represents approximation and detail coefficients of 1DDWT in terms of filter coefficients. To obtain approximation coefficients of 2DDWT i.e., CC, the input is passed through lowpass filter twice. This is obtained by passing C ij again through lowpass filters. C ij = C ij h 0 + C ij1 h 1 + C ij2 h 2 + C ij3 h 3 (3.6) Substituting equation (3.3) in above and rearranging we get the final design equations as, CC ij = a ij h a i1j1 h a i2j2 h a i3j3 h [a ij1 + a i1j ] h 0 h 1 + [a ij2 + a i2j ] h 0 h 2 + [a ij3 + a i3j ] h 0 h 3 + [a i2j1 + a i1j2 ] h 1 h 2 + [a i1j3 + a i3j1 ] h 1 h 3 + [a i2j3 + a i3j2 ] h 2 h 3 (3.7) Figure 5 The architecture consists of the following modules, which are interconnected to compute the 2DDWT coefficients for the given image. CD ij = a i3j h a i2j1 h 1 a i1j2 h a ij3 h [a ij a i2j3 ] h 0 h 3 [a i3j2 + a i1j ] h 0 h 2 + [a i2j a i3j1 ] h 0 h 1 + [a ij1 + a i2j3 ] h 1 h 3 + [a i2j2 a i1j1 ] h 1 h 2 + [a ij2 a i1j3 ] h 2 h 3 (3.8) DC ij = a ij3 h a i1j2 h 2 1 a i2j1 h a i3j h [a ij a i3j3 ] h 0 h 3 [a ij1 + a i2j3 ] h 0 h 2 + [a ij2 a i3j3 ] h 0 h 1 + [a i 1j + a i3j2 ] h 1 h 3 + [a i2j2 a i1j1 ] h 1 h 2 + [a i2j a i3j1 ] h 2 h 3 (3.9) ιξ = α ι3ξ3 η α ι2ξ2 η α ι1ξ1 η α ιξ η 3 2 [α ι3ξ + α ιξ3 ] η 0 η 3 + [α ι3ξ1 + α ι1ξ3 ] η 0 η 2 [α ι3ξ2 + α ι2ξ3 ] η 0 η 1 [α ι2ξ1 + α ι1ξ2 ] η 1 η 2 + [α ι2ξ + α ιξ2 ] η 1 η 3 [α ι1ξ + α ιξ1 ] η 2 η 3 (3.10) Figure 6 Each pixel is represented as an 8bit binary gray value. The pixel (i,j) of the image, indicates the one, belonging to the i th row and j th column. The architecture has an input buffer memory of size 64 x 8 to store the digital values of an image of size 8 x 8. From the design equations (3.7) to (3.10) it can be seen that to compute 2DDWT of the present pixel, a 4 x 4 matrix comprising of previous 4 rows and 4 columns including that of the present pixel is needed as shown in shaded part of Figure 5 with the present pixel at the rightmost corner (circled in Figure 5).The mat_sel

4 block of figure 6 will select these required 16 pixels serially and routes them to the matrix block through an 8bit wide, 1:4 Demux. The 4 x 4 matrix for present pixel say (5,5) (circled in figure 5) is shown in Figure 7. Figure 9 Figure 7 The design equations (3.7) to (3.10), have sum of 16 product terms, where each term is a product of pixel value and its corresponding filter coefficient, which gives the output DWT coefficients. It is seen that, few pixels in each equation have a common multiplier. For example in equation (3.7) a i1j & a ij1 are to be multiplied with the same coefficient h 0 h 1. Hence the pixels having common multiplier are added in adder block, which consists of 6 synchronized adders in it as shown in Figure 8. The same cycle can be repeated for computing other output DWT coefficients (CD, DC & DD) by modifying the inputs to adder block & multiplier block according to design equations (3.8) to (3.10). The required modifications are done by appropriate port mapping in VHDL code. The computed coefficient will be then routed to control logic block, which logically places the coefficient in the corresponding memory location of the output coefficient buffer (CC, CD, DC, DD) as shown in Figure 10. Continuing the process, the ij_decoder block suitably increments i and j to choose the next pixel to be operated upon. Figure 8 The 4 diagonal elements (2,2), (3,3), (4,4), (5,5) of "matrix"(in figure 7) and the 6 output terms (S1, S2... S6) from adder block are multiplied by the corresponding filter coefficients (stored in 8bit buffers) in multiplier block with 10 synchronized multipliers as shown in Figure 9. Hence instead of using 16 multipliers, we are using only 10 multipliers & 6 adders, reducing the overall hardware complexity. The Reg_10w block (PISO register) will store the 10 output terms (p1, p2,...p10) of multiplier block, which when added in add and accumulate fashion by the adder, will give the output DWT coefficient Simulation Results. Figure 10 The VHDL code is written for all the blocks of the architecture. The individual blocks are simulated both in Active VHDL & ISE Simulator. All the individual modules are portmapped in a toplevel module called as DWT_Struct and simulated. The synthesis is performed on Xilinx ISE 8.1i using XST (VHDL/Verilog) synthesis tool on VirtexII Pro using device 2vp100ff16966 on a global clock of 24 Mhz. The device utilization summary of the proposed architecture for an 8x 8 image is shown below.

5 Component IP_Buffer Mat_Sel Matrix Adder Block Multiplier Block Reg_10W Adder Output_Mat Slices TABLE 1 Slice FFs IP LUTs IOBs 19 8 Delay (ns) Total VirtexII Pro Conclusion. This paper has explored the feasibility of implementing a nonseparable, parallel 2DDWT architecture on an FPGA. The proposed architecture provides a methodology to reduce the number of adders and multipliers required for the computation of 2DDWT and thus minimizing the hardware requirements. The design is modular and scalable in its totality. The initial results are promising enough for the use of FPGAs in online computation of 2DDWT for real time images. Work is underway for the implementation of Inverse DWT (IDWT). The future work involves hardware implementation of 2DDWT on larger size images and further optimising the hardware requirements. Percentage Utilization 4.07% 1.44% 2.61% 2.3% References. Figure11 shows the technology schematic of 8bit multiplier block (using VirtexII Pro 100 synthesis tool). Figure 11 Thus it can be estimated that, the 2DDWT for an image size of 64 x 64 can be housed in a single FPGA VirtexII Pro 100 as shown below. TABLE 2 Image Size Slices Slice FFs 4 IP LUTs IOBs 8X Delay (ns) [1] BingFei Wu, ChungFU Lin, "A resheduling and fast pipeline VLSI architecture for liftingbased", The 2003 IEEE International Symposium on Circuits and Systems, Vol.2, (2003) [2] D. SantaCruz and T. Ebrahimi, A study of JPEG 2000 still image coding versus other standards, Proc. of the X European Signal Processing Conference (EUSIPCO), Tampere, Finland, pages , [3] M. Marcellin, M. Gormish, A. Bilgin, and M. Boliek, An Overview of JPEG2000, Proc. Data Compression Conference, J.A. Storer and M. Cohn, eds., Snowbird, Utah, p , Mar.28Mar.30, [4] P.M. Lam, C.S. Leung, and T.T. Wong, A compression method for a massive image data set in the imagebased rendering application, Signal Processing: Image Communication, vol. 19, no. 8, pp , September [5] T.T. Wong and C.S. Leung, Compression of illuminationadjustable images, IEEE Transactions on Circuits and Systems for Video Technology (special issue on Imagebased Modeling, Rendering and Animation), vol. 13, no. 11, pp , November [6] S. Mallat, A Wavelet Tour of Signal Processing, second ed., Academic Press, New York, [7] C. Chakrabarti, M. Vishwanath, Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to SIMD parallel computers, IEEE Trans. Signal Process. 43 (3) (1995) [8] M. Vishwanath, R.M. Owens, M.J. Irwin, VLSI architectures for the discrete wavelet transform, IEEE Trans.Circuits Syst. II 42 (5) (1995). 1. Digital Image Processing by Gonzalez & Woods. 2. Wavelet Transforms, Introduction to Theory and Applications by Raghuveer M.Rao, Ajit S.Bopardikar 3. Xilinx Data Sheets at 64X µs