IRI Frankfurt. Norbert Abel, Christian Stüllein, Udo Kebschull. Partitions and Partial Reconfiguration
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1 IRI Frankfurt Norbert Abel, Christian Stüllein, Udo Kebschull Partitions and Partial Reconfiguration
2 History ISE 1 ISE 2 ISE 3 ISE 4 ISE 5 No PR at all ISE 6 ISE 7 ISE 8 ISE 9 PREA patch ISE 10 ISE 11 New approach based on Partitions & official support ISE 12 ISE 13 Page 2
3 Motivation Black, Donovan, Bunton, Keist SystemC: From the Ground Up Page 3
4 Motivation High Level Synthesis Team Design Hierarchical Design & Re-Use Page 4
5 Partitions Partitions are Xilinx's approach to Team Design and Hierarchical Design Tool: PlanAhead Page 5
6 RTL Project Page 6
7 RTL Project Page 7
8 RTL Project clkbufds: ibufgds port map (O=>clk, I=>clk_p, IB=>clk_n); team1_inst: team1 port map (clk=>clk, led=>led1); team2_inst: team2 port map (clk=>clk, led=>led2); Page 8
9 RTL Project process (clk) begin if rising_edge(clk) then c <= c + 1; end if; end process; led(3 downto 0) <= c (31 downto 28); Page 9
10 RTL Project process (clk) begin if rising_edge(clk) then c(31 downto 0) <= c(30 downto 0) & c(31); end if; end process; led(3 downto 0) <= c (31 downto 28); Page 10
11 RTL Project Page 11
12 RTL Project Page 12
13 RTL Project Page 13
14 RTL Project Page 14
15 RTL Project Page 15
16 RTL Project Page 16
17 RTL Project Page 17
18 RTL Project Page 18
19 RTL Project 3 Levels of Design Preservation: Synthesis Placement Routing Page 19
20 NGC Project Page 20
21 NGC Project Differences to the RTL Project: Sources: NGC files (netlists) ==> Requires external synthesis Instantiates team1 and team2 as black box top.ngc team1.ngc team2.ngc general Synthesis hints: - deactivate automatically generated I/O buffers - instantiate all I/O buffers directly Page 21
22 NGC Project Differences to the RTL Project: 3 Levels of Design Preservation: Synthesis (same as Implement) Placement Routing Page 22
23 Partial Reconfiguration Requires a special PR-License No patches needed any longer! Page 23
24 Partial Reconfiguration PR designs are NGC designs Sources: NGC files (netlists) ==> Requires external synthesis Instantiates subcomponents as black boxes top.ngc staticmodule.ngc recomodule1.ngc general Synthesis hints: - deactivate automatically generated I/O buffers - instantiate all I/O buffers directly recomodule2.ngc no BUFGs, PLLs, DCMs, etc. allowed Page 24
25 Partial Reconfiguration Page 25
26 Partial Reconfiguration Page 26
27 Partial Reconfiguration Page 27
28 Partial Reconfiguration Page 28
29 Partial Reconfiguration Page 29
30 Partial Reconfiguration Page 30
31 Partial Reconfiguration Page 31
32 Partial Reconfiguration Page 32
33 Partial Reconfiguration Page 33
34 Partial Reconfiguration Page 34
35 Partial Reconfiguration Page 35
36 Partial Reconfiguration Page 36
37 Partial Reconfiguration Page 37
38 Partial Reconfiguration Page 38
39 Partial Reconfiguration! Page 39
40 Partial Reconfiguration recomodule1 proxy logic (LUT1) staticmodule recomodule2 FPGA Page 40
41 Partial Reconfiguration Page 41
42 Partial Reconfiguration Page 42
43 Conclusion recomodule1 proxy logic (LUT1) staticmodule Problems: Timing change of static Module causes rebuild of all Modules a Areas using m Modules => m configurations => m full implementation runs => m full bitfiles => a m partial bitfiles no support of Spartan-6 recomodule2 FPGA Our aims: clear Timing strict module separation movable bitfiles Page 43
44 Questions? Page 44
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