CMOS 12-Bit Monolithic Multiplying DAC AD7541A

Transcription

1 a FEATUES Improved Version of AD754 Full Four-Quadrant Multiplication 2-Bit Linearity (Endpoint) All Parts Guaranteed Monotonic TTL/CMOS Compatible Low Cost Protection Schottky Diodes Not equired Low Logic Input Leakage GENEAL DESCIPTION The Analog Devices AD754A is a low cost, high performance 2-bit monolithic multiplying digital-to-analog converter. It is fabricated using advanced, low noise, thin film on CMOS technology and is available in a standard 8-lead DIP and in 20-terminal surface mount packages. The AD754A is functionally and pin compatible with the industry standard AD754 device and offers improved specifications and performance. The improved design ensures that the device is latch-up free so no output protection Schottky diodes are required. This new device uses laser wafer trimming to provide full 2-bit endpoint linearity with several new high performance grades. ODEING GUIDE elative Gain Temperature Accuracy Error Package Model 2 ange T MIN to T MAX T A = +25 C Options AD754AJN 0 C to +70 C ± LSB ±6 LSB N-8 AD754AKN 0 C to +70 C ±/2 LSB ± LSB N-8 AD754AJP 0 C to +70 C ± LSB ±6 P-20A AD754AKP 0 C to +70 C ±/2 LSB ± P-20A AD754AK 0 C to +70 C ±/2 LSB ± -8 AD754AAQ 25 C to +85 C ± LSB ±6 LSB Q-8 AD754ABQ 25 C to +85 C ±/2 LSB ± LSB Q-8 AD754ASQ 55 C to +25 C ± LSB ±6 LSB Q-8 AD754ATQ 55 C to +25 C ±/2 LSB ± LSB Q-8 AD754ASE 55 C to +25 C ± LSB ±6 LSB E-20A AD754ATE 55 C to +25 C ±/2 LSB ± LSB E-20A NOTES Analog Devices reserves the right to ship either ceramic (D-8) or cerdip (Q-8) hermetic packages. 2 To order MIL-STD-88, Class B process parts, add /88B to part number. Contact local sales office for military data sheet. E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; = Small Outline IC. CMOS 2-Bit Monolithic Multiplying DAC AD754A FUNCTIONAL BLOCK DIAGAM 0kΩ 0kΩ 0kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ S S2 S S2 0kΩ BIT (MSB) BIT 2 BIT BIT 2 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) LOGIC: A SWITCH IS CLOSED TO I OUT FO ITS DIGITAL INPUT IN A "HIGH" STATE. OUT FEEDBACK PODUCT HIGHLIGHTS Compatibility: The AD754A can be used as a direct replacement for any AD754-type device. As with the Analog Devices AD754, the digital inputs are TTL/CMOS compatible and have been designed to have a ± µa maximum input current requirement so as not to load the driving circuitry. Improvements: The AD754A offers the following improved specifications over the AD754:. Gain Error for all grades has been reduced with premium grade versions having a maximum gain error of ± LSB. 2. Gain Error temperature coefficient has been reduced to 2 ppm/ C typical and 5 ppm/ C maximum.. Digital-to-analog charge injection energy for this new device is typically 20% less than the standard AD754 part. 4. Latch-up proof. 5. Improvements in laser wafer trimming provides /2 LSB max differential nonlinearity for top grade devices over the operating temperature range (vs. LSB on older 754 types). 6. All grades are guaranteed monotonic to 2 bits over the operating temperature range. EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: 67/ World Wide Web Site: Fax: 67/ Analog Devices, Inc., 997

2 AD754A SPECIFICATIONS ( = +5 V, = +0 V; OUT = OUT 2 = GND = 0 V unless otherwise noted) T A = T A = Parameter Version +25 C T MIN, T MAX Units Test Conditions/Comments ACCUACY esolution All 2 2 Bits elative Accuracy J, A, S ± ± LSB max ± LSB = ±0.024% of Full Scale K, B, T ± /2 ± /2 LSB max ± /2 LSB = ± 0.02% of Full Scale Differential Nonlinearity J, A, S ± ± LSB max All Grades Guaranteed Monotonic K, B, T ± /2 ± /2 LSB max to 2 Bits, T MIN to T MAX. Gain Error J, A, S ± 6 ± 8 LSB max Measured Using Internal FB and Includes K, B, T ± ± 5 LSB max Effect of Leakage Current and Gain TC. Gain Error Can Be Trimmed to Zero. Gain Temperature Coefficient 2 Gain/ Temperature All 5 5 ppm/ C max Typical Value Is 2 ppm/ C. Output Leakage Current OUT (Pin ) J, K ± 5 ± 0 na max All Digital Inputs = 0 V. A, B ± 5 ± 0 na max S, T ± 5 ± 200 na max (Pin 2) J, K ± 5 ± 0 na max All Digital Inputs =. A, B ± 5 ± 0 na max S, T ± 5 ± 200 na max EFEENCE INPUT Input esistance (Pin 7 to GND) All kω min/max Typical Input esistance = kω. Typical Input esistance Temperature Coefficient = 00 ppm/ C. DIGITAL INPUTS V IH (Input HIGH Voltage) All V min V IL (Input LOW Voltage) All V max I IN (Input Current) All ± ± µa max Logic Inputs Are MOS Gates. I IN typ (25 C) = na. C IN (Input Capacitance) 2 All 8 8 pf max V IN = 0 V POWE SUPPLY EJECTION Gain/ All ± 0.0 ± 0.02 % per % max = ± 5% POWE SUPPLY ange All +5 to to +6 V min/v max Accuracy Is Not Guaranteed Over This ange. I DD All 2 2 ma max All Digital Inputs V IL or V IH µa max All Digital Inputs 0 V or. AC PEFOMANCE CHAACTEISTICS These Characteristics are included for Design Guidance only and are not subject to test. = +5 V, V IN = +0 V except where noted, OUT = 0UT2 = GND = 0 V, Output Amp is AD544 except where noted. T A = T A = Parameter Version +25 C T MIN, T MAX Units Test Conditions/Comments POPAGATION DELAY (From Digital Input OUT Load = 00 Ω, C EXT = pf. Change to 90% of Final Analog Output) All 00 ns typ Digital Inputs = 0 V to or to 0 V. DIGITAL TO ANALOG GLITCH = 0 V. All digital inputs 0 V to or IMPULSE to 0 V. All 000 nv-sec typ Measured using Model 50K as output amplifier. MULTIPLYING FEEDTHOUGH EO ( to OUT) All.0 mv p-p typ = ± 0 V, 0 khz sine wave. OUTPUT CUENT SETTLING TIME All 0.6 µs typ To 0.0% of full-scale range. OUT Load = 00 Ω, C EXT = pf. Digital Inputs = 0 V to or to 0 V. OUTPUT CAPACITANCE C OUT (Pin ) All pf max Digital Inputs C (Pin 2) All pf max = V IH C OUT (Pin ) All pf max Digital Inputs C (Pin 2) All pf max = V IL NOTES Temperature range as follows: J, K versions, 0 C to +70 C; A, B versions, 25 C to +85 C; S, T versions, 55 C to +25 C. 2 Guaranteed by design but not production tested. To minimize feedthrough in the ceramic package (Suffix D) the user must ground the metal lid. Specifications subject to change without notice. 2 EV. B

3 AD754A ABSOLUTE MAXIMUM ATINGS* (T A = +25 C unless otherwise noted) to GND V to GND ± 25 V V FB to GND ± 25 V Digital Input Voltage to GND V, + 0. V OUT, OUT 2 to GND V, + 0. V Power Dissipation (Any Package) To +75 C mw Derates above +75 C mw/ C Operating Temperature ange Commercial (J, K Versions) C to +70 C Industrial (A, B Versions) C to +85 C Extended (S, T Versions) C to +25 C Storage Temperature C to +50 C Lead Temperature (Soldering, 0 secs) C *Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD754A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WANING! ESD SENSITIVE DEVICE TEMINOLOGY ELATIVE ACCUACY elative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is expressed in % of fullscale range or (sub)multiples of LSB. DIFFEENTIAL NONLINEAITY Differential nonlinearity is the difference between the measured change and the ideal l LSB change between any two adjacent codes. A specified differential nonlinearity of ± LSB max over the operating temperature range insures monotonicity. GAIN EO Gain error is a measure of the output error between an ideal DAC and the actual device output. For the AD754A, ideal maximum output is 4095 (V EF ). Gain error is adjustable to zero using external trims as shown in Figures 4, 5 and 6. OUTPUT LEAKAGE CUENT Current which appears at OUTI with the DAC loaded to all 0s or at with the DAC loaded to all s. MULTIPLYING FEEDTHOUGH EO AC error due to capacitive feedthrough from terminal to OUT with DAC loaded to all 0s. OUTPUT CUENT SETTLING TIME Time required for the output function of the DAC to settle to within /2 LSB for a given digital input stimulus, i.e., 0 to full scale. POPAGATION DELAY This is a measure of the internal delay of the circuit and is measured from the time a digital input changes to the point at which the analog output at OUT reaches 90% of its final value. DIGITAL-TO-ANALOG CHAGE INJECTION (QDA) This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the glitch in nv secs and is measured with = GND and a Model 50K as the output op amp, C (phase compensation) = 0 pf. PIN CONFIGUATIONS DIP/SOIC LCCC PLCC OUT FEEDBACK IN OUT 2 OUT NC FB OUT 2 OUT NC FB GND 6 (+) BIT (MSB) 4 AD754A 5 BIT 2 (LSB) BIT 2 5 TOP VIEW (Not to Scale) 4 BIT BIT BIT 4 BIT BIT 0 BIT 9 BIT 8 BIT BIT 7 GND 4 BIT (MSB) 5 BIT 2 6 BIT 7 BIT 4 8 NC = NO CONNECT TOP VIEW (Not to Scale) BIT 5 BIT 6 AD754A NC BIT 7 BIT BIT 2 (LSB) 6 BIT 5 BIT 0 4 BIT 9 GND 4 BIT (MSB) 5 BIT 2 6 BIT 7 BIT 4 8 NC = NO CONNECT PIN IDENTIFIE AD754A TOP VIEW (Not to Scale) BIT 5 BIT 6 NC BIT 7 BIT BIT 2 (LSB) BIT BIT 0 BIT 9 EV. B

4 AD754A GENEAL CICUIT INFOMATION The simplified D/A circuit is shown in Figure. An inverted -2 ladder structure is used that is, the binarily weighted currents are switched between the OUT and bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. 0kΩ 0kΩ 0kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ S S2 S S2 0kΩ BIT (MSB) BIT 2 BIT BIT 2 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) LOGIC: A SWITCH IS CLOSED TO I OUT FO ITS DIGITAL INPUT IN A "HIGH" STATE. OUT Figure. Functional Diagram (Inputs HIGH) FEEDBACK The input resistance at (Figure ) is always equal to LD ( LD is the /2 ladder characteristic resistance and is equal to value ). Since IN at the pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature coefficient external FB is recommended to define scale factor.) EQUIVALENT CICUIT ANALYSIS The equivalent circuits for all digital inputs LOW and all digital inputs HIGH are shown in Figures 2 and. In Figure 2 with all digital inputs LOW, the reference current is switched to. The current source I LEAKAGE is composed of surface and junction leakages to the substrate, while the I/ 4096 current source represents a constant -bit current drain through the termination resistor on the -2 ladder. The ON capacitance of the output N-channel switch is 200 pf, as shown on the terminal. The OFF switch capacitance is 70 pf, as shown on the OUT terminal. Analysis of the circuit for all digital inputs HIGH, as shown in Figure is similar to Figure 2; however, the ON switches are now on terminal OUT, hence the 200 pf at that terminal. 5kΩ I EF I /4096 I LEAKAGE I LEAKAGE 70pF 200pF FB OUT Figure 2. DAC Equivalent Circuit All Digital Inputs LOW 5kΩ IEF I /4096 I LEAKAGE I LEAKAGE 200pF 70pF FB OUT Figure. DAC Equivalent Circuit All Digital Inputs HIGH APPLICATIONS UNIPOLA BINAY OPEATION (2-QUADANT MULTIPLICATION) Figure 4 shows the analog circuit connections required for unipolar binary (2-quadrant multiplication) operation. With a dc reference voltage or current (positive or negative polarity) applied at Pin 7, the circuit is a unipolar D/A converter. With an ac reference voltage or current, the circuit provides 2-quadrant multiplication (digitally controlled attenuation). The input/ output relationship is shown in Table II. provides full-scale trim capability [i.e., load the DAC register to, adjust for V OUT = (4095/4096)]. Alternatively, Full Scale can be adjusted by omitting and 2 and trimming the reference voltage magnitude. C phase compensation (0 pf to 25 pf) may be required for stability when using high speed amplifiers. (C is used to cancel the pole formed by the DAC internal feedback resistance and output capacitance at OUT). Amplifier A should be selected or trimmed to provide V OS 0% of the voltage resolution at V OUT. Additionally, the amplifier should exhibit a bias current which is low over the temperature range of interest (bias current causes output offset at V OUT equal to I B times the DAC feedback resistance, nominally kω). The AD544L is a high speed implanted FET input op amp with low factory-trimmed V OS. V IN * 6 8 FB OUT 7 AD754A PINS 4 5 DGND BIT BIT 2 2* 2 DIGITAL GOUND C pf ANALOG COMMON AD544L (SEE TEXT) *EFE TO TABLE Figure 4. Unipolar Binary Operation V OUT Table I. ecommended Trim esistor Values vs. Grades Trim esistor JN/AQ/SD KN/BQ/TD 00 Ω 00 Ω 2 47 Ω Ω Table II. Unipolar Binary Code Table for Circuit of Figure 4 Binary Number in DAC MSB LSB Analog Output, V OUT 4095 V IN V IN = /2 V IN V IN Volts 4 EV. B

5 AD754A BIPOLA OPEATION (4-QUADANT MULTIPLICATION) Figure 5 and Table III illustrate the circuitry and code relationship for bipolar operation. With a dc reference (positive or negative polarity) the circuit provides offset binary operation. With an ac reference the circuit provides full 4-quadrant multiplication. With the DAC loaded to , adjust for V OUT = 0 V (alternatively, one can omit and 2 and adjust the ratio of to 4 for V OUT = 0 V). Full-scale trimming can be accomplished by adjusting the amplitude of or by varying the value of 5. As in unipolar operation, A must be chosen for low V OS and low I B., 4 and 5 must be selected for matching and tracking. Mismatch of 2 to 4 causes both offset and full-scale error. Mismatch of 5 to 4 or 2 causes full-scale error. C phase compensation (0 pf to 50 pf) may be required for stability, depending on amplifier used. V IN 2* 6 8 FB OUT 7 * AD754A 2 GND PINS 4 5 BIT BIT 2 DIGITAL GOUND C pf ANALOG COMMON A AD544L 0kΩ 6 5kΩ 0% 4 20kΩ A2 5 20kΩ AD544J *FO VALUES OF AND 2 SEE TABLE. Figure 5. Bipolar Operation (4-Quadrant Multiplication) Table III. Bipolar Code Table for Offset Binary Circuit of Figure 5 Binary Number in DAC MSB LSB Analog Output, V OUT V IN 2048 V OUT Figure 6 and Table IV show an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage of giving 2-bit resolution in each quadrant, compared with -bit resolution per quadrant for the circuit of Figure 5. The AD7592 is a fully protected CMOS changeover switch with data latches. 4 and 5 should match each other to 0.0% to maintain the accuracy of the D/A converter. Mismatch between 4 and 5 introduces a gain error. V IN 6 8 FB 2* OUT 7 * AD754A 2 GND PINS 4 5 BIT BIT 2 SIGN BIT DIGITAL GOUND C pf A AD544L ANALOG COMMON 4 20kΩ 0kΩ 0% /2 AD7592JN 5 20kΩ A2 *FO VALUES OF AND 2 SEE TABLE. AD544J Figure 6. 2-Bit Plus Sign Magnitude Operation Table IV. 2-Bit Plus Sign Magnitude Code Table for Circuit of Figure 6 Sign Binary Number in DAC Bit MSB LSB Analog Output, V OUT V IN Volts Volts 4095 V IN Note: Sign bit of 0 connects to GND. V OUT V IN Volts 0 V IN V IN 2048 EV. B 5

6 AD754A APPLICATIONS HINTS Output Offset: CMOS D/A converters exhibit a code-dependent output resistance which in turn can cause a code-dependent error voltage at the output of the amplifier. The maximum amplitude of this offset, which adds to the D/A converter nonlinearity, is 0.67 V OS where V OS is the amplifier input offset voltage. To maintain monotonic operation it is recommended that V OS be no greater than ( ) ( ) over the temperature range of operation. Suitable op amps are AD57L and AD544L. The AD57L is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (50 µv) and in most applications will not require an offset trim. The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD544L may be necessary in some circuits. Digital Glitches: One cause of digital glitches is capacitive coupling from the digital lines to the OUT and terminals. This should be minimized by screening the analog pins of the AD754A (Pins, 2, 7, 8) from the digital pins by a ground track run between Pins 2 and and between Pins 6 and 7 of the AD754A. Note how the analog pins are at one end of the package and separated from the digital pins by and GND to aid screening at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digital-to-analog sections of the AD754A, particularly in circuits with high currents and fast rise and fall times. Temperature Coefficients: The gain temperature coefficient of the AD754A has a maximum value of 5 ppm/ C and a typical value of 2 ppm/ C. This corresponds to worst case gain shifts of 2 LSBs and 0.8 LSBs, respectively, over a 00 C temperature range. When trim resistors and 2 are used to adjust fullscale range, the temperature coefficient of and 2 should also be taken into account. The reader is referred to Analog Devices Application Note Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs, Publication Number E60c-5-/86. SINGLE SUPPLY OPEATION Figure 7 shows the AD754A connected in a voltage switching mode. OUT is connected to the reference voltage and is connected to GND. The D/A converter output voltage is available at the pin (Pin 7) and has a constant output impedance equal to LD. The feedback resistor FB is not used in this circuit. +2.5V NOT USED 8 6 FB V CA40B DD OUT VEF AD754A 7 2 GND PINS kΩ BIT BIT 2 2 0kΩ V OUT ± D ( +2/) WHEE 0 D i.e., D IS A FACTIONAL EPESENTATION OF THE DIGITAL INPUT V+ V = +5V V OUT = 0V TO +0V SYSTEM GOUND Figure 7. Single Supply Operation Using Voltage Switching Mode The reference voltage must always be positive. If OUT goes more than 0. V less than GND, an internal diode will be turned on and a heavy current may flow causing device damage (the AD754A is, however, protected from the SC latch-up phenomenon prevalent in many CMOS devices). Suitable references include the AD580 and AD584. The loading on the reference voltage source is code-dependent and the response time of the circuit is often determined by the behavior of the reference voltage with changing load conditions. To maintain linearity, the voltage at OUT should remain within 2.5 V of GND, for a of 5 V. If is reduced from 5 V or the reference voltage at OUT increased to more than 2.5 V, the differential nonlinearity of the DAC will increase and the linearity of the DAC will be degraded. SUPPLEMENTAL APPLICATION MATEIAL For further information on CMOS multiplying D/A converters, the reader is referred to the following texts: CMOS DAC Application Guide, Publication Number G872b-8-/89 available from Analog Devices. Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs Application Note, Publication Number E60c-5-/86 available from Analog Devices. Analog-Digital Conversion Handbook available from Analog Devices. 6 EV. B

7 AD754A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal Ceramic Leadless Chip Carrier (E-20A) 20-Lead Plastic Leadless Chip Carrier (P-20A) 0.58 (9.09) 0.58 (9.09) 0.42 (8.69) MAX SQ SQ 0.00 (2.54) (.6) (2.24) (.7) (2.4) (.90) 0.0 (0.28) (0.8) TYP (.9) EF (5.08) (.9) EF (.40) (.4) BOTTOM VIEW (.8) 0.00 (2.54) 0.05 (0.8) MIN (0.7) (0.56) (.27) 45 TYP (.2) (.07) (0.50) (.2) (.07) 9 4 PIN 8 IDENTIFIE TOP VIEW (PINS DOWN) (9.04) 0.50 (8.89) SQ 0.95 (0.02) 0.85 (9.78) SQ (.42) (.07) (.27) 0.80 (4.57) 0.65 (4.9) 0.0 (2.79) (2.6) (0.6) 0.05 (0.8) 0.02 (0.5) 0.0 (0.) 0.0 (8.8) 0.02 (0.8) (7.7) (0.66) (.0) (0.64) 8-Lead Plastic DIP (N-8) 8-Lead Cerdip (Q-8) (2.49) (2.47) (0.) MIN (2.49) MAX (4.06) 0.5 (2.9) (0.558) 0.04 (0.56) (7.) (6.0) PIN (.52) (0.8) (5.) MAX (2.54) (.77) (.5) (.0) MIN SEATING PLANE 0.25 (8.25) 0.00 (7.62) 0.95 (4.95) 0.5 (2.9) 0.05 (0.8) (0.204) (5.08) MAX (5.08) 0.25 (.8) 0.02 (0.58) 0.04 (0.6) 0 9 PIN (24.8) MAX 0.00 (2.54) (.78) 0.00 (0.76) 0.0 (7.87) (5.59) (.52) 0.05 (0.8) 0.50 (.8) MIN SEATING PLANE (8.) (7.7) 0.05 (0.8) (0.20) 8-Lead SOIC (-8) (.75) (.5) (7.60) (7.40) 0.49 (0.65) 0.97 (0.00) PIN 0.04 (2.65) (2.5) (0.74) (0.25) x (0.0) (0.0) (.27) (0.49) 0.08 (0.5) SEATING PLANE (0.2) (0.2) (.27) (0.40) EV. B 7

8 PINTED IN U.S.A. C78b 6/97 8