Effective Power Integrity Floor-Planning and Success Stories in Japan

Transcription

1 Effective Power Integrity Floor-Planning and Success Stories in Japan Giga Hertz Technology Inc, CEO Ryuji Kawamura 1

2 Agenda 1. Early Stage PI analysis Needs 2. Basic PI theories 3. Floor-planning PI analysis and its Effect 4. Case Studies 4

3 1. Early Stage PI analysis Needs 5

4 Case1 : Total optimization by using Co-Design for Chip/PKG/PCB Design Co-Design for Chip/PKG/PCB Design Cost reduction and rapid time-to-market Partial optimization has been shifting to total optimization. Co-design Working Group of LPB ( LSI-Package-Board ) in JEITA Examine Co-design flow and common data format Chip design Package design PCB design Key to LPB design success is early stage design & analysis

5 Case2 : Early Stage PI Analysis for PCB Design Schematic Design Layout Design Evaluation Testing Pre-PI Prototyping Analysis tool Middle-PI 2-D based PI analysis tool Sign-off tool High-accuracy PI analysis tool Pre-layout PI analysis Component Selection Optimize the design rule Number of Capacitors Mounting rule for Capacitors Stackup and Plane Shape Middle of the layout design Feed back from the real design Reconsideration the design rules Final Confirmation Final Impedance analysis SSN analysis ery Accurate time consuming EMI analysis Fast analyses are required to simulate the what-if analysis many times. 7

6 Requirement for Floor-Planning Tool Easy and Fast to create the Prototype design ery Fast Simulation What-If analysis and easy to compare the other condition That s why We developed the PDNDesigner and PDNExpert ( continue to improve based on the Customer s voice ) 8

7 2. Basic PI Theory 9

8 Keyword of PI analysis Input Impedance (Z11) Self impedance when normalized AC current source is excited. Transfer Impedance (Z21) ictim voltage noise when normalized AC current source is excited The parameter is related to EMI as well as PI Target Impedance Input impedance should be below target impedance in order to suppress power noise 10

9 oltage Fluctuation Equation Port1 Port2 RM 1 2 ( t) = ( t) = IFFT IFFT [ Z ] [ ] 11( f ) I1( f ) + IFFT Z12( f ) I2( f ) [ Z ( f ) I ( f )] + IFFT[ Z ( f ) I ( f )] How to Decrease Power Bus Noise 1. Reduce Input Impedance (Z11,Z22) of the chip Capacitor, Number of Power pins, On chip Cap 2. Reduce Transfer Impedance (Z12,Z21) from other chips Low Impedance theory & High Impedance theory 3. Reduce Current alue (i1(f),i2(f)) IO buffer Optimization 11

10 Fundamental Characteristics of Capacitor Model Equivalent Circuit Model Fundamental Characteristics 1 Z = R + jωl + jωc Capacitor Model Capacitor Mounting Inductance Model ESR ESL Lmnt Self-resonant Frequency 1 2π LC Capacitance Capacitance Characteristics Inductance Characteristics 12

11 Fundamental Characteristics of Capacitors Capacitance ESL 0.01uF 2nH 0.5nH 10uF 0.1uF 0.1nH ESR 1000mΩ 100mΩ Knowledge of capacitor characteristics help to understand PI analysis. 10mΩ 13

12 Reduce the high frequency noise => Reduce the Mounting Inductance Location of capacitors on PCB Calculates parasitic inductance between CC pin and capacitor location. Pad Stack Calculates parasitic inductance caused by pad stack and traces. ia Shape Calculates parasitic inductance caused by via dimension. + = Location of capacitor on board Pad Stack Estimate the optimal mounting conditions

13 Reduce the high frequency noise => Low-ESL Capacitors Capacitor :0.1uF G G G G G G G G G 15

14 Fundamental Characteristics of Power Plane Parameters for defining power plane W1 W2 Dielectric Thickness Copper Thickness Dielectric Thickness Plane Dimension Stackup Capacitance Characteristics Inductance Characteristics Plane Resonance 16

15 Frequency Distribution and Relationship to Chip PKG PKG PCBPCB Capacitor in PKG Capacitor in PCB RM RM PCB PKG Chip/PKG Chip Bulk Capacitor Ceramic Capacitor Capacitor in PKG 17

16 Effective Frequency Range of PCB Capacitors Lower limit by RM Inductance Frequency range where PCB capacitors are effective Upper limit by PKG Inductance ery Important to know the effective frequency range 18

17 3.Floor-planning PI analysis and its Effect Analysis Tool : PDNExpert 19

18 Case Study I Input impedance analysis Pre-layout PI analysis Positive Effects No additional re-design Reduced capacitor quantity Additional benefits : Time to simulate Setup time : about 1hour Simulation time : about 20sec/1 per simulation Real time simulation during meeting with layout designer and circuit designer

19 Case Study II Plane Resonance Analysis Before design : EMI issues occurred Increase EMI countermeasure components Current design : Introduce Pre-PI analysis Power Plane shape and capacitor optimization Advantages Capacitor number reduction Plane Impedance dramatically decreased EMI noise reduction

20 Case Study Ⅲ Chip/PKG/PCB Co-simulation System noise examination of Chip design flow in the early stage PCB Prototyping : PDNExpert 31

21 Summary 1. Early Stage PI analysis Needs 2. Basic PI theories 3. Floor-planning PI analysis and its Effect 4. Demonstration Ryuji Kawamura 35