Power Delivery Network (PDN) Analysis

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1 Power Delivery Network (PDN) Analysis Edoardo Genovese

2 Importance of PDN Design Ensure clean power Power Deliver Network (PDN) Signal Integrity EMC Limit

3 Power Delivery Network (PDN) VRM Bulk caps MB caps Active device Power net Ref. net PDN consists: 1. VRM (voltage regulator module) 2. Capacitors (Decoupling/Bypass) 3. PCB parasitic impedance 4. Active device (On Package Decap)

4 Power Integrity Simulation IR-Drop AC PI Analysis Decap Analysis Tool SSO from DDR2 Module PCB+Pckg+Chip Courtesy of SIEMENS

5 Board Description 8 metal layers board with total thickness 1.696mm 1.8V power plane to be analyzed located in 4th layer 1 memory controller and 2 DDR2 memory modules 130mm 70mm CST COMPUTER SIMULATION TECHNOLOGY Jun-15 Courtesy of SIEMENS

6 IR-Drop Simulation Component Voltage (V) VDD Drop (V) GND Drop (V) DC Resistance 1.8V 19 CPU pins, 16 Mem I pins & 16 Mem II 20mA Memory controller Group m 1.007m 575mOhm Memory Module I Group m 0.969m 498mOhm Memory Module II Group m 0.929m 469mOhm II I Mem. Ctrl JEDEC 79-2F

7 PDN Impedance of 1.8V Net 3 PDN Impedances are plotted from three different components: D1 the memory controller D3 and D4 the memory modules

8 Spatial Impedance Plot Impedance plot on P1V8 plane seen from memory controller Impedance plot on P1V8 plane seen from memory module I Impedance plot on P1V8 plane seen from memory module

9 Decap Placement 220pF Decaps shifts the high impedance at its placement area

10 SSO Analysis for 2 DQ lines 2 I/O Buffer: Driver VRM I/O Buffer: Input DDR2-400 I/O Buffer IBIS PRBS N=7

11 Transient Response Power Supply VDD No Decaps With Decaps

12 Decap Analysis Tool Over designing the PCB Additional BOM cost slightly or without performance improvement Define the target impedance Multiple goals: Optimizing the BOM cost Optimizing the PDN impedance Define the list of parts for optimization Start the optimization CST COMPUTER SIMULATION TECHNOLOGY Jun-15

13 Decap Analysis Tool Optimization (Step 1) Target Impedance Part lib. of current Decaps mounted on PCB

14 Decap Analysis Tool Optimization (Step 2) Removing the decaps from PCB (Bare board)

15 Decap Analysis Tool - Results Locate the marker to impedance curve manually and optimizing the impedance Impedance curve with 10 decaps Before: 76 After : 52 Initial config. with 23 decaps

16 Decap Analysis Tool Results (II) Run the automatic impedance optimization Impedance curve after optimization Before: 76 After : 33

17 PDN Impedance: PCB + I/O Buffer Pckg VDD Line PDN Impedance Z PACKAGE PCB + - VRM VSS Line

18 PDN Impedance Comparison Series resistive and inductance from package

19 PDN Impedance: PCB + Package + Chip SPICE model from Vendor or CHIP PACKAGE VDD Line PCB + - VRM using c_comp keyword from I/O buffer IBIS Total PDN Impedance Z VSS Line

20 PDN Impedance Comparison Lumped RC DIE or better SPICE improve the high frequency PDN Imp.

21 SSO Analysis Setup RLC Package CHIP SPICE model

22 Transient Response PCB only PCB + Package + Chip Max Noise: 1.89V Max Noise: 1.84V

23 Impedance Measurement Method Zconnection Zconnection Z connection Z 11 V I 1 1 I 2 0 Z conn. Z DUT Z DUT Z 12 V I 1 2 I 0 1 V I 2 2 Z conn. Z DUT Z DUT Z DUT Two port shunt-through measurement: Measuring the Z DUT One port measurement: Measuring the Z connection + Z DUT

24 Probing Position Goals: Very small layout area for probing (2mm²) High frequency measurement (up to 10GHz) PWR pins GND pins

25 Comparison Measurement of bareboard Measurement with mounted decaps

26 Conclusions Frequency Domain Analysis Quick and less computational effort Optimization via Decap Tool analysis No charging effect Time Domain Analysis Provides more realistic I/O behavior (using IBIS buffer) Higher simulation time for complex board HPC Impedance Measurement One Port measurement Two port measurement

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