Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

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1 Nine-Coded Copression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decopression Mohaad Tehranipour, Mehrdad Nourani Center or Integrated Circuits & Systes The Univ o Texas at Dallas Richardson, TX 7583 Krishnendu Chakrabarty Dept o Electrical and Coputer Engineering Duke University Durha, NC 778 krish@eedukeedu Abstract This paper presents a new test data copression technique based on a copression code that uses exactly nine codewords In spite o its siplicity, it provides signiicant reduction in test data volue and test application tie In addition, the decopression logic is very sall and independent o the precoputed test data set Our technique leaves any don t-care bits unchanged in the copressed test set, and these bits can be illed randoly to detect non-odeled aults The proposed technique can be eiciently adopted or single- or ultiple-scan chain designs to reduce test application tie and pin requireent Experiental results or IAS 89 bencharks illustrate the lexibility and eiciency o the proposed technique I INTRODUCTION Testing today s syste-on-chip (SoC) circuits is diicult due to large test data volue, long test application tie, high power consuption during test, and liited bandwidth o autoatic test equipent (ATE) New techniques are needed to test ebedded cores in an SoC without exceeding liits power, ATE eory and bandwidth These techniques are oten based on test resource partitioning (TRP) to reduce ATE eory and test power and tackle ATE bandwidth liitation There are several techniques to reduce SoC test data volue and test application tie Built-in sel-test (BIST) ethodology reduces the need or an expensive ATE [] In BIST, on-chip pseudo-rando pattern generators and signature copaction are used In practice, BIST cannot replace other test ethods especially or large chips due to the long tie needed to detect rando pattern resistant aults To overcoe these diiculties, deterinistic test patterns need to be transerred ro the ATE to the SoC under test to shorten overall test tie and iprove ault coverage While the ault coverage in BIST can be iproved using techniques such as reseeding [], bit lipping [3] and bit-ixing [4], these techniques need structural inoration or ault siulation and test generation Test data copression techniques are used to speed up the ATE-SoC interaction during test These techniques are used to copress the precoputed test data set T D provided by core vendor to a saller test set T E ( T E T D ) which is then stored in the ATE s eory An on-chip decoder decopresses T E to T D to be applied to the core under test Many copression techniques have been proposed in recent years, however none has becoe standardized or is universally applicable Many o the proposed solutions in the past ew years are proprietary, this reduces lexibility and interoperability aong tools Copression ethods such as statistical coding [5] [6], selective Huan o the Design, coding Autoation [7], Golob and coding Test Europe [8], FDR Conerence coding and Exhibition (DATE 4) Proceedings 53-59/4 $ 4 IEEE [9], alternating run-length coding using FDR [], EFDR coding [], MTC coding [] and VIHC coding [3] have been proposed to reduce test data volue These techniques copress T D without requiring any structural inoration or the test application ro the core vendor There are soe structural ethods or reducing test volue and tie which requires design odiication The proposed Illinois scan architecture (ILS) [4] needs ault siulation and test generation as postprocessing steps to get high ault coverage Other techniques are based on on-chip pattern decopression, such as scan-chain concealent [5], geoetric-priitive based copression [6], utation encoding [7], deterinistic ebedded test (reusing the scan chain o one core in a SoC to copress the patterns or another core) [8], packet-based copression [9] and LFSR reseeding [] [] [] An ebedded deterinistic test technology or low cost test to reduce the scan test data volue and scan test tie is presented in [] Several dictionary-based copression ethods have recently been proposed to reduce test data volue In [6], requently occurring blocks are encoded into variable-length indices using Huan coding A dictionary with ixed-length indices is used to generate all the distinct output vectors in [3] Test data copression techniques based on LZ77 and LZW ethods are proposed in [4] and [5], respectively The orer uses a dynaic dictionary and the latter uses a eory in the on-chip decoder The ethod proposed in [6] is a copression technique using dictionary with ixed-length indices There are usually a large nuber o don t-care bits in a precoputed test data set T D These don t-cares are used to help copression techniques achieve higher copression Generally, ATPG ills don t-cares randoly to have ore chance o detecting non-odeled aults to increase deect coverage Soe o the above proposed techniques replace existing don t-cares in T D with or to generate a saller T E and the on-chip decoder generates T D without don t-care Such copression ay adversely aect the ault coverage o non-odeled aults Thereore, new techniques are required to leave at least a portion o don t-caresunchanged, suchthattheycan bereplaced randoly to help detect non-odeled aults In this paper, we present a new copression technique based on a copression code with only nine codewords Our ethod achieves signiicant copression or precoputed test set, reduces test application tie, and requires a very sall decoder Since we use ixed-length blocks, the proposed ethod oers ease o synchronization between the decoder and ATE The

2 technique is quite lexible in reducing test tie and ATE s testpin requireent or single- and ultiple-scan chain designs, respectively Another advantage o the proposed technique is having letover don t-care bits in T E, which can be illed randoly to detect non-odeled aults The rest o this paper is organized as ollows Section II describes the proposed test data copression technique Section III discusses the single- and ultiple-scan chain decoder architectures, and provide test tie analysis The experiental results are shown in Section IV Finally, the paper presents the concluding rearks in Section V II 9C COMPRESSION TECHNIQUE The proposed technique is based on ixed-length-input test data copression Assue that K is thesizeo theixed-length input blocks The input test vectors are partitioned into groups o K bits and encoding is perored on each K-bit block Table I shows the proposed coding or K=8 As shown in the table, each K-bit block is divided into two K halves As shown, there are overall nine codewords For the rows to 4, each hal K-bit is atched with all s or s Rows 5-8 show the isatched bits, which have to be sent along with the codeword (UUUU is called a isatch eaning this hal has ix o and and perhaps don t-care X) Row 9 shows that each hal is a isatch and the entire K-bit block has to be sent along with the codeword The third colun shows a sybol or each case The sixth colun shows the decoder input which can be only a codeword (in the irst our rows) or codeword plus the isatch portion (in the last ive rows) Finally, the last colun shows the inal code size or each case In this technique, regardless o K, we use only nine unique codewords shown in the ith colun in Table I Hence, we call our ethod nine-coded copression, or 9C or short In the 9C technique, the input test vectors are divided into K-bit blocks and each K-bit block is divided into two parts The various cases that can arise are atched with one o the above sybols For exaple, assuing X represents don t-cares in one hal o a block, blocks o, X, X and XX are all atched with sybol Blocks o, X and X are atched with sybol Blocks o XU, U and UX, U are atched with sybols U and U, respectively We acknowledge that ore nuber o unior K-bit blocks (eg,, etc) can be added to Table I However, a systeatic coding in such cases requires 4 7 codewords This ay slightly iprove the copression ratio but results in a ore coplicated and expensive decoder In this paper we ocus on having nine codes since our experientation indicates that it provides the best tradeo between copression and decoder cost Figure Figure III 9C DECOMPRESSION ARCHITECTURE The 9C technique is lexible to be used or copressing input test data or single-scan chain or ultiple-scan chain designs Here, we propose a sall and lexible decopression architecture or each case A Single-Scan Chain Decoder B Multiple-Scan Chain Decoder Figure shows the decoder architecture or a single-scan Proceedings chain Decoder o the decodes Design, Autoation only nine and preix-ree Test in Europe codeword Conerence inde- and Exhibition (DATE 4) 53-59/4 $ 4 IEEE Ack Dec_en Clk_ate FSM Clk_soc Shit_en Sel Cnt_en Inc Done K/-bit shiter log (k/) counter 9C decoder architecture or single-scan chain C3 C C4 Dec_en S4 S C C5 Ack S S3 S5 FSM diagra o 9C decoder C7 C6 S S7 C8 S6 C9 M U X D_out pendent o K value and precoputed test data set _en The decoder consists o a inite-state achine (FSM), a log K - bit counter and an K -bit shiter The FSM takes data ro Data in to ind out which codeword has been entered I the input codeword is C, C, C 3 or C 4,allK bits are generated only with s or s accordingly When the FSM receives the codewords C 5, C 6, C 7, C 8 or C 9, it expects to receive K -bit or K-bit exact data ro Data in As shown in this igure, MUX has three inputs, and Data in which is shited through K -bit shiter Two bits select (Sel) coe ro FSM to MUX The log K -bit counter is used to control sending K -bit into scan chain The FSM sends signals Cnt en and Inc to activate and increent the counter, respectively At the sae tie, it activates signal en to enable the scan chain, hence D out is shited into the scan chain () When counter inishes counting, it sends signal Done to the FSM to send the next Sel and Cnt en Ater sending the second signal Done by counter, FSM sends Ack signal to the ATE to send the next codeword and deactivates signal en Figure shows the state diagra o the 9C decoder Note careully that it is totally independent o K It starts by checking Dec en WhenDec en is active, it receives the Data in which is the codeword ro ATE Maxiu o ive cycles are required or the longest codeword Since a K-bit block is divided into two halves, the FSM sends one Sel or each hal Ater detecting a codeword the required signals are sent to the counter, MUX and scan chain When the job is done or one received codeword, the state controller starts again ro state S Thisis done when Ack signal becoes active, then ATE sends the next codeword Let denote the nuber o scan chains in a circuit under test The 9C technique can be used to copress the input test data

3 TABLE I 9C CODING FOR K=8 Case (i) Input Block Sybol Description Codeword (C i ) Decoder Input Size (bits) All s All s 3 Let hal, right hal 5 4 Let hal, right hal 5 5 UUUU U Let hal, right hal isatch UUUU 5+K/=9 6 UUUU U Let hal isatch, right hal UUUU 5+K/=9 7 UUUU U Let hal, right hal isatch UUUU 5+K/=9 8 UUUU U Let hal isatch, right hal UUUU 5+K/=9 9 UUUU UUUU UU All isatch UUUUUUUU 4+K= vertically ie, with respect to chain In this case, the -bit data are divided into groups o K-bit blocks The decoder is shown in Figure 3 The FSM sends Cnt en to enable the log K and log K counters and Shi t en to let the D out to be shited into the -bit shiter The FSM used in ultiple-scan chain decoder is the sae as the one used or single-scan chain decoder A log K counter is used to control shiting bits into the -bit shiter Any tie that log K counter sends K bit into the -bit shiter, signal Done is sent to the FSM to send the next Sel and Cnt en and log K counter to be increented by one When the log K counter is equal to K, eaning bits have been shited into -bit shiter, it sends the signal Load to -bit shiter to load its content into the scan chains to This architecture reduces the input test pins which only one input test pin is required In this case, only one decoder is used or scan chains Assue that the length o scan chain is l Figure 4(a) shows the single-scan chain decoder, used to decode and send the test patterns into a l-bit scan chain In this case, l clock cycles are required to shit l bits into the scan chain Assue that the l bit scan chain is rearranged into groups o -bit scan chains In this case, the length o each scan chain is l Figure 4(b) shows a ultiple-scan chain decoder with one input pin and one decoder The ATE sends codewords through Data in and the decoder drives the detected bits into the -bit shiter This case does not increase test tie copared to single-scan chain, because each detected K-bitisshitedintothe-bitshiterand ater copleting -bit, the content o -bit shiter is sent into scan chains which uses l clock cycles This architecture reduces test pins to while keeping the test application tie unchanged Note that the ultiple-scan chain architecture can be extended to reduce the ATE pin count requireent to any desired raction o as shown in Figure 4(c) For exaple, assue that we use one decoder or each K-bit Instead o having - bit shiter as shown in Figure 3, we need K-bit shiter such that or each K nuber o scan chains only one input pin is required Thereore, or nuber o scan chains, K input pins and decoders are needed which increases hardware overhead but decreases the test tie by a actor o K copared to having only one input test pin (see Figure 4(c)) because K decoders work in parallel In this case, Kl clock cycles are required C Test Application Tie Reduction Reducing the overall test application tie is one o the iportant goals o any test data copression ethod In general, the aount o tie reduction depends on the copression ratio and decopression ethod In this section, we estiate the Figure 3 Ack Dec_en Clk_ate FSM Clk_soc Shit_en Sel Cnt_en Inc Done K/-bit shiter Inc log (k/) counter log (/k) counter M U X Shit_en Load 9C decoder architecture or ultiple-scan chains D_out CUT CUT CUT Decoder (a) Decoder (b) /k -bit shiter Decoder Decoder Decoder (c) k k+ k -k+ Figure 4 Dierent scan architectures: (a) Single-scan single-pin, (b) Multiplescan single-pin (c) Multiple-scan K pins overall test application tie reduction ratio (TAT) or singlescan chain Since 9C is a ixed-block copression technique, the test tie analysis is sipler copared to the variable-block copression techniques Suppose the ATE and SoC scan requencies are and scan ( scan ), respectively TAT is given by TAT% Proceedings o the Design, Autoation and Test in Europe Conerence and Exhibition (DATE 4) 53-59/4 $ 4 IEEE t no cop t cop t no cop where t no cop and t cop are the test application ties or applying uncopressed and copressed test data, respectively Assue that the scan clock requency o the syste under test is p ties that o the ATE s clock requency scan p The test application tie or the case o no copression (t no cop ) depends on the total nuber o input bits (T D )and ATE s working requency t no cop T D p T D scan Ater copressing the test data, the test application tie t cop depends on the occurrence requency (repetitions) o each

4 codeword C i LetN i denote occurrence requency o C i Thereore, in our ethod t cop is given by: t cop t t t 3 4 t 5 8 t 9 where t, t, t 3 4, t 5 8 and t 9 are the application tie o codewords C, C, C 3, C 4, C 5, C 6, C 7, C 8 and C 9,respectively Note that t 3 4=t 3 +t 4 and t 5 8=t 5 +t 6 +t 7 +t 8 When codeword C is entered into the FSM, only one ATE s clock is required (because C is one bit), K syste s clocks are needed or applying K s into the scan chain Hence, t = + K scan, where scan =p Due to the lack o space, the details o the estiation approach or all t s are not discussed here However, the tie paraeters will be: t = t = t 3 4 = t 5 8 = t 9 = K C p N K C p N K C 3 p N 3 4 K K C 5 p K K C 9 p N 9 scan N 5 8 where N, N, N 3 4, N 5 8 and N 9 are the occurrence requency o codewords C, C, C 3, C 4, C 5, C 6, C 7, C 8 and C 9, respectively Note that N 3 4=N 3 +N 4 and N 5 8=N 5 +N 6 +N 7 +N 8 C i is the size o codeword C i, that are C =, C =, C 3 = C 4 = C 5 = C 6 = C 7 = C 8 =5 and C 9 =4 IV EXPERIMENTAL RESULTS Table II shows the copression results o IAS89 s bencharks or dierent K s using 9C technique or single-scan chain The copression ratio (CR) is coputed by: CR% = T D T E T D T E = C N C N C 3 N 3 4 K C 5 N 5 8 K C 9 N 9 As seen in Table II, the axiu copression ratio or these bencharks happens in K=8, or 6 When K increases the copression ratio increases to reach a peak at K=8,, or 6 and then it starts to decrease in ost o the cases As shown, K=3 generates less copression ratio copared to other K s The last row shows the average copression ratio or each K on all bencharks and it indicates that K=8 shows ore average copression ratio copared to other K s or these bencharks It eans that having K=8 or all these bencharks, the decoder gives very high copression ratio which is independent o the bencharks and precoputed test sets The FSM has been ipleented by Synopsys Design Copiler [7] and it includes 4 gates Table III shows the letover don t-care (LX) percentage or each benchark or dierent K s These don t-care bitscan be replaced randoly to detect soe o the non-odeled aults The second colun in the table shows the existing don t-care percentage (X%) o each benchark As shown, when K increases the LX increase in which the axiu LXs or all benchark happen in K=3 Note that or K 4 each hal is a 53-59/4 $ 4 IEEE Proceedings o the Design, Autoation and Test in Europe Conerence and Exhibition (DATE 4) very sall -bit block where all don t-cares need to be replaced according to our technique The last row shows the average LX or all bencharks or each K O course, the letover don tcare bits can be also used to reduce the total scan-in power Soe researchers replace the don t-cares with or to iniize the transitions between the consecutive bits Power issue is beyond the scope o this paper Based on Tables II and III, we are able to tradeo between the letover don t-cares (LX) and copression ratio I user asks or a speciic aount o don t-cares to possibly detect soe o the non-odeled aults K is obtained ro Table III and the copression ratio is obtained ro Table II Coparing the 9C technique with the other techniques (FDR [], VIHC [3], MTC [] and Selective Huan [7]) is shown in Table IV As the last row shows the average copression ratio o the 9C technique is ore than others Table V shows the test application tie reduction or IS- CAS89 bencharks or dierent working requencies o the syste under test The next three coluns show the result or p=8, p=6 and p=4, respectively TAT is bounded by CR, eaning as p scan increases, the test application tie approaches copression ratio For exaple, assue that =MHz (a very slow ATE) and SoC requency to shit test data into scan chain scan =6MHz (p=8) The average TAT%=559%, indicates good reduction in test application tie or such a low speed ATE Table VI shows the statistics o occurrence requencies o each codeword (N i ) in the bencharks As the last row in the table shows, codeword C always happens ore requently than the other codewords which it has the iniu codeword size (one bit) C is the second requent codeword which has the second iniu codeword length (two bits) And C 9 is in third place with codeword size our bits The other codeword (C 3, C 4, C 5, C 6, C 7 and C 8 ) have the sae codeword size (ive bits) which occur less requently copared to C, C and C 9 This statistics show that the proposed coding is the best or these bencharks and indicates the coding eiciency or these bencharks and we expect it to be the sae specially or large circuits When the occurrences are dierent, the 9C technique can be eployed using a requency-directed strategy Such statistics or a circuit can be obtained apriori And or a special architecture, codewords can be rearranged according to the real occurrence requencies o codewords in the test pattern set Although or ajority o circuits we expect the order proposed in Table I be the best As shown in Table VI, soe bencharks (eg s5378, s934 and s585) do not coply with the order o occurrence requencies shown in the last row For exaple, or the bencharks s934 and s585 soe other codewords like C 8 (in s934) and C 7 (in s585) have ore occurrence requency than codeword C 9 To get the best copression ratio or these two bencharks, we change the order o codewords as C 8 in s934 and C 7 in s585 to have our bit codeword size, respectively Table VII shows the new copression results based on re-assigned codewords (requency-directed assignent) according to the occurrence requencies in these three bencharks As shown, there are slight iproveents or each K copared to the original results shown in Table II

5 TABLE II COMPRESSION RATIO FOR DIFFERENTK S Circuit T D CR% K=4 K=8 K= K=6 K= K=4 K=8 K=3 s s s s s s Avg TABLE III LEFTOVER DON T-CARES (LX) FOR DIFFERENT K S Circuit X% LX% K=4 K=8 K= K=6 K= K=4 K=8 K=3 s s s s s s Avg TABLE IV COMPARISON BETWEEN DIFFERENT TECHNIQUES Circuit K 9C FDR [] VIHC [3] MTC [] Selec Hu [7] s s s s s s Avg TABLE V TEST APPLICATION TIME REDUCTION (TAT%) USING 9C TECHNIQUE Circuit K CR% TAT% scan 8 scan 6 scan 4 s s s s s s Avg TABLE VI CODEWORD STATISTICS OF THE BENCHMARKS Circuit K N N N 3 N 4 N 5 N 6 N 7 N 8 N 9 s s s s s s Avg TABLE VII COMPRESSION RATIO FOR THREE BENCHMARKS AFTER RE-ASSIGNING THE CODEWORDS BASED ON OCCURRENCE FREQUENCIES Circuit CR% K=4 K=8 K= K=6 K= K=4 K=8 K=3 s s Proceedings o the Design, Autoation s585 and Test 658 in Europe 665Conerence and Exhibition 647 (DATE 4) /4 $ 4 IEEE

6 TABLE VIII COMPRESSION RESULTS FOR TWO LARGE CIRCUITS FROM IBM Circuit X% T D K CKT CKT We also evaluated the copression eiciency o the 9C technique or very large test sets ro IBM previously reported in [6] Circuit CKT contains 36 illion gates, 76 lip lops and requires about 6 Mbit test data Circuit CKT has illion gates, 3 lip lops and needs 4 Mbit test data Table VIII shows the copression ratio or dierent K s As shown, K=48 and K=3 show the axiu copression or CKT and CKT, respectively The style, cost and lexibility o on-chip decopresser have becoe iportant actors in practicality o copression techniques Speciically, soe decoders such as those proposed in [5] [6] [7] [3] [3] are dependent on the precoputed test set and thus are custoized or the circuit under test The decopression logics in [9] [] are independent o the precoputed test set However, since the ethods are based on variablelength coding, the nuber o codewords required to be decoded or the large circuits can be huge Thereore, or having an independent decoder, they have to consider a possible axiu length happening in the test set But, the 9C technique s decoder is totally independent o the circuit under test and precoputed test set In other words, or the circuits using the sae K, the decoder reains the sae, no atter what the precoputed test data set is This eature akes our 9C technique superior in ters o cost, lexibility and design reuse V CONCLUSION A new copression technique using only nine codewords called 9C has been proposed in this paper It signiicantly reduces the test data volue and application tie The letover don t-care bits or -5% o data volue and can be utilized or detecting soe o the non-odeled aults Using the 9C technique, it is possible to tradeo between test volue-tie, pin-count requireent and letover don t-cares Ipleentation o 9C technique on IAS bencharks has shown up to 83% copression The decopression logic is very sall and lexible and independent o the precoputed test data set ACKNOWLEDGEMENTS The work o M Tehranipour and M Nourani was supported in part by the National Science Foundation CAREER Award #CCR-353 The work o K Chakrabarty was supported by the National Science Foundation under grants CCR and CCR-477 REFERENCES [] Y Zorian, E Marinissen and S Dey, Testing Ebedded-Core-Based Syste Chips, Coputer Magazine, 3(6), pp 5-6, 999 [] S Hellebrand, H Linag and H -J Wunderlich, A Mixed-Mode BIST Schee Based on Reseeding o Folding Counters, in Proc Int Test Con (ITC ), pp , [3] H -J Wunderlich and G Kieer, Bit-Flipping BIST, in Proc Int Test Con (ITC ), pp , 996 [4] N Touba and E McCluskey, Altering a Pseudo-Rando Bit Sequence or Scan Based BIST, in Proc Int Test Con (ITC ), pp 67-75, /4 $ 4 IEEE Proceedings o the Design, Autoation and Test in Europe Conerence and Exhibition (DATE 4) [5] V Iyengar, K Chakrabarty and B Murray, Built-In Sel Testing o Sequential Circuits Using Precoputed Test Sets, in Proc VLSI Test Syp (VTS 98), pp 48-43, 998 [6] A Jas, J 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