Lecture Notes in Electrical Engineering

Transcription

1 Lecture Notes in Electrical Engineering Volume 73 For other titles published in this series, go to

2 Guy Gogniat Dragomir Milojevic Adam Morawiec Ahmet Erdogan Editors Algorithm- Architecture Matching for Signal and Image Processing Best papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009

3 Editors Guy Gogniat Lab-STICC-CNRS, UMR 3192, Centre de Recherche Université de Bretagne Sud UEB BP Lorient Cedex France Dragomir Milojevic Université libre de Bruxelles CP , Av. FD Roosevelt Bruxelles Belgium Adam Morawiec ECSI Av. de Vignate Gières France adam.morawiec@ecsi.org Ahmet Erdogan School of Engineering The University of Edinburgh Mayfield Road EH9 3JL Edinburgh United Kingdom ahmet.erdogan@ee.ed.ac.uk ISSN e-issn ISBN e-isbn DOI / Springer Dordrecht Heidelberg London New York Library of Congress Control Number: Springer Science+Business Media B.V No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Cover design: VTEX, Vilnius Printed on acid-free paper Springer is part of Springer Science+Business Media (

4 Preface Advances in signal and image processing together with increasing computing power are bringing mobile technology closer to applications in a variety of domains like automotive, health, telecommunication, multimedia, entertainment and many others. The development of these leading applications, involving a large diversity of algorithms (e.g. signal, image, video, 3D, communication, cryptography) is classically divided into three consecutive steps: a theoretical study of the algorithms, a study of the target architecture, and finally the implementation. Such a linear design flow is reaching its limits due to intense pressure on design cycle and strict performance constraints. The approach, called Algorithm-Architecture Matching, aims to leverage design flows with a simultaneous study of both algorithmic and architectural issues, taking into account multiple design constraints, as well as algorithm and architecture optimizations, that couldn t be achieved otherwise if considered separately. Introducing new design methodologies is mandatory when facing the new emerging applications as for example advanced mobile communication or graphics using sub-micron manufacturing technologies or 3D-Integrated Circuits. This diversity forms a driving force for the future evolutions of embedded system designs methodologies. The main expectations from system designers point of view are related to methods, tools and architectures supporting application complexity and design cycle reduction. Advanced optimizations are essential to meet design constraints and to enable a wide acceptance of these new technologies. This book presents a collection of selected contributions addressing different aspects of Algorithm-Architecture Matching approach ranging from sensors to architectures design. The scope of this book reflects the diversity of potential algorithms, including signal, communication, image, video, 3D-Graphics implemented onto various architectures from FPGA to multiprocessor systems. Several synthesis and resource management techniques leveraging design optimizations are also described and applied to numerous algorithms. The contributions of this book are split into three parts addressing major issues when designing embedded systems. The first part proposes key contributions in the domain of architectures for embedded applications and especially for image and v

5 vi Preface telecommunication processing. The second part focuses on data acquisition and design techniques for embedded systems. First, an optimized sensor for image acquisition is detailed. Then several multiplication and division operators are described. The end of this part proposes several contributions in the domain of partial and dynamic reconfiguration for signal and image processing. This technology leads to complex design issues which are addressed in this chapter. The third part targets embedded systems design. RTOS for embedded systems and scheduling techniques are first addressed. Finally CAD tools for signal and image processing are detailed. The coverage of this book is large and provides an in-depth analysis of existing techniques and methodologies to design embedded systems targeting image and signal processing. Guy Gogniat Dragomir Milojevic Adam Morawiec Ahmet Erdogan

6 Contents Part 1 Architectures for Embedded Applications Lossless Multi-Mode Interband Image Compression and Its Hardware Architecture... 3 Xiaolin Chen, Nishan Canagarajah, and Jose L. Nunez-Yanez Efficient Memory Management for Uniform and Recursive Grid Traversal 27 Tomasz Toczek and Stéphane Mancini Mapping a Telecommunication Application on a Multiprocessor System-on-Chip Daniela Genius, Etienne Faure, and Nicolas Pouillon Part 2 Data Acquisition and Embedded Systems A Standard 3.5T CMOS Imager Including a Light Adaptive System for Integration Time Optimization Gilles Sicard, Estelle Labonne, and Robin Rolland Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor Daniel R. Kelly, Braden J. Phillips, and Said Al-Sarawi RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip Daniel Chillet, Sébastien Pillement, and Olivier Sentieys A New Three-Level Strategy for Off-Line Placement of Hardware Tasks on Partially and Dynamically Reconfigurable Hardware Ikbel Belaid, Fabrice Muller, and Maher Benjemaa End-to-End Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems Jérémie Crenne, Pierre Bomel, Guy Gogniat, and Jean-Philippe Diguet vii

7 viii Contents Part 3 Embedded Systems Design SystemC Multiprocessor RTOS Model for Services Distribution on MPSoC Platforms Benoît Miramond, Emmanuel Huck, Thomas Lefebvre, and François Verdier A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention Pengcheng Mu, Jean-François Nezan, and Mickaël Raulet Multiprocessor Scheduling of Dataflow Programs within the Reconfigurable Video Coding Framework Jani Boutellier, Christophe Lucarz, Victor Martin Gomez, Marco Mattavelli, and Olli Silvén A High Level Synthesis Flow Using Model Driven Engineering Sébastien Le Beux, Laurent Moss, Philippe Marquet, and Jean-Luc Dekeyser Generation of Hardware/Software Systems Based on CAL Dataflow Description Richard Thavot, Romuald Mosqueron, Julien Dubois, and Marco Mattavelli Index...293

8 Contributors Said Al-Sarawi CHiPTec, Centre for High Performance Integrated Technologies and Systems, The University of Adelaide, Adelaide, Australia, Ikbel Belaid University of Nice-Sophia Antipolis/LEAT-CNRS, 250 rue Albert Einstein, Valbonne, France, Maher Benjemaa National Engineering School of Sfax/Research Unit ReDCAD, Sfax, Tunisia, Sebastien Le Beux Institut des Nanotechnologies de Lyon, Ecole Centrale de Lyon, 36, Avenue Guy de Collongue, Ecully Cedex, France, Pierre Bomel LAB-STICC, Université Européenne de Bretagne, Lorient, France, Jani Boutellier Computer Science and Engineering Laboratory, University of Oulu, Oulu, Finland, Nishan Canagarajah University of Bristol, Bristol, UK, Xiaolin Chen University of Bristol, Bristol, UK, Daniel Chillet University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Kerampont, F22305 Lannion, France, Daniel.Chillet@irisa.fr Jérémie Crenne LAB-STICC, Université Européenne de Bretagne, Lorient, France, jeremie.crenne@univ-ubs.fr Jean-Luc Dekeyser LIFL and INRIA Lille Nord-Europe, Parc Scientifique de la Haute Borne, Park Plaza, Bât A, 40 avenue Halley, Villeneuve d Ascq 59650, France, Jean-Luc.Dekeyser@lifl.fr Jean-Philippe Diguet LAB-STICC, Université Européenne de Bretagne, Lorient, France, jean-philippe.diguet@univ-ubs.fr ix

9 x Contributors Julien Dubois Laboratoire LE2I, Université de Bourgogne, Dijon, France, Etienne Faure SoC Department, LIP6, 4 place Jussieu, Paris Cedex, France, etienne.faure@lip6.fr Daniela Genius SoC Department, LIP6, 4 place Jussieu, Paris Cedex, France, daniela.genius@lip6.fr Guy Gogniat LAB-STICC, Université Européenne de Bretagne, Lorient, France, guy.gogniat@univ-ubs.fr Victor Martin Gomez Computer Science and Engineering Laboratory, University of Oulu, Oulu, Finland, victor.martin@ee.oulu.fi Emmanuel Huck ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, Cergy-Pontoise, France, huck@ensea.fr Daniel R. Kelly CHiPTec, Centre for High Performance Integrated Technologies and Systems, The University of Adelaide, Adelaide, Australia, dankelly@eleceng.adelaide.edu.au Estelle Labonne TIMA Laboratory (CNRS, Grenoble INP, UJF), Grenoble, France Thomas Lefebvre ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, Cergy-Pontoise, France, lefebvre@ensea.fr Christophe Lucarz Microelectronic Systems Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, christophe.lucarz@epfl.ch Stéphane Mancini GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine Universitaire-B.P. 46, 38402, Saint Martin d Heres, France, stephane.mancini@gipsa-lab.inpg.fr Philippe Marquet LIFL and INRIA Lille Nord-Europe, Parc Scientifique de la Haute Borne, Park Plaza, Bât A, 40 avenue Halley, Villeneuve d Ascq 59650, France, Philippe.Marquet@lifl.fr Marco Mattavelli SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, marco.mattavelli@epfl.ch Marco Mattavelli Microelectronic Systems Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, marco.mattavelli@epfl.ch Benoît Miramond ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, Cergy-Pontoise, France, miramond@ensea.fr Romuald Mosqueron SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, romuald.mosqueron@epfl.ch

10 Contributors xi Laurent Moss Ecole Polytechnique de Montréal, Campus de l Université de Montréal, 2500, chemin de Polytechnique, 2900 boulevard Edouard-Montpetit, Montréal, Quebec H3T 1J4, Canada, Laurent.Moss@polymtl.ca Pengcheng Mu Ministry of Education Key Lab for Intelligent Networks and Network Security, School of Electronic and Information Engineering, Xi an Jiaotong University, Xi an , P.R. China, pengchengmu@gmail.com Fabrice Muller University of Nice-Sophia Antipolis/LEAT-CNRS, 250 rue Albert Einstein, Valbonne, France, Fabrice.Muller@unice.fr Jean-François Nezan IETR/Image and Remote Sensing Group, CNRS UMR 6164/INSA Rennes, 20, avenue des Buttes de Coësmes, Rennes Cedex, France, jnezan@insa-rennes.fr Jose L. Nunez-Yanez University of Bristol, Bristol, UK, J.L.Nunez-Yanez@bristol.ac.uk Braden J. Phillips CHiPTec, Centre for High Performance Integrated Technologies and Systems, The University of Adelaide, Adelaide, Australia, phillips@eleceng.adelaide.edu.au Sébastien Pillement University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Kerampont, F22305 Lannion, France Nicolas Pouillon SoC Department, LIP6, 4 place Jussieu, Paris Cedex, France, nicolas.pouillon@lip6.fr Mickaël Raulet IETR/Image and Remote Sensing Group, CNRS UMR 6164/INSA Rennes, 20, avenue des Buttes de Coësmes, Rennes Cedex, France, mraulet@insa-rennes.fr Robin Rolland CIME Nanotech, Grenoble, France Olivier Sentieys University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Kerampont, F22305 Lannion, France Gilles Sicard TIMA Laboratory (CNRS, Grenoble INP, UJF), Grenoble, France Olli Silvén Computer Science and Engineering Laboratory, University of Oulu, Oulu, Finland, olli.silven@ee.oulu.fi Richard Thavot SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, richard.thavot@epfl.ch Tomasz Toczek GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine Universitaire-B.P. 46, 38402, Saint Martin d Heres, France, tomasz.toczek@gipsa-lab.inpg.fr François Verdier ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, Cergy-Pontoise, France, verdier@ensea.fr