Operating System Support for Multiprocessor Systems-on-Chip
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1 Operating System Support for Multiprocessor Systems-on-Chip Dr. Gabriel marchesan almeida
2 Agenda. Introduction. Adaptive System + Shop Architecture. Preliminary Results. Perspectives & Conclusions Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
3 INTRODUCTION HOMOGENEOUS / HETEROGENEOUS PLATFORMS Network Processing Unit RISC USB Router Video Accelerator Power Managem. RAM Audio Accelerator Memory UART Y L D H AR BL E LA A C S Power CPU Bridge Bluetooth Webcam Management GPIO HETEROGENEOUS PLATFORMS SHARED MEMORY ILY S A E LE B A L SCA Homogeneous Heterogeneous Performance ADAPTATION Power Flexibility HOMOGENEOUS PLATFORM DISTRIBUTED MEMORY Programmability Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
4 ARCHITECTURES IN THE MARKET SCC (Single Chip Cloud Computer) Intel Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
5 Context Array of tiny scalar ISP w. private RAM Interconnected through a NoC Adaptive DVFS Dynamic Task Mapping Domain-specific Tele Load balancing General purpose Multi OS com média Institute for Information Processing Technology (ITIV) Telecom CPU DSP DSP Prof. Dr.-Ing. K. D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork RAM I/O Multimedia Centralized control (GPP) Specialized ISPs, ASIPs Static task mapping Bus-like interconnect Centralized control (OS) Symmetric multicore Dynamic load balancing High-freq. memory & Bus Heterogeneous Homogeneous Homogeneous Centralized Distributed Centralized Static Adaptive Dynamic Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
6 SHOP Self-adaptive Homogeneous Platform Distributed Memory Message Passing (State of the art) Network Processing Unit NPU Router RISC RAM Power Management Task Migration Task N... Task Task RTOS Frequency Scaling ADAPTATION Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 6 /
7 SHOP OS Operating System Tiny, preemptive OS with dynamic loader Scheduler based on thread priorities Features: Communication between local and remote threads Use of RAW/UDP/TCP IP connection to ensure reliable communication Possible use of a self-adaptive RAW/UDP/TCP IP protocol Frequency scaling DMA support Routing Table (Master node) NPU Task Ports , Step : Registering Tasks Step : Requesting Task Location Step : Receiving Task Location Step : Establishing the Link Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 7 /
8 SHOP OS Operating System Routing Table (Master node) Task Migration NPU Task Ports , Step : T is selected to be migrated : Stork Sending Prof. Dr.-Ing. K. D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer.step nat. W. information to the sender tasks Step : Stopping sending packets to T Step : Sending information to the master node Step : Removing T entry from routing table Step 6: Migrating T to NPU Step 7: Sending new position to the master node Step 8: Registering T in the routing table Step 9: Updating T position in the sender tasks Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 8 /
9 SHOP OS Operating System RAW/UDP/TCP protocol Protocol Speed QoS Raw High No UDP/IP Medium No TCP/IP Low Yes Packet FaultLost Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 9 /
10 SHOP OS Processor software hardware Applications Router software hardware FPGA SystemC Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 0/
11 Platforms for validation HS-Scale (Nicolas Saint Jean, LIRMM, France) Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
12 Platforms for validation System C (Nicolas Hebert, LIRMM, France) Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
13 METRICS AND VALIDATION FLOW OFF-LINE (DESIGN TIME) APPLICATION ANSI C CODE PROFILING SPLIT APPLICATION ANSI C CODE + API INITIAL STATIC MAPPING SPLIT APPLICATION ANSI C CODE + API INITIAL STATIC MAPPING TASK GRAPH WITH PROCESSING COST Institute for Information Processing Technology (ITIV) PROCESSING REQUIREMENTS Prof. Dr.-Ing.SNAPSHOT K. D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork PERFORMANCE MEASUREMENT PERFORMANCE MEASUREMENT NEW STATIC MAPPING NEW DYNAMIC MAPPING SPLITTING ANSI C CODE + API SPLIT APPLICATION PERFORMANCE SMi PERFORMANCE DMI ON-LINE (RUN-TIME) Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
14 ADAPTIVE SYSTEM Action Monitoring O = f(l) SYSTEM The user feeds the O=f(l) law, the system then handles decision (action) making accordingly Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
15 HOW TO MANAGE ADAPTABILITY? Events and Maps Events represent perturbations - decisions taken based on history - stored in DRET: Distributed Raw Event Table The set of all tiles states represents the map of the MPSoC - temperature map - power consumption map - working/not working map Maps are stored in AIM: Architecture Instant Map MONITORING INSTRUMENTED SYSTEM SENSORS DRET Network Processing Unit DRET LEVEL DIAGNOSIS AIM LEVEL SENSORS DIAGNOSIS ONLINE APPLICATION REMAPPING Three levels of reactiveness LEVEL AIM Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
16 HOW TO MANAGE ADAPTABILITY? CLUSTER CLUSTER AIM AIM Technology (ITIV) Institute for Information Processing AIM CLUSTER AIM CLUSTER Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 6/
17 DRET DISTRIBUTED RAW EVENT TABLE Create Table Create Table Rows Columns Clock cycles Rows Insert Dump Table Columns 000 Clock cycles Get First Row Columns Rows Delete Table Columns Sort Table Rows Columns Clock cycles Rows Columns Clock Rows Clock Prof. Dr.-Ing. K. D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork cycles cycles Insert 00 Clock cycles Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 7/
18 EXPERIMENTS MONITORING Action O = f(l) Monitoring ACTUAL CPU WORKLOAD FIFO USAGE FREQUENCY FUTURE TEMPERATURE NOC USAGE Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 8/
19 EXPERIMENTS DIAGNOSIS Action 0 N O = f(l) Monitoring N E W 8 9 E W 6 7 Institute for Information Processing S Technology (ITIV) S 0 N N E W 9 8 E W 7 S 0 6 S Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 9/
20 EXPERIMENTS CASE STUDY (MJPEG DECODER) Sender T APPLICATION ANSI C CODE T PROFILING IVLC T TASK GRAPH WITH Prof. Dr.-Ing. K. PROCESSING D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork COST PROCESSING REQUIREMENTS SNAPSHOT T IQUANT T T SPLITTING ANSI C CODE + API T 0 SPLIT APPLICATION IDCT T Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk 0/
21 EXPERIMENTS ACTION MJPEG MULTI TASK PROCESSOR (600MHz) MJPEG MULTI TASK PROCESSOR (600MHz) x 0 Action MJPEG MULTI TASK PROCESSOR (600MHz) Technology Institute for Information Processing (ITIV) Prof. Dr.-Ing. K. D. Müller-Glaser. Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork FIFO Filling (Number of Positions) Throughput (MB/s) NUMBER OF(CLOCK PACKETS MIGRATION TIME CYCLES) THROUGHPUT (MB/s) O = f(l) Monitoring TASK SIZE (KB) 0 0 TIME (ms) TIME (ms) 0 DYNAMIC MAPPING BUFFER FILLING DYNAMIC MAPPING MIGRATION TRIGGER MIGRATION MIGRATIONCOST COST POINT 8MIGRATION TIME (ms) 0 0 Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
22 PERSPECTIVES & CONCLUSIONS Investigate the use of a self-adaptive RAW/UDP/TCP IP protocol Develop different monitoring systems TEMPERATURE CPU FIFO USAGE WORKLOAD Explore different task migration techniques Critical applications to perform the experiments VOICE ENCODING MSA VIDEO (MULTIPLE SEQUENCE ALIGNMENT) ENCODING DIALIGN ALGORITHM PROTEIN ENERGY INTERACTION Dr. Gabriel Marchesan Almeida - Laboratory of Informatics, Robotics and Microelectronics of Montpellier, France November st 0 - Invited Talk /
23 Thank you for your attention! Dr. Gabriel Marchesan Almeida Institute of Information Processing Technology (ITIV)
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