Energiatehokas laskenta Ubi-sovelluksissa

Transcription

1 Energiatehokas laskenta Ubi-sovelluksissa Jarmo Takala Tampereen teknillinen yliopisto Tietokonetekniikan laitos

2 Energy-Efficiency Comparison: VGA 30 frames/s, 512kbit/s Software Power needs (mw) of MPEG-4 and H.264 decoders (130nm 1V CMOS) MPEG-4 H.264 ARM7 (720T) ARM9 (926EJ-S) ARM10 (1022E) ARM11 (1136J-S) Hardware Power needs (mw) of MPEG-4 hardware encoder and decoders (130nm 1V CMOS) kgates MPEG-4 Power (mw) Decoder Encoder

3 Relative demands of video decoder implementations Data for H.264 decoding (Hantro Products 2007) HW: Hantro 7170 hardware decoder DSP platform: averages of solutions from ARC, Tensilica, CEVA, and TI SW: ARM performance for Hantro s 6100 software decoder Either flexibility or power consumption compromised

4 Hardware/Software Interface Peripheral Device task switch T1 T2 interrupt & task switch T1 start dct HWDCT executing dct ready Instruction Set Extension (ISE) ISE dct mul b No support on HLL compilers!

5 Overheads Example of overheads, MPEG-4 : 30/s 36k/s Up-to 216k/s If fine grained accelerators at block level with 300 cycle invocation overhead = at least ~70MHz for HW/SW interfacing (probably underestimated)

6 Challenge: Support Multiple Video Standards " Ultimately, the description of the decoder should be received as reconfiguration of executable code " RVC: Reconfigurable Video Coding

7 Energy-Efficient Computing in Ubicom Systems, ECUUS ( ) " Research partners Tampere University of Technology (TUT) Prof. Jarmo Takala / Department of Computer Systems University of Oulu (UO) Prof. Olli Silvén / Information Processing Laboratory Åbo Akademi University (ÅAU) Prof. Johan Lilius / Department on Information Technologies " Industry Partners: Elektrobit Finnish Navy Research Center On2 (Hantro) Nokia Teleste Texas Instruments, France

8 ÅAU: Canals Streaming Language " Aims to Provide intuitive visual and textual syntax Modular scalable designs " Powerful dataflow descriptions " Scheduling algorithms can be described in language itself " Automatic bit stream parsing Automatic deserialization of data in network inputs

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10 Canals Demonstration

11 UO: Accelerator Scheduling " Exploit a-priori information on scheduling " Example: btype token in MPEG-4 SP consists of 12 bits data -> 4096 different values Exploration reveals that 5 different operation sequences occur " Quasi-static scheduling Dynamic schedule consisting of static portions " Collaboration with EPFL, Switzerland

12 Permutation Flow-shop Scheduling Accelerator contributions to RVC demo in EPFL

13 TUT: TTA-based Codesign Environment (TCE) " Design methodology and tools for tailoring transport triggered architecture " Exploit instruction level parallelism " Allow easy inclusion of user defined special function units " Can be used for developing programmable accelerators " Implementations on ASIC or FPGA " The developed tools released in public domain: tce.cs.tut.fi/

14 TCE Design Environment, Functionality (C/C++) LLVM frontend Resource Constraints Modify Resources Map & Schedule Simulate FU models (C, HDL) Cost Functions (area, power, speed) Parametric Compiler Parallel Object Code Code Compression TTA Processor Parametric Processor Generator HDL Code

15 VLC Decoder Implementations: the most popular standards supported Normalized throughput (CABAC) Normalized throughput/gate Notes Microprocessor 1 1 DSP 1 1 ASIP tailored instructions ASP (TTA) (est.) tailored data paths HW accelerator largest silicon area Only the hardware accelerator is not programmable [Rouvinen*, Jääskeläinen**, Rintaluoma***, Silvén*, and Takala** *University of Oulu **Tampere University of Technology ***ON2 Technologies (Hantro), Oulu]

16 Other Demonstrators Transform accelerator for RVC Supports all discrete transforms and transform sizes defined in H.264, VC-1, and MPEG-4 MIMO receivers FFT on TTA List-Sphere decoding on TTA Viterbi decoding on TTA Turbo decoding on TTA QR decomposition on TTA A TTA-based GPU Collaboration with Univ. Ray Juan Carlos, Madrid Standalone OpenGL implementation

17 References Boutellier J, Bhattacharyya SS & Silvén O (2009) A low-overhead scheduling methodology for fine-grained acceleration of signal processing systems. Journal of Signal Processing Systems (to appear). Boutellier J, Lucarz C, Lafond S, Martin Gomez V & Mattavelli M (2009) Quasi-static scheduling of CAL actor networks for Reconfigurable Video Coding. Journal of Signal Processing Systems (to appear). Boutellier J, Cevrero A, Brisk P & Ienne P (2009) Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. Proc. IEEE Workshop on Signal Processing Systems, Tampere, Finland. Salmela P, Antikainen J, Pitkänen T, Silvén O & Takala J (2009) 3G Long Term Evolution Baseband Processing with Application-Specific Processors. Int. J. Digital Multimedia Broadcasting. Salmela P, Sorokin H & Takala J (2008) A Programmable Max-Log-MAP Turbo Decoder Implementation. VLSI Design. Jääskeläinen P, Kellomäki P, Takala J, Kultala H & Lepistö M (2008) Reducing Context Switch Overhead with Compiler-Assisted Threading. Proc. 3rd Int. Workshop Embedded Software Optimization, Shanghai, China.