Accelerating the next technology revolution THIRD EDITION 2008 REPORT. In this edition: Sustaining Business with Smart Partnering

Transcription

1 NEWS THIRD EDITION report Accelerating the next technology revolution REPORT In this edition: Sustaining Business with Smart Partnering

2 Moving the Industry Forward SEMATECH Knowledge Series (SKS) meetings Lithography 2008 International Symposium on Extreme Ultraviolet Lithography 28 September 2 October 2008; Lake Tahoe, California SEMATECH Advanced Mask Cleaning Workshop 06 October 2008; Monterey, California Advanced Technologies Advanced Gate Stack Symposium 29 September 1 October; Austin, Texas 3D Design/TestWorkshop 13 November 2008; San Jose, California 3D Architectures for Semiconductor Integration and Packaging November; Burlingame, California Manufacturing AEC/APC Symposia 4-8 October 2008; AEC/APC Symposium XX North America, Salt Lake City, Utah November, 2008; AEC/APC Asia, Hsin Chu, Taiwan ISMI Manufacturing Week October 2008; Austin, Texas Other Industry-wide Events International Technology Roadmap for Semiconductors (ITRS) Conferences Winter Conference, December 2008 SEMATECH and ISMI Symposium, Japan October, 2008; Tokyo, Japan Workshop on Maskless Lithography 14 December 2008; San Francisco, California Contents 4 UMC Joins SEMATECH Research Consortium 6 SEMATECH Reports Major Advances in EUV Resist Development 7 Look Who s Talking - An insight into SEMATECH and ISMI presentations 8 Reports from the 5th International Symposium on Immersion Lithography 10 Accelerating Productivity - ISMI s 450mm Program 11 Sustaining Business with Smart Partnering 12 Mark his Words - Mark Sheedy 14 SEMATECH Reports Resist and Mask Progress at EUVL Symposium 16 SEMATECH Research on Reliability High-k Metal Gates Recognized 2 SEMATECH TECH REPORT

3 In this Edition... A note from Michael R. Polcari, President and CEO, SEMATECH Over the last half-century the semiconductor industry has been remarkably successful in making chips that are faster, better, cheaper and smaller. As a result, our world is smaller people around the globe are connected in ways we never even imagined a few decades ago. Our success is due to innovation: the innovation of our scientists and engineers who explore new technologies and make critical breakthroughs; the innovation of our manufacturing experts who solve productivity and yield challenges; and the innovation and entrepreneurial spirit of our business leaders who bring our products and services to market. Our Tech Report this quarter features several examples: You ll learn how SEMATECH engineers have partnered with researchers from resist manufacturers to reach a major milestone in the development of EUV lithography infrastructure chemically amplified resist platforms that support 22 nm half-pitch resolution and why a SEMATECH-authored paper on the reliability of nmosfets with lanthanum-doped HfO2 dielectrics has won the Best Paper award at the International Conference on Solid State Devices and Materials. You ll also find out how the International SEMATECH Manufacturing Initiative (ISMI) and equipment experts are actively testing prototype automation and equipment interfaces in ISMI s Interoperability Test Bed lab, as part of the consortium s 450mm program aimed at developing 450mm industry capability to increase productivity and reduce costs. And you ll meet Mark Sheedy, SEMATECH s Business Development Director, whose leadership exemplifies what it takes to build global relationships and partnerships with leading chipmakers and equipment and materials manufacturers. Our success is also due to connections. The thread that ties these innovative achievements together is collaboration smart partnerships that help reduce cost and risk, foster innovation, and increase productivity. Each of our Tech Report articles illustrates effective partnering at work, but several in particular illustrate the value of consortia and of industry-wide conferences in sharing knowledge and forging consensus: You ll learn about UMC s recent decision to join SEMATECH, and the mutual benefits that UMC and the SEMATECH membership stand to gain from this new and exciting partnership. You ll read new reports on the state of EUV and 193nm immersion lithography and progress on top critical issues, as presented at recent symposia organized by SEMATECH and our international partners. Innovation and connections these are the keys to staying productive and profitable in a challenging economy and a changing industry. THIRD EDITION

4 UMC Joins SEMATECH Research Consortium Partnership to drive acceleration of semiconductor technology development SEMATECH and United Microelectronics Corporation (UMC), a leading global semiconductor foundry, have announced UMC s decision to join SEMATECH. The relationship will focus on research and development for exploratory technologies on 300 mm wafers, including 22 nm and beyond process generations. SEMATECH President and CEO Dr. Michael Polcari said, Our members join me in welcoming UMC to SEMATECH, and we look forward to their contributions and technical insight from their perspective as a global leader in 300 mm foundry services. UMC will be an important partner in accelerating the progress of R&D innovations into manufacturing solutions. Given SEMATECH s excellent progress in its advanced technology and manufacturing programs in Albany and Austin and with suppliers, universities, and research institutes around the world, strong synergies have been created to drive the cooperation with UMC. UMC is a natural partner for SEMATECH. In addition to large-scale 300 mm production for 90 nm and 65 nm foundry products, UMC is currently qualifying its 45 nm/40 nm technology and making good progress on 32 nm/28 nm technology. Partnering with SEMATECH is a win-win situation for both organizations, said Dr. Shih Wei Sun, CEO of UMC. The combination of UMC s 300 mm manufacturing experience and process technology expertise and SEMATECH s wealth of knowledge in the field of semiconductor R&D will help the industry better handle the challenges of migration to next generation processes. We are excited about SEMATECH s commitment to 300 mm exploratory research and development and look forward to passing the benefits of this technology relationship to our customers. 4 SEMATECH TECH REPORT

5 NEW MEMBER About United Microelectronics Corporation United Microelectronics Corporation (UMC) is a full service semiconductor wafer foundry that manufactures integrated circuits for fabless design companies, integrated device manufacturers, and system companies. It also provides a variety of services including intellectual property, IC design support, design verification, mask tooling, wafer fabrication, and testing. UMC s technology includes a wide range of advanced processes, such as 90 nanometer, 65-nanometer, embedded memories, and Mixed-Signal/RF CMOS. In 2007, UMC marked its 27th anniversary celebration with the opening of the company s 300mm R&D center, located at UMC s fab complex in Tainan Science Park, Taiwan. The facility will focus on R&D for advanced 45-, 32-nanometer and below technologies for 300mm manufacturing. Furthermore, UMC continues to develop resources for SoC designers including embedded memory macros, Mixed-Signal/RF CMOS processes, and other system integration technologies used for SoC designs. The company s products are used in communication devices including consumer electronics, computer, memory and others, while continuing to focus on manufacturing for high growth, large volume applications, including networking, telecommunications, Internet, multimedia, PCs, and graphics. Founded in 1980, UMC is based in Hsinchu City, Taiwan, and employs approximately 13,000 people worldwide with offices in Taiwan, Japan, Singapore, Europe, and the United States. THIRD EDITION

6 SEMATECH Reports Major Advances in EUV Resist Development SEMATECH engineers and resist suppliers demonstrate CAR platforms that support 22 nm introduction SEMATECH engineers, working closely with researchers from major resist suppliers, have demonstrated chemically amplified resist (CAR) platforms that support 22 nm half-pitch resolution and are close to resolving sub-20 nm half-pitch features. These significant advances are critical in advancing the infrastructure that will prepare extreme ultraviolet lithography (EUVL) for high volume manufacturing at the 22 nm half-pitch. Resist suppliers and SEMATECH evaluated resist platforms with results demonstrating 22 nm half-pitch resolution, favorable photospeed (15 mj/ cm2), and line width roughness (LWR) of 5-6 nm. Although LWR is still higher than the International Technology Roadmap for Semiconductors specification, it is expected that resist post-processing and etch processes are likely to reduce LWR to a value that is acceptable on the device level for early adopters in DRAM and/or Flash applications. These results mark a cornerstone in the development of EUV lithography. They represent the first real 22 nm resist data, building confidence for EUV as a viable technology for 22 nm half-pitch lithography, said John Warlaumont, Vice President of Advanced Technology at SEMATECH. Partnering with resist suppliers to accelerate resist cycles of learning has been critical to bringing EUV resist readiness to this point, where EUV resists can now support 22 nm half-pitch imaging. The combination of SEMATECH and resist supplier expertise has been an indispensable asset in conducting this important advanced research. John Warlaumont, Vice President of Advanced Technology Over the past year, significant advances in EUV resists have been enabled by SEMATECH s EUV Resist Test Center (RTC) in Albany, NY, through its two micro-exposure tools (METs) at the University at Albany s College of Nanoscale Science and Engineering and the University of California at Berkeley. SEMATECH s METs have been critical in helping the industry break the 35 nm half-pitch resolution barrier in Through SEMATECH s EUV resist development program, engineers and resist suppliers subsequently made significant progress to improve resist resolution down to the nm half-pitch; now they have demonstrated 22 nm half-pitch resolution. Chawon Koh, SEMATECH s EUV resist process engineer and resist expert leading the joint evaluation of resist platforms with resist suppliers, commented, This achievement was deemed to be impossible by leading resist experts only a few years ago. Resist suppliers have made excellent progress in improving EUV resist resolution, thanks to access to the METs, which provide the highest resolution available worldwide among EUV optical imaging systems. The focus of SEMATECH s EUV resist development program is to engineer current CAR platforms to realize 22 nm high-pitch introduction and provide a fundamental understanding of EUV resist exposure mechanisms to develop new platforms, said Stefan Wurm, EUV Program Manager at SEMATECH. We believe this two-pronged approach will drive resist development to the highest level and support EUVL introduction. 22 nm hp resist pattern 6 SEMATECH TECH REPORT

7 Look Who s Talking An insight into SEMATECH and ISMI presentations Nikkei Microdevices 450 mm Seminar - Tokyo, Japan October 14 Scott Kramer, Vice President of Manufacturing Technology, will speak on ISMI s comprehensive strategy to implement 450 mm wafers. ISSM Conference - Tokyo, Japan October Ben Bunday, Project Manager, CD Metrology, will be presenting Phenomenology of ArF Photoresist Shrinkage Trends, which focuses on ArF and iarf photoresist shrinkage. 4th Annual ISMI/SEMATECH Symposium - Tokyo, Japan October 30 Mike Polcari, President and Chief Executive Officer, will provide a high-level briefing on SEMATECH s efforts, in cooperation with its global members and partners, to tackle major technology development challenges as the consortium pushes even further into the nanotechnology realm to find new manufacturable and affordable approaches to patterning, materials, device structures, and interconnections. Scott Kramer, Vice President of Manufacturing Technology, will explain ISMI s productivity improvement strategy, including projects in equipment productivity, continuous improvement, next generation fabs, benchmarking, and resource conservation, all aimed at cost reduction and productivity improvement in today s and tomorrow s factories. Scott Kramer will also outline ISMI s projects and priorities in the critical areas of resource conservation, climate change, sustainability, chemical management, and regulatory initiatives and describe ISMI s activities to ensure long-term sustainability of manufacturing operations. Joe Draina, Director, ISMI, will outline ISMI s ongoing emphasis on hardware and software development that will enable new capabilities in 300 mm equipment and factory productivity and significant reductions in cost and cycle time. Joe Draina will also provide an update on ISMI s 450 mm program, which is currently aimed at building infrastructure in silicon wafer readiness and factory integration guidelines and standards. John Warlaumont, Vice President of Advanced Technology, will outline the near-term and strategic directions being explored by SEMATECH in advanced technology. Raj Jammy, Vice President of Emerging Technology, will present an overview of SEMATECH s technical programs in functional materials and novel structures at the nanoscale, which are key elements not only for future scaling in both logic and memory, but also for a number of emerging and alternative technology applications that may provide additional pathways for increased functionality. Global Environmental Symposium - Tokyo, Japan December 14 ISMI s Environment, Safety, and Health technology manager, James Beasley, will explore ISMI s supply chain environmental management efforts and expectations to suppliers for resource conservation in semiconductor manufacturing. THIRD EDITION

8 Reports from the 5th International Symposium on Immersion Lithography Technologists reveal results on 193 nm high-index immersion lithography and other extensions to optical lithography At the 5th International Symposium on Immersion Lithography, September 22-25, lithography technologists and engineers gathered to discuss progress on 193 nm high index immersion lithography and other extensions to optical lithography and to build consensus on how the industry will address emerging critical issues. The symposium was organized by Selete and SEMATECH in cooperation with IMEC. Immersion lithography extensions provide opportunities for patterning solutions for the 32 nm, 22 nm, and perhaps even the 16 nm half-pitch nodes. These solutions are not automatic or even guaranteed and will require research and development to become reality. Bryan Rice, SEMATECH s Lithography director, said, This year s conference showed great results from immersion lithography in every field from high index immersion and double patterning to fundamental resist enhancements and manufacturing readiness. Immersion has gone from being a new idea to the workhorse technology in just five years. I doubt we will ever see such a rapid adoption of a lithography technology again. Key results outlined at the symposium, and SEMATECH s contributions to them, include the following: Double Patterning Double patterning is being used in high volume manufacturing right now. Processes for 45 nm and 3x nm are in various stages of completion at a number of semiconductor manufacturers. The industry has chosen double patterning because it is available and, although more expensive than single exposure, it is still affordable. SEMATECH s fundamental work on defectivity and fluid modeling has played an important role in enabling immersion double patterning. 22 nm Double Patterning Progress is being made towards the 22 nm node. While more difficult, 22 nm patterning feasibility has been demonstrated. SEMATECH will support the extendibility of 22 nm through its extensive mask infrastructure development program by working to reduce mask costs, improve mask metrology, and drive overlay capability to meet the demanding 22 nm specifications. Process Control Process control, a recurring theme throughout the symposium, is the greatest challenge for 22 nm patterning and beyond. SEMATECH and ISMI are aware of the need for improved process control in all potential future lithography technologies. Together, they are pursuing metrology improvement strategies to meet future overlay, CD control, and defect inspection requirements for optical lithography. 8 SEMATECH TECH REPORT

9 High Index Immersion SEMATECH has led the world effort in high index immersion materials by supporting lens, fluid, and resist research. Schott Lithotec showed high index lens materials results for lutetium aluminum garnet (LuAG) with an absorbance of 0.035/cm, including surface effects and an estimated 0.025/ cm in the bulk a factor of 4 improvement since last year s symposium. SEMATECH showed LuAG imaging results for the 30 nm half-pitch with interference lithography. SEMATECH-sponsored researchers at Cornell, Columbia, MIT, and DuPont showed high index fluid results from nanocomposite materials made by adding HfO2 nanoparticles to water or decalin. The nanoparticles created had size distributions averaging 1 nm in diameter. The champion aqueous solution achieved 70 weight percent loading, equivalent to 19 volume percent loading, with a 1.59 index of refraction at 193 nm compared to 1.44 for pure water. The champion organic solution achieved over 5 volume percent loading and an estimated 1.7 index of refraction at 193 nm. The research indicates that a nanocomposite high index fluid with an index of refraction greater than 1.72 is feasible. High Index Critical Review SEMATECH sponsored a meeting of the semiconductor scanner and material suppliers to discuss the status of high index immersion. The audience consensus was that technical progress was slow but did, in fact, indicate the feasibility of high index immersion. With promising results for high index fluid, most attendees conceded the feasibility of NAs exceeding A logical insertion point for high index immersion was suggested at the 22 nm or 16 nm half-pitch in combination with double patterning, which provides a good backup for EUV. Business concerns the lack of a market for a tool, issues about the timing for insertion, and the lack of sufficient funding for materials research outweighed the technical feasibility of a high index solution. The meeting resulted in consensus that high index will not be pursued because of economic and timing issues. Accordingly, researchers are suspending further development of high index immersion. This symposium is the last of the series, given the significant progress of immersion lithography throughout the industry. Much of the double patterning work has progressed beyond the pre-competitive phase and therefore is no longer suitable for a symposium. High index immersion is not seen as a potential lithography solution, and the remaining topics of resist advancement, nanoimprint, and maskless will be more appropriately addressed in workshop settings or in conjunction with other, more broadly scoped symposia. The Immersion Symposium series represents a great success in the history of SEMATECH-sponsored conferences as the technology has evolved from tabletop experiments to fully adopted high volume manufacturing over the past half dozen years. Although the symposia are over, SEMATECH will continue to enable advancements in multiple exposure lithography and extensions to 193 nm immersion through sponsored research and joint development with suppliers. THIRD EDITION

10 Accelerating Productivity Interoperability Test Bed providing critical inputs to accelerate the development of 450mm Factory Integration standards ISMI s 450 mm Program is now well underway at SEMATECH s Austin, Texas, facility. A major focus of the 450 mm wafer development effort is the Interoperability Test Bed (ITB) for interoperability testing of prototype automation and equipment interfaces. Lab space has been allocated and prepared, and prototype wafer carriers, handling robotics, and equipment loadports have been installed. ISMI plans on expanding the lab space, with an eventual move into cleanroom space in A 450 mm ITB Users Group, established this year, is comprised of multiple suppliers working together on the test bed and on early infrastructure challenges associated with it. Additionally, ISMI has agreed to work with Japan s Interoperability Test Group to combine the strengths of both organizations to focus on standards related to 450 mm carriers, loadports, equipment front-end modules (EFEMs), and automated material handling systems (AMHS). Both groups will provide test reports to accelerate critical standards decisions and enable data-based 450 mm standardization. thicknesses to test the implications of wafer thickness on wafer carrier design. To date, ~150,000 wafer transfers have been completed between prototype carriers and robots at 10 mm pitch. ISMI s 450 mm Program is dedicated to moving ahead with 450 mm industry capability to increase productivity and decrease costs. The goal is to establish a 450 mm tool demonstration line to support member stakeholder plans for pilot lines by Currently, ISMI s focus is on evaluating factory integration equipment prototypes and providing timely, quantitative inputs to 450 mm standards development efforts. To prevent operational gaps, the 450 mm standards are being developed in a rigorous, data-driven manner. For example, ITB engineers are working to validate the wafer pitch target of 10 mm and are also working with polycrystalline wafers of varying physical 10 SEMATECH TECH REPORT

11 Sustaining Business with Smart Partnering The recent economic downturn precipitated by the subprime mortgage crisis, rising oil prices, and a weaker dollar has resulted in skyrocketing costs and has seriously impacted priorities for R&D investments, which, in turn, has focused attention on new models for R&D investment. Companies around the world face a compelling need for balance between the industry s rapid pace of technology development, driven by Moore s Law, and the demands of running a profitable business in today s economic climate. With R&D costs escalating out of control (semiconductor R&D costs are expected to reach $49.2 billion in 2008 and double by 2012), chip makers are forming technology alliances to offset R&D costs and meet the need for complementary specialized skills to generate new technologies. As a result, some IC makers are abandoning the in-house R&D model and relying on strategic partnerships for the migration of technology. The advantages of shared R&D models are clear: minimizing the cost of developing new technologies by eliminating unnecessary duplication of research efforts; sharing the risks; gaining immediate access to new technologies, new markets and cheap production sources; and making otherwise big and complex research projects possible. In addition to such alliances and partnerships, the industry also comes together in technology conferences, symposia, and workshops, which have burgeoned over the last several years, allowing manufacturers, suppliers, developers, academia, and consortia to share knowledge and thus make the most informed, cost-effective R&D decisions possible. Especially in today s economic climate, companies can t afford to make mistakes in their R&D investments; collaboration is the key. With smart partnering, companies can be more productive and more profitable. Making the right R&D decisions is more critical than ever. To ensure that they hit the key milestones on their technology roadmaps, chip makers are collaborating with thoughtleaders in their particular technology sectors. To preserve their leadership and competitiveness, chip makers are outsourcing more of their R&D requirements to consortia, silicon foundries, and third-party suppliers. THIRD EDITION

12 Mark his Words Mark Sheedy, SEMATECH s Business Development Director and World Traveler shares his thoughts about the semiconductor market and SEMATECH s plans for the future. Jet lag is a tough part of Mark Sheedy s job, but it s the necessary and inevitable price for establishing global relationships and, eventually, partnerships with leading chip makers and suppliers. As SEMATECH s Business Development Director, Mark plays an integral role in developing and implementing business development strategies, building broad-base awareness of SEMATECH s collaborative program and membership opportunities, and closing on new smart partnerships. You ve been spearheading new member and program/ associate member recruitment efforts for awhile. Can you give an example of a recent successful partnership? While all of the partnerships we have in place are important to SEMATECH, I believe our partnership with Tokyo Electron is noteworthy. We have a long history of collaborative R&D activities with Tokyo Electron, including joint SiGe/ Ge Epi development and Tokyo Electron s relatively recent membership in SEMATECH s 3D interconnect program. We have an excellent relationship with TEL, and hope to build on the success of these programs and continue to expand our relationship in the future. It is not always easy to recognize and take advantage of good partnering opportunities when they arise. How do you identify and target companies that are willing to get involved in successful partnerships? SEMATECH s established brand name and long history of good relationships with the various companies within the industry have been very helpful in this regard. Since our research is member driven, and our members make up over 50% of the world semiconductor market, the relevance of our research portfolio is well known in the industry. Consequently, engaging new partners to join our consortia provides good leverage opportunities for all participating companies. In today s economic climate, what are some of the challenges facing the chip R&D market? What is SEMATECH doing to address these issues? The key R&D challenge facing the semiconductor market is the gap in R&D funding if we re to continue to realize the historic productivity described by Moore s Law. SEMATECH is addressing this issue by leveraging the value of our member driven consortia model. The member companies of SEMATECH have selected a portfolio of research activities that are critical to solving the technical and cost challenges facing the industry. By managing programs that will help decide which technologies will work and equally important, which technologies will not work - SEMATECH maximizes member/ partner return on investment. 12 SEMATECH TECH REPORT

13 What are the key components that chipmakers consider before deciding to join a consortium or collaborate through cooperative R&D? R&D in the semiconductor and emerging technology markets is too large for any one company or region to do on its own, so key determiners for chipmakers are leverage and return on investment. Chipmakers want to know that they are receiving maximum leverage and an excellent rate of return on their investment. By providing a unique forum to leverage both the financial and intellectual resources of all participating parties, a consortial model like SEMATECH s provides important assistance to its members/ partners in identifying their common problems, and pooling their resources to implement the right cooperative R&D programs to find effective, timely solutions. Do you believe collaborating or joining a consortium is a successful strategy for market share growth or is its value more in expense reduction? Each member calculates their return on investment differently. For some members, consortia participation provides early learning and improves their product time to market, which in turn helps them grow their market share. For others, ROI comes through cost avoidance and expense savings. For most members, it s a blend of both. What are the competitive values SEMATECH brings to the table? SEMATECH provides a unique forum for our members and partners to leverage both technical and economic risk. Here s how we work: Our program portfolio is broad encompassing emerging technology, advanced technology, and manufacturing productivity - and is member/partner driven. Our members and partners choose the programs SEMATECH works on, and actively participate in their execution and evaluation. Our broad global collaborative network bridges all sectors of our industry, including chipmakers, foundries, fabless companies, suppliers, universities, and government entities The chipmaker and foundry members participating in SEMATECH and ISMI represent over 50% of the world semiconductor market, which gives our research portfolio timely relevance in addressing the key technical and manufacturing challenges facing the industry. Our technical staff provides expertise that allows our members and partners to extend and expand their own internal R&D activities. Participation options are flexible to meet the varying needs of our customer base. That means that our members can choose to join one or more individual programs or have access to the entire scope of the consortium. For example, we recently provided an offering to equipment and material suppliers to join as associate members. Our programs are performed in an industrial setting in state-of-the-art facilities that leverage focused academic research. The ultimate goal is to move innovation to commercialization. Our programs are run on well tested baselines imbued with the background knowledge of our technical experts. All of these competitive advantages explain why our members and partners consistently report an annual return on investment of 5x. THIRD EDITION

14 SEMATECH Reports Resist and Mask Progress at EUVL Symposium SEMATECH engineers and the industry at large have made significant advances in moving forward the infrastructure that will prepare extreme ultraviolet lithography (EUVL) for cost-effective manufacturing, according to papers presented at the 2008 International EUVL Symposium in Lake Tahoe, California. At the seventh EUVL Symposium, an outstanding set of 52 technical papers and 106 posters covering all aspects of EUVL technology, reported excellent progress in many key areas. At the same time, presenters highlighted various technology, infrastructure, and business challenges that the industry needs to address to successfully insert EUVL into manufacturing at the 22 nm half-pitch node. The forum keynote addresses EUV Lithography s Future, by Dr. Harry Levinson of AMD, and Samsung s Lithography Strategy, from Dr. Woosung Han of Samsung emphasized that EUVL technology has transitioned from the research phase to the development phase, and is now focused on early device and yield learning and pre-production tooling to prepare EUVL for pilot line insertion in the timeframe. Experts reported, for the first time 45 nm node yielding fullfield SRAM s produced using EUV lithography. A presentation by a chip manufacturer illustrated how EUVL contact hole printing for 3X nm half-pitch nodes and line and space printing for 2X nm hp nodes are significantly more cost effective than competing technologies, in part because little or no optical proximity correction (OPC) is needed. Further data showing approximately 1 nm intrawafer critical dimension uniformity (CDU) for 35 nm hp 1:1 lines and spaces clearly demonstrate the excellent imaging performance of EUVL alpha tools. Critical progress has also been made in EUV sources. A fully integrated laser produced plasma (LPP) source collector module with effective mitigation of tin deposition and ion erosion was demonstrated with 3 to 4 W at intermediate focus (IF). Also, generated EUV power for discharge produced plasma (DPP) sources the type that currently is used in alpha tools has tripled to 500W. SEMATECH researchers and research partners highlighted the key role the consortium has played in achieving significant advances in EUV resists in papers presented at the symposium. Specifically, SEMATECH researchers have demonstrated 20 nm resolution images and 30 nm 1:1 contact hole images and have achieved feature resolution for both, as confirmed by cross-section scanning electron microscopy images. The resist technology research leading to these accomplishments has been enabled by SEMATECH s EUV Resist Test Center (RTC) at the College of Nanoscale Science and Engineering s (CNSE) Albany NanoTech Complex in Albany, NY, and by its micro-exposure tool (MET) located at the Berkley Advanced Light Source (ALS) Lab at University of California, Berkeley. Supported by SEMATECH s MET exposure capabilities, resist suppliers have been able to address the challenges of simultaneously meeting resolution, line edge roughness (LER), and sensitivity targets in a systematic way. Full field tool imaging, using conventional illumination, has demonstrated 28 nm half-pitch line and space resolution and 28 nm 1:1 contact hole resolution without using OPC. 14 SEMATECH TECH REPORT

15 Good progress has been made toward achieving resist resolution and sensitivity targets, with some improvement in line edge roughness, and now chip manufacturers are demonstrating post-exposure resist processes that lead to significantly reduced line edge roughness, said Stefan Wurm, EUVL Symposium chair and SEMATECH s associate director of Lithography. With the world s leading-edge exposure tool for EUV resists learning, SEMATECH continues to enable the development of high performance resists required to demonstrate EUV manufacturability to our member companies and the industry. Furthermore, SEMATECH also reported it has significantly reduced printable substrate defects with its development of a new and fast defect-removing cleans process. Combining a 6X faster two-hour defect smoothing process, this constitutes a major step forward in enabling cost efficient low-defect mask blank manufacturing solutions. EUV mask blanks are now commercially available with approximately 5 defects at 73 nm size. To achieve the pilot line target of eight defects at 18 nm, the industry will require more sensitive defect inspection tools for mask substrates and blanks. Lastly, SEMATECH s aerial imaging and inspection research tool (AIT) at the Berkeley ALS Lab demonstrated that it is capable of resolving 88 nm mask features (22 nm half-pitch on the wafer). It is the only tool, world-wide, that allows chip manufacturers to characterize mask defect in an aerial imaging mode at this high resolution. However, to support pilot line operation and EUVL transition into manufacturing, a commercial EUV aerial imaging tool will be required for patterned mask defect review. Given these significant advances, the EUVL Symposium Steering Committee identified at the conclusion of the conference three remaining focus areas that the industry needs to work on to enable EUVL manufacturing insertion: 1. Long-term source operation with 100 W at the IF and 5 megajoule per day 2. Availability of defect-free masks, throughout a mask lifecycle, and the need to address critical mask infrastructure tool gaps, specifically in the defect inspection and defect review area 3. Simultaneous resist resolution sensitivity and LER THIRD EDITION

16 SEMATECH Research on Reliability High-k Metal Gates Recognized SEMATECH engineers received best paper award at the 2008 International Conference on Solid State Devices and Materials in Japan SEMATECH has received the Solid State Devices and Materials (SSDM) Best Paper Award for its work on reliability of high-k metal gates. The paper was presented at the International Conference on Solid State Devices and Materials in September 2007 by Chang Yong Kang, research engineer in the Front End Processes (FEP) division of SEMATECH. The award ceremony took place on September 24 at the Tsukuba International Congress Center during the 2008 International Conference on Solid State Devices and Materials in Ibaraki, Japan. The paper, entitled nmosfet Reliability Improvement attributed to the Interfacial Dipole formed by La Incorporation in HfO2, was co-authored by Paul Kirsch, Dawei Heh, Chadwin Young, Gennadi Bersuker, Byoung Hun Lee, Prassana Sivasubramani, Seung Chul Song, Rino Choi and Raj Jammy of SEMATECH, and Daniel Lichtenwalner, Jesse Jur, and Angus Kingon of North Carolina State University. The paper investigates the reliability of nmosfets with lanthanumdoped HfO2 dielectrics, whose device performance and voltage threshold are suitable for future technology nodes applications. The best paper is selected each year by the attendees and the program committee. It gives me great pleasure to congratulate our engineers for this prestigious recognition of their success as they continue to address the challenges of integrating new materials and device structures for functionality, said Raj Jammy, vice president of materials and emerging technologies at SEMATECH. Quality work such as this paper - and those being presented by our technologists this year - is representative of SEMATECH s commitment to provide innovative and practical solutions for continued scaling of semiconductor technologies that can easily be incorporated in real-world manufacturing environments. SEMATECH has been an active contributor to SSDM conferences since SSDM is one of many industry forums it uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners. Subscribe to the SEMATECH Tech Report Keep up to date with the latest SEMATECH and ISMI industry news and information. To subscribe online, visit or complete the form below and fax to , attention Kristy Coulter, or mail it to us at: SEMATECH Tech Report Subscription 255 Fuller Rd, Suite 359 Albany, NY I would like to receive the Tech Report (please tick): mail Company...Contact Name... Address... City... State...Zip Code... Address SEMATECH TECH REPORT