COM 353 Microprocessors Lecture 3. Introduction to 8-bit Microprocessor Architecture and Operation. Prof. Dr. Halûk Gümüşkaya

Transcription

1 COM 353 Microprocessors Lecture 3 Prof. Dr. Halûk Gümüşkaya haluk.gumuskaya@gediz.edu.tr haluk@gumuskaya.com Introduction to 8-bit Microprocessor Architecture and Operation Computer Engineering Department Tuesday, October 23, 202. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 A Microprocessor Based System ROM RWM I Giriş (Temel) 3-durumlu buffer SİSTEM YOLU Çıkış (Temel) Latch, FF Programlanabilir Giriş/Çıkış Birimleri 8255, (8254) ,... A collection of addressable registers: Those registers reside within the microprocessor are internal registers, and those exist in the ROM, RWM, and I/O ports are external registers.

2 Typical Partial Set of System Bus Signals 3 Buses of a P-Based System Name Function Number Direction* A 3 A 0 Address bus 6, 20, 24, 32, 36 Output CPU Çip-üzeri yollar Mikroişlemcili Sistem D 63 D 0 Data bus 8, 6, 32, 64 Bidirectional Generalized read strobe Output Saklayıcılar Yerel Sistem Yolu Generalized write strobe Output IO/M Status (I/O or memory reference) Output MEMR Memory read strobe Output MEMW Memory write strobe Output IOR Input device read strobe Output ALU Hafıza I/O I/O IOW Output device write strobe Output RESET System reset out Output * Direction is specified with respect to the microprocessor. Harici Sistem Yolu Simple Input Port for a P-Based System Simple Output Port for a P-Based System Giriş Cihazı Latch Giriş Port'u 3-Durumlu Buffer Sistem Veri Yolu D 0 D Çıkış Cihazı Çıkış Port'u Latch Sistem Veri Yolu D 0 D E D m D m Veri Tutturma Darbesi Cihaz Seçme Lojiği Giriş Cihazı Seçme Darbesi A 0 A Cihaz Seçme Lojiği Çıkış Cihazı Seçme Darbesi A 0 A A n A n IO / M IO / M

3 Internal Architecture. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor Microprocessor Based System Genel Amaçlı Saklayıcılar R0 R R2 R3 ALU (Arithmetic Logic Unit). Control Unit 2. General Purpose Registers 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 Özel Amaçlı Saklayıcılar R3 SR (Status Register) IR (Instruction Register) IP (Instruction Pointer) SP (Stack Pointer) MAR (Memory Address Register) MBR (Memory Buffer Register) Kontrol Birimi Teknolojinin gelişmesiyle eklenen diğer donanım ve yazılım (FPU, hafıza yönetim birimi, cache,...) 3. Special Purpose Registers 4. Arithmetic Logic Unit 5. Other Special Units. Control Unit Simplified States of Control Unit Harici Veri Yolu Komut Saklayıcısı MBR IR Dahili Veri Yolu It controls and synchronizes all data transfers and transformations in the microprocessor system. Komut Okuma (Fetch) Komut mikroişlemcide Yürütme (Execute) Saat Komut Kod Çözücü Kontrol Birimi Dahili Saklayıcılara Kontrol Sinyalleri Bayraklar The output of the IR is decoded and used by the control unit to develop a sequence of microoperations (microistructions) and register transfers that execute the instruction. RESET Donanım sıfırlaması olmadığı sürece dur Komut yürütmesi biter Durma (Halt) Durma (HALT) Komutu RESET Harici Kontrol Girişleri Harici Kontrol Çıkışları

4 Fetch Decode Execute Cycles 2. General Purpose Registers Instruction Fetch Read an instruction from memory A (ACC) They are used for storage, arithmetic and logic operations (x86), and addressing purposes. Instruction Decode Operand Fetch Determine required operations Locate and obtain operand data Intel 8085 registers The registers are used and operated upon either singly or in pairs Execute Compute result value or status Result Store Write results to memory for later use X86 registers Next Instruction Determine next instruction 3. Special Purpose Registers 4. Arithmetic Logic Unit F (Flags) (8-bit status register, modified after an ALU operation) PC (Program Counter points to the next instruction to be executed in memory) MAR (Memory Address Register) MBR (Memory Buffer Register) 8085 registers SP (Stack Pointer) X86 registers A Temp. Reg AX BX CX DX DI SI BP SP Internal Bus ALU ALU Flags 8-bit ALU (8085) 6-bit ALU (8086/8088) Arithmetic and logic operations on one or two 8-bit, 6-bit (x86), and 32-bit (x86) operands are performed in this unit. Flags Halûk Gümüşkaya

5 FPU (Floating Point Unit) Cache Memory Memory Management Unit. 5. Other Special Units External Architecture Address Bus Data Bus Control Bus. Bus control 2. Bus status 3. Interrupts 4. Bus arbitration 5. Coprocessor signaling 6. Misc The pins on a CPU chip Address Bus: Common address bus widths are 6, 20, 32, and 64 Data Bus: Common widths are 8, 6, 32, and 64. Control Bus: The control pins regulate the flow and timing of data to and from the CPU and have other miscellaneous uses. Control pins can be roughly grouped into the following major categories: Bus Control Interrupts Bus Arbitration Coprocessor Signalling Status Miscellaneous Control Bus Bus Control: Mostly outputs from the CPU to the bus telling whether the CPU wants to read or write memory or do something else. The CPU uses these pins to control the rest of the system. Status: They show the status (i.e. bus operation, MEMR, IOW) of CPU. Interrupts: They are inputs from I/O devices to the CPU. Bus Arbitration: These pins regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time. Coprocessor Signalling: Some CPU chips are designed to operate with coprocessors such as floating point chips, graphics or other chips. Miscellaneous: CLK, XTAL, reset, power,

6 Internal Architecture of 8085A. Basic Microprocessor System Concepts INTR RST5.5 RST6.5 RST7.5 TRAP SID SOD 2. Microprocessor Architecture and Operation INTA Kesme Kontrol Seri I/O Kontrol 3. Intel 8085 Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O A ALU Geçici Reg. IR Komut Kod Çözücü B D H SP PC C E L 7. Programmable I/O and 8255 Bayraklar (F) X X2 CLK Üretimi Zamanlama ve Kontrol CLK OUT Kontrol Durum DMA RESET MAR MAR / MBR READY ALE S0 S IO/M HOLD HLDA RIN ROUT A 5 - A 8 Adres Yolu AD 7 - AD 0 Adres/Veri Yolu External Architecture of 8085A Multiplexing of Address/Data Pins of 8085A X 40 Vcc Adres Yolu X HOLD A 5 - A 0 6 RESET OUT SOD SID TRAP HLDA CLK (OUT) RESET IN READY Veri Yolu D 7 - D 0 8 RST IO/M Yol Kontrol RST S RST ALE INTR A INTA 30 ALE READY AD S0 AD AD2 AD3 AD4 AD5 AD6 AD7 VSS A5 A4 A3 A2 A A0 A9 A8 INTA Yol Durum IO/M S 0 S 8085A TRAP RST 7.5 RST 6.5 RST 5.5 INTR HOLD HLDA SID SOD RESET IN RESET OUT CLK X X2 Kesmeler Yol Hakemliği Çeşitli 8085A A 5 - A 8 A 5 - A 8 AD 7 - AD 0 A 7 - A 0 ALE 74LS373 C OE Adres Latch'ı D 7 - D 0 Adres Yolu A 5 - A 0 Veri Yolu (a) (b)

7 8085A Based System Machine Cycles and Timing Machine cycle: The fetching and execution of a single instruction. It consists of one more read/write operations (references) to memory or an I/O device. There are 7 different types of machine cycles in the 8085: Opcode fetch Memory read MEMR Memory write MEMW I/O Read IOR I/O Write IOW Interrupt acknowledge Bus idle Machine Cycle and State Information for the 8085A The Format of 8085 Instructions and Instruction Fetch Cycle 3 status signals generated at the beginning of each machine cycle identify each type and remain valid for the duration of the cycle. Bus Status Bus Control Machine Cycle IO/M S S0 INTA Opcode fetch 0 0 Memory read Memory write I/O read 0 0 I/O write 0 0 Interrupt Ack. 0 Bus idle DAD 0 0 Ack. of RST, TRAP HLT 3-state state 3-state The instructions consist of to 3 bytes. Therefore, instruction fetch is to 3 machine cycles The first machine cycle in an instruction cycle is always an OPCODE FETCH, and the 8-bits obtained during an OPCODE FETCH are always interpreted as the OP code of an instruction. The total number of machine cycles required varies from to 5, with no one instruction cycle containing more than 5 machine cycles. Opcode Opcode Operand Opcode Operand Operand2 (a) (b) (c) (a) -byte (b) 2-byte (c) 3-byte 8085A instructions.

8 Execution of STA and LDA Instructions STA (Store Accumulator Direct) transfers the contents of ACC to an external register (a memory register or a memory mapped output register) whose address is specified in the instruction. The opcode for STA is 32h. This register can be located anywhere in the 64 K memory space that the 8085 can directly address, 6-bits are required for the address. LDA (Load Accumulator Direct) does the reverse operation. It reads from an external register to the ACC. The opcode is 3Ah. Timing Values of 8085AH Microprocessor Processor Crystal MHz (f c ) State Time ns (T) ADD Instruction ( s) 8085AH AH AH AH ADDR ADDR + ADDR + 2 İşlem Kodu Düşük Adres Yüksek Adres byte byte 2 byte 3 STA veya LDA komutu 3-byte STA and LDA instructions Execution of STA and LDA Instructions Activities Associated with the T-States of 8085A Each machine cycle is divided by system clock into a number of state transitions, or T states, which correspond to the period between two negative going transition of that clock. T T 2 T w T 3 T 4 T 5 -T 6 A memory or I/O device address is placed on the address/data bus (AD7-AD0) and address bus (A5-A0). An address latch enable, ALE, pulse is generated to facilitate latching the low order address bits on AD7-AD0. Status information is placed on IO/M, S, and S0 to define the type of machine cycle. The halt flag is check. Ready and hold inputs are sampled. PC is incremented if machine cycle is part of an instruction fetch. In all machine cycles except BUS IDLE, one of the control strobes,, or INTAmakes a to 0 transition. (optional) This state is entered if the ready line is low. The states of the address, data and control signals remain the same as at the end of T2. An instruction byte or data byte is transfered to/from memory the microprocessor. The active control strobe makes a 0 to transition. The contents of instruction register (IR) are decoded. These states are used to complete the execution of some instructions.

9 T-States of LDA and STA Instructions Machine Cycles T-States. Opcode fetch 4 2. Memory read 3 3. Memory write 3 4. Memory write (STA) or read (LDA) 3 Total T-states for 4 machine cycles 3 For STA and LDA instructions, the number of T-states required for the execution is 3. If the 8085 is operating at a ns state time, the STA/LDA instruction cycle is executed in 4.23 S. Execution of IN and OUT Instruction IN InputPort IN reads the contents of an input device located at InputPort to the accumulator (ACC). The opcode for IN is DBh. InputPort is an 8-bit port address which is an operand in this instruction. 256 input ports are possible with this 8-bit port address. OUT OutputPort OUT does the reverse operation. It writes the contents of the ACC to the output port located at OutputPort. OutputPort is also an 8-bit address. This means 256 possible output ports. The opcode for OUT is D3h. ADDR ADDR + İşlem Kodu Port Adresi byte byte 2 IN veya OUT komutu 2-byte IN and OUT instructions Execution of IN and OUT Instruction. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255

10 System Memory System Memory Using Full Decoding The 8085 system has ROM and RWM memory modules, one input port (a simple 8-bit three-state buffer 74LS244) for reading switches, and one output port (74LS374) for driving a LED display. Veri Yolu D 7 - D 0 Use the memory system example given in the first lecture. 4K 8 EPROM ve 2K 8 RWM EPROM starts from 0000h, after EPROM RWM starts. 0000h 0FFFh 000h 7FFh 800h ROM RWM Boş 4K 2K 58K 0000h 0FFFh 000h 7FFh A 5 - A İlk 4K'lık bloğu seçer Üçüncü 2K'lık bloğu seçer A - A A 7 - A K ROM içinde bir hafıza hücresini seçer K RWM içinde bir hafıza hücresini seçer A 3 - A IO / M A 3 A 2 A A 5 A 4 74LS38 C Y0 B Y A Y2 Y3 Y4 G2A Y5 G2B Y6 G Y7 07FFh-0000h 0FFFh-0800h 7FFh-000h A - A 0 A 0 - A 0 2 A - A 0 D 7 - D 0 CE OE K x 8 EPROM A - A 0 D 7 - D 0 CS OE WE 66 2K x 8 RWM FFFFh Memory Map Address Bit Map A Simple Input Port at F0h (partial decoding) A Simple Output Port at Fh (partial decoding) D 7 D 7 D 0 IO / M 74LS244 Octal Buffer OE Cihaz Seçme Darbesi Anahtar bilgisi F8h S 7 S 0 D 7 D 0 IO / M A 7 A 6 A 5 A 4 A 0 CLK 74LS374 Octal FF OE D 0 Cihaz Seçme Darbesi Fh Adresindeki Çıkış Port'u A 7 A 6 A 5 A 4 F0h Adresindeki Giriş Port'u

11 Simple System Test Program at ROM Execution of In F0h Instruction IN F0h ; F0h adresli giriş port'undan oku ((ACC) <- (F0h)). CMA ; Okunan verinin bit'lerini tersle ((ACC) = (ACC)'). STA 000h ; ACC'yi RAM'ın 000h nolu hücresine yaz. LDA 000h ; RAM'ın 000h nolu hücresinden ACC'ye oku. OUT Fh ; Fh adresli çıkış port'una yaz ((ACC) -> (Fh)). HLT ; Program yürütmesini durdur. Program Assembly and Machine Code Address Machine Code Assembly Code 0000 DB F0 IN F0h F CMA STA 000h A 00 0 LDA 000h 0009 D3 F OUT Fh 000B 76 HLT ADRES 0000h 000h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh VERİ DBh F0h 2Fh 32h 00h 0h 3Ah 00h 0h D3h Fh 76h KOMUTLAR IN F0h CMA STA 000h LDA 000h OUT Fh HLT Execution of STA 000h Instruction Execution of Program in the 8085 Simulator

12 Assembly Program and its Machine Code Registers EPROM and RWM Input and Output Ports

13 Input and Output Address Spaces. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 IN PortNumber instruction Read from an input port located at PortNumber to the accumulator (ACC) [PortNumber]. PortNumber = 00h FFh: 256 input ports OUT PortNumber instruction Write the contents of ACC to an output port located at PortNumber. Again 256 output ports. I/O Decoding of Control Lines and Addresses The corresponding IO/M,, signals are generated when these instructions are executed by the CPU. These signals and some address lines are used by the decoding logic to access the I/O ports. I/O Address Spaces and Ports Since there are 2 different instructions for I/O access, two different address spaces exist for I/O operations. Totally 52 ports (8085). Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255

14 I/O Devices at Memory Address Space I/O devices are located at memory address space. Use memory related instructions (like LDA, STA) to access I/O devices. The I/O decoders monitor memory related control lines and addresses. An Input Device at a Memory Address To access an input port, use a memory access instruction, like LDA The input decoder monitors memory related control lines and addresses. An example: An input device is located at a memory address F000h. Use partial address decoding, use just 4 address lines from the address bus: A5, A4, A3, and A2. IO / M MEMR A 5 A 4 A 3 A 2 F000h Adresindeki Giriş Port'unu Seçme Darbesi An 8-input NAND gate is used as an input decoder. The input device is located at F000h. When IN F000h is executed by CPU, at the last machine cycle, F000h is placed onto the address bus, IO/M becomes 0. Finally is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the 3-state buffer of the input device is activated, and data at this device is read to ACC by CPU. An Output Device at a Memory Address Memory and I/O Address Spaces To write to an output port, use a memory access instruction, like STA. The output decoder monitors memory related control lines and addresses. An example: An output device is located at a memory address F00h. Use partial address decoding, use just 5 address lines from the address bus: A5, A4, A3, A2, and A0. IO / M MEMW A 5 A 4 A 3 A 2 A 0 F00h Adresindeki Çıkış Port'unu Seçme Darbesi An 8-input NAND gate is used as an output decoder. The output device is located at F00h. When OUT F00h is executed by CPU, at the last machine cycle, F00h is placed onto the address bus, IO/M becomes 0. Finally is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the input device is activated, and 8-bit data at ACC is written to the output device by CPU.

15 Why Memory Mapped I/O? Some processors may not have such separate IN and OUT instructions for I/O in their instruction set. Using IN and OUT, you can only read from or write to an I/O device. If you want to do some other operations, like OR, AND, ADD, ) directly on I/O devices, the memory mapped I/O technique can be used. If the number of I/O devices is larger than 52 (for 8085) use the memory mapped I/O.. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 Programmable I/O 8255 IC (a) and Logic Diagram (b) In our previous simple example, we had very simple I/O devices. In general microprocessor based systems, like PCs, have programmable I/O devices. These devices have programmable I/O ports. In addition to simple reading and writing data, they have also some build-in additional features, like timers/counters, interrupts, bit-addressable ports, Some examples: Basic and handshake parallel I/O (8255, 8256) Timer/counter (8253/8254) Interrupt controller (8259) Serial/parallel data communication (8250, 825, 8256) -bit data I/O (bit addressable) (8256) Keyboard/display interface (8279) Block data transfer between memory and external world (DMA) (8257) PA3 PA2 PA PA0 CS GND A A0 PC7 PC6 PC5 PC4 PC0 PC PC2 PC3 PB0 PB PB A (a) PA4 PA5 PA6 PA7 RESET D0 D D2 D3 D4 D5 D6 D7 VCC PB7 PB6 PB5 PB4 PB3 Programmable pripheral device Veri Yolu D 0 - D 7 CS A A0 PA PC 8255A RESET (b) PB 4 addresses are occupied in I/O space D 7 -D 0 Data Bus (bidirectional) PA 7 -PA 0 Port A PB 7 -PB 0 Port B PC 7 -PC 0 Port C CS Chip Select A 0, A Port Address Read Control Write Control RESET Reset Input VCC +5 Volt GND 0 Volt 8255A Chip and Port Select Signals CS A A Selected Port Port A 0 0 Port B 0 0 Port C 0 Control Register X X 8255A not selected

16 8255A at C0h and its Select Logic 8255 Control Word D D 7 - D 7 - D 0 0 PA PA = C0h A 7 A 6 A 5 CS A 4 A 3 A A A 2 A 0 A 0 IOR IOW PB PC CS = 0 Address Selected Port A 7 A 6 A 5 A 4 A 3 A A A = C0h = Ch = C2h = C3h PB = Ch PC = C2h PA PB PC Control Register BSR Modu (Bit Set/Reset) C Port'u üzerinde tek bit 0'lama ve 'leme yapılır A ve B port'ları etkilenmez D 7 D 6 D 5 D 4 D 3 D 2 D 2 D 0 0 / Kontrol Kelimesi I / O Modu Mod 0 Mod Mod 2 A, B ve C port'ları için basit giriş/çıkış A ve (veya) B port'ları için el sıkışmalı (handshake) çalışma C port'u el sıkışma sinyalleri için kullanılır A port'u için iki yönlü veri yolu Port B: Mod 0 veya de çalışır C port'unun bit'leri el sıkışma sinyalleri olarak kullanılır Kontrol Kelimesi D 7 D 6 D 5 D 4 D 3 D 2 D D 0 Grup B Port C (Düşük PC 3 - PC 0 ) = Giriş 0 = Çıkış Port B = Giriş 0 = Çıkış Mod Seçimi = Mod 0 0 = Mod Grup A Port C (Yüksek PC 7 - PC 4 ) = Giriş 0 = Çıkış Port A = Giriş 0 = Çıkış Mod Seçimi 00 = Mode 0 0 = Mod X = Mod 2 = I/O Modu 0 = BSR modu 8255 for the 8085 Based System I/O Operations Using 8255 Instead of using a 3-state buffer and a latch for I/O devices, this time use an 8255 for the 8085 based system example base address is F0h, that is the address of PA. PA will be used to read switches. PB (at Fh) will be used to drive the LED display. PC (at F2h) will not be used. Control register is at F3h. Control word = = 90h. IO / M A7 A6 A5 A4 D 0 - D 7 Veri Yolu A A0 8255A D 0 - D 7 PA CS A A0 PB D 7 D 0 S 7 S 0 RESET PC MVI A, 90h OUT F3h A simple I/O example using a 8255 located at F0h. ; (ACC) 90h, Load ACC with 90h (A: input, B: output) ; (F3) (ACC), write the contents of ACC (90h) to control register, 8255 is programmed. IN F0h; ; read switches (ACC) (F0h) OUT Fh ; drive LEDs (F) (ACC)

17 References Mikroişlemciler ve Bilgisayarlar, 3. Basım, H. Gümüşkaya, ALFA, (Chapter 3).